<p>Subrata Banik has uploaded this change for <strong>review</strong>.</p><p><a href="https://review.coreboot.org/20942">View Change</a></p><pre style="font-family: monospace,monospace; white-space: pre-wrap;">soc/intel/cannonlake: Remove unused systemagent registers<br><br>This patch to make code cleaner and remove unused systemagent<br>register macros. [same as KBL implementation]<br><br>Change-Id: I13b9c83097fc98183ea138c9087b5fc7834efd58<br>Signed-off-by: Subrata Banik <subrata.banik@intel.com><br>---<br>M src/soc/intel/cannonlake/include/soc/systemagent.h<br>1 file changed, 0 insertions(+), 58 deletions(-)<br><br></pre><pre style="font-family: monospace,monospace; white-space: pre-wrap;">git pull ssh://review.coreboot.org:29418/coreboot refs/changes/42/20942/1</pre><pre style="font-family: monospace,monospace; white-space: pre-wrap;">diff --git a/src/soc/intel/cannonlake/include/soc/systemagent.h b/src/soc/intel/cannonlake/include/soc/systemagent.h<br>index 09b4b32..1902314 100644<br>--- a/src/soc/intel/cannonlake/include/soc/systemagent.h<br>+++ b/src/soc/intel/cannonlake/include/soc/systemagent.h<br>@@ -19,36 +19,11 @@<br> #define SOC_CANNONLAKE_SYSTEMAGENT_H<br> <br> #include <intelblocks/systemagent.h><br>-#include <soc/iomap.h><br> <br> /* Device 0:0.0 PCI configuration space */<br> <br> #define EPBAR 0x40<br>-#define PCIEXBAR 0x60<br> #define DMIBAR 0x68<br>-#define GGC 0x50 /* GMCH Graphics Control */<br>-#define DEVEN 0x54 /* Device Enable */<br>-#define DEVEN_D7EN (1 << 14)<br>-#define DEVEN_D4EN (1 << 7)<br>-#define DEVEN_D3EN (1 << 5)<br>-#define DEVEN_D2EN (1 << 4)<br>-#define DEVEN_D1F0EN (1 << 3)<br>-#define DEVEN_D1F1EN (1 << 2)<br>-#define DEVEN_D1F2EN (1 << 1)<br>-#define DEVEN_D0EN (1 << 0)<br>-#define DPR 0x5c<br>-#define DPR_EPM (1 << 2)<br>-#define DPR_PRS (1 << 1)<br>-#define DPR_SIZE_MASK 0xff0<br>-<br>-#define PAM0 0x80<br>-#define PAM1 0x81<br>-#define PAM2 0x82<br>-#define PAM3 0x83<br>-#define PAM4 0x84<br>-#define PAM5 0x85<br>-#define PAM6 0x86<br>-<br> #define SMRAM 0x88 /* System Management RAM Control */<br> #define D_OPEN (1 << 6)<br> #define D_CLS (1 << 5)<br>@@ -56,46 +31,13 @@<br> #define G_SMRAME (1 << 3)<br> #define C_BASE_SEG ((0 << 2) | (1 << 1) | (0 << 0))<br> <br>-#define MESEG_BASE 0x70 /* Management Engine Base. */<br>-#define MESEG_LIMIT 0x78 /* Management Engine Limit. */<br>-#define TOM 0xa0 /* Top of DRAM in memory controller space. */<br>-#define SKPAD 0xdc /* Scratchpad Data */<br>-<br>-/* MCHBAR */<br>-<br>-#define MCHBAR8(x) (*(volatile u8 *)(MCH_BASE_ADDRESS + x))<br>-#define MCHBAR16(x) (*(volatile u16 *)(MCH_BASE_ADDRESS + x))<br>-#define MCHBAR32(x) (*(volatile u32 *)(MCH_BASE_ADDRESS + x))<br>-<br>-#define MCHBAR_PEI_VERSION 0x5034<br>-#define REMAPBASE 0x5090 /* Remap base. */<br>-#define REMAPLIMIT 0x5098 /* Remap limit. */<br> #define BIOS_RESET_CPL 0x5da8<br> #define EDRAMBAR 0x5408<br>-#define MCH_PAIR 0x5418<br> #define REGBAR 0x5420<br> <br> #define MCH_PKG_POWER_LIMIT_LO 0x59a0<br> #define MCH_PKG_POWER_LIMIT_HI 0x59a4<br> #define MCH_DDR_POWER_LIMIT_LO 0x58e0<br> #define MCH_DDR_POWER_LIMIT_HI 0x58e4<br>-<br>-/* PCODE MMIO communications live in the MCHBAR. */<br>-#define BIOS_MAILBOX_INTERFACE 0x5da4<br>-#define MAILBOX_RUN_BUSY (1 << 31)<br>-/* Errors are returned back in bits 7:0. */<br>-#define MAILBOX_BIOS_ERROR_NONE 0<br>-#define MAILBOX_BIOS_ERROR_INVALID_COMMAND 1<br>-#define MAILBOX_BIOS_ERROR_TIMEOUT 2<br>-#define MAILBOX_BIOS_ERROR_ILLEGAL_DATA 3<br>-#define MAILBOX_BIOS_ERROR_RESERVED 4<br>-#define MAILBOX_BIOS_ERROR_ILLEGAL_VR_ID 5<br>-#define MAILBOX_BIOS_ERROR_VR_INTERFACE_LOCKED 6<br>-#define MAILBOX_BIOS_ERROR_VR_ERROR 7<br>-/* Data is passed through bits 31:0 of the data register. */<br>-#define BIOS_MAILBOX_DATA 0x5da0<br>-<br>-/* System Agent identification */<br>-u8 systemagent_revision(void);<br> <br> #endif<br></pre><p>To view, visit <a href="https://review.coreboot.org/20942">change 20942</a>. To unsubscribe, visit <a href="https://review.coreboot.org/settings">settings</a>.</p><div itemscope itemtype="http://schema.org/EmailMessage"><div itemscope itemprop="action" itemtype="http://schema.org/ViewAction"><link itemprop="url" href="https://review.coreboot.org/20942"/><meta itemprop="name" content="View Change"/></div></div>
<div style="display:none"> Gerrit-Project: coreboot </div>
<div style="display:none"> Gerrit-Branch: master </div>
<div style="display:none"> Gerrit-MessageType: newchange </div>
<div style="display:none"> Gerrit-Change-Id: I13b9c83097fc98183ea138c9087b5fc7834efd58 </div>
<div style="display:none"> Gerrit-Change-Number: 20942 </div>
<div style="display:none"> Gerrit-PatchSet: 1 </div>
<div style="display:none"> Gerrit-Owner: Subrata Banik <subrata.banik@intel.com> </div>