<p>Patrick Rudolph has uploaded this change for <strong>review</strong>.</p><p><a href="https://review.coreboot.org/20926">View Change</a></p><pre style="font-family: monospace,monospace; white-space: pre-wrap;">nb/intel/sandybridge/early_init: Add static PHY init<br><br>Write PEG PHY registers to improve PEG on IvyBridge.<br>For PCIe Gen3 additional training sequence is required, but<br>for PCIe Gen2 static PHY configuration should work fine.<br><br>Needs test on all platforms.<br><br>Change-Id: If66eba3d717c579228876467096bbada20732533<br>Signed-off-by: Patrick Rudolph <siro@das-labor.org><br>---<br>M src/northbridge/intel/sandybridge/early_init.c<br>1 file changed, 62 insertions(+), 0 deletions(-)<br><br></pre><pre style="font-family: monospace,monospace; white-space: pre-wrap;">git pull ssh://review.coreboot.org:29418/coreboot refs/changes/26/20926/1</pre><pre style="font-family: monospace,monospace; white-space: pre-wrap;">diff --git a/src/northbridge/intel/sandybridge/early_init.c b/src/northbridge/intel/sandybridge/early_init.c<br>index 3580f35..f1d9efe 100644<br>--- a/src/northbridge/intel/sandybridge/early_init.c<br>+++ b/src/northbridge/intel/sandybridge/early_init.c<br>@@ -150,6 +150,65 @@<br>   MCHBAR32(0x5418) = reg32;<br> }<br> <br>+/* Static PHY configuration for IvyBridge */<br>+static void ivybridge_peg_phy(void)<br>+{<br>+    u32 tmp;<br>+<br>+  struct pcie_config {<br>+         u16 reg;<br>+             u32 and_mask;<br>+                u32 or_mask;<br>+ };<br>+<br>+        static const struct pcie_config lanes[] = {<br>+          {0x0a00, 0xf0d9ffc1, 0x0324001a},<br>+            {0x0a04, 0xfff9e7ff, 0x00021800},<br>+    };<br>+   static const struct pcie_config bundles[] = {<br>+                {0x0700, 0x04177ff7, 0x09e88008},<br>+            {0x0da0, 0x80F080F0, 0x27082708},<br>+            {0x0900, 0xf3ffffff, 0x00000000},<br>+            {0x0904, 0x8000f000, 0x2a1804a2},<br>+            {0x0908, 0x27ffffff, 0x50000000},<br>+            {0x090c, 0xc111f81f, 0x0ea00120},<br>+            {0x0910, 0xffffc03f, 0x00000340},<br>+            {0x0914, 0x77c21bff, 0x8815a400},<br>+    };<br>+   static const struct pcie_config single[] = {<br>+         {0x0308, 0xff80ff00, 0x0012006c},<br>+            {0x0314, 0xff80ffff, 0x00130000},<br>+            {0x0dd8, 0xffffbfff, 0x00004000},<br>+    };<br>+<br>+        for (size_t j = 0; j < ARRAY_SIZE(lanes); j++)<br>+            for (size_t i = 0; i < 16; i++) {<br>+                 const u16 reg = lanes[j].reg + i * 0x10;<br>+<br>+                  tmp = pci_read_config32(PCI_DEV(0, 1, 0), reg);<br>+                      tmp &= lanes[j].and_mask;<br>+                        tmp |= lanes[j].or_mask;<br>+                     pci_write_config32(PCI_DEV(0, 1, 0), reg, tmp);<br>+              }<br>+<br>+ for (size_t j = 0; j < ARRAY_SIZE(bundles); j++)<br>+          for (size_t i = 0; i < 8; i++) {<br>+                  const u16 reg = bundles[j].reg + i * 0x20;<br>+<br>+                        tmp = pci_read_config32(PCI_DEV(0, 1, 0), reg);<br>+                      tmp &= bundles[j].and_mask;<br>+                      tmp |= bundles[j].or_mask;<br>+                   pci_write_config32(PCI_DEV(0, 1, 0), reg, tmp);<br>+              }<br>+<br>+ for (size_t j = 0; j < ARRAY_SIZE(single); j++) {<br>+         tmp = pci_read_config32(PCI_DEV(0, 1, 0), single[j].reg);<br>+            tmp &= single[j].and_mask;<br>+               tmp |= single[j].or_mask;<br>+            pci_write_config32(PCI_DEV(0, 1, 0), single[j].reg, tmp);<br>+    }<br>+}<br>+<br> static void start_peg_link_training(void)<br> {<br>      u32 tmp;<br>@@ -162,6 +221,9 @@<br>                 IS_ENABLED(CONFIG_HAVE_MRC))<br>          return;<br> <br>+   /* Configure PEG10/PEG11/PEG12 PHY */<br>+        ivybridge_peg_phy();<br>+<br>       deven = pci_read_config32(PCI_DEV(0, 0, 0), DEVEN);<br> <br>        if (deven & DEVEN_PEG10) {<br></pre><p>To view, visit <a href="https://review.coreboot.org/20926">change 20926</a>. To unsubscribe, visit <a href="https://review.coreboot.org/settings">settings</a>.</p><div itemscope itemtype="http://schema.org/EmailMessage"><div itemscope itemprop="action" itemtype="http://schema.org/ViewAction"><link itemprop="url" href="https://review.coreboot.org/20926"/><meta itemprop="name" content="View Change"/></div></div>

<div style="display:none"> Gerrit-Project: coreboot </div>
<div style="display:none"> Gerrit-Branch: master </div>
<div style="display:none"> Gerrit-MessageType: newchange </div>
<div style="display:none"> Gerrit-Change-Id: If66eba3d717c579228876467096bbada20732533 </div>
<div style="display:none"> Gerrit-Change-Number: 20926 </div>
<div style="display:none"> Gerrit-PatchSet: 1 </div>
<div style="display:none"> Gerrit-Owner: Patrick Rudolph <siro@das-labor.org> </div>