<p>Marc Jones has uploaded this change for <strong>review</strong>.</p><p><a href="https://review.coreboot.org/20912">View Change</a></p><pre style="font-family: monospace,monospace; white-space: pre-wrap;">stoneyridge: Rename hudson to southbridge<br><br>Simplify funciton names and remove reference to hudson in stoneyridge.<br>The southbridge in Stoney Ridge is Kern and hudson naming is<br>no longer accurate.<br><br>BUG=b:62200157<br>BRANCH=none<br>TEST=Build and booted on Kahlee.<br><br>Change-Id: Ide7a72dae69b881997101f1e37a1ac739901744d<br>Signed-off-by: Marc Jones <marcj303@gmail.com><br>---<br>M src/mainboard/amd/gardenia/BiosCallOuts.c<br>M src/mainboard/amd/gardenia/bootblock/BiosCallOuts.c<br>M src/mainboard/amd/gardenia/mptable.c<br>M src/mainboard/google/kahlee/BiosCallOuts.c<br>M src/mainboard/google/kahlee/bootblock/BiosCallOuts.c<br>M src/mainboard/google/kahlee/bootblock/bootblock.c<br>M src/mainboard/google/kahlee/ec.c<br>M src/mainboard/google/kahlee/gpio.c<br>M src/mainboard/google/kahlee/mptable.c<br>M src/soc/amd/common/def_callouts.c<br>M src/soc/amd/common/dimmSpd.h<br>M src/soc/amd/stoneyridge/Makefile.inc<br>M src/soc/amd/stoneyridge/acpi.c<br>M src/soc/amd/stoneyridge/acpi/fch.asl<br>M src/soc/amd/stoneyridge/bootblock/bootblock.c<br>M src/soc/amd/stoneyridge/chip.c<br>M src/soc/amd/stoneyridge/dimmSpd.c<br>M src/soc/amd/stoneyridge/early_setup.c<br>M src/soc/amd/stoneyridge/enable_usbdebug.c<br>M src/soc/amd/stoneyridge/hda.c<br>M src/soc/amd/stoneyridge/include/soc/smi.h<br>R src/soc/amd/stoneyridge/include/soc/southbridge.h<br>M src/soc/amd/stoneyridge/lpc.c<br>M src/soc/amd/stoneyridge/reset.c<br>M src/soc/amd/stoneyridge/romstage.c<br>M src/soc/amd/stoneyridge/sata.c<br>M src/soc/amd/stoneyridge/sm.c<br>M src/soc/amd/stoneyridge/smbus_spd.c<br>M src/soc/amd/stoneyridge/smi.c<br>M src/soc/amd/stoneyridge/smi_util.c<br>M src/soc/amd/stoneyridge/smihandler.c<br>R src/soc/amd/stoneyridge/southbridge.c<br>M src/soc/amd/stoneyridge/uart.c<br>M src/soc/amd/stoneyridge/usb.c<br>34 files changed, 111 insertions(+), 115 deletions(-)<br><br></pre><pre style="font-family: monospace,monospace; white-space: pre-wrap;">git pull ssh://review.coreboot.org:29418/coreboot refs/changes/12/20912/1</pre><pre style="font-family: monospace,monospace; white-space: pre-wrap;">diff --git a/src/mainboard/amd/gardenia/BiosCallOuts.c b/src/mainboard/amd/gardenia/BiosCallOuts.c<br>index fd03f4e..31681cb 100644<br>--- a/src/mainboard/amd/gardenia/BiosCallOuts.c<br>+++ b/src/mainboard/amd/gardenia/BiosCallOuts.c<br>@@ -17,7 +17,7 @@<br> #include <BiosCallOuts.h><br> #include <FchPlatform.h><br> #include <soc/imc.h><br>-#include <soc/hudson.h><br>+#include <soc/southbridge.h><br> #include <stdlib.h><br> <br> static AGESA_STATUS fch_initenv(UINT32 Func, UINTN FchData, VOID *ConfigPtr)<br>diff --git a/src/mainboard/amd/gardenia/bootblock/BiosCallOuts.c b/src/mainboard/amd/gardenia/bootblock/BiosCallOuts.c<br>index a54078a..b0a3e23 100644<br>--- a/src/mainboard/amd/gardenia/bootblock/BiosCallOuts.c<br>+++ b/src/mainboard/amd/gardenia/bootblock/BiosCallOuts.c<br>@@ -16,7 +16,7 @@<br> #include <AGESA.h><br> #include <BiosCallOuts.h><br> #include <FchPlatform.h><br>-#include <soc/hudson.h><br>+#include <soc/southbridge.h><br> #include <stdlib.h><br> <br> static const GPIO_CONTROL oem_gardenia_gpio[] = {<br>@@ -53,8 +53,8 @@<br> FCH_RESET_DATA_BLOCK *FchParams_reset;<br> FchParams_reset = (FCH_RESET_DATA_BLOCK *)FchData;<br> printk(BIOS_DEBUG, "Fch OEM config in INIT RESET ");<br>- FchParams_reset->FchReset.SataEnable = hudson_sata_enable();<br>- FchParams_reset->FchReset.IdeEnable = hudson_ide_enable();<br>+ FchParams_reset->FchReset.SataEnable = sb_sata_enable();<br>+ FchParams_reset->FchReset.IdeEnable = sb_ide_enable();<br> FchParams_reset->EarlyOemGpioTable = oem_gardenia_gpio;<br> printk(BIOS_DEBUG, "Done\n");<br> }<br>diff --git a/src/mainboard/amd/gardenia/mptable.c b/src/mainboard/amd/gardenia/mptable.c<br>index f32b8da..c329558 100644<br>--- a/src/mainboard/amd/gardenia/mptable.c<br>+++ b/src/mainboard/amd/gardenia/mptable.c<br>@@ -23,7 +23,7 @@<br> #include <cpu/amd/amdfam15.h><br> #include <arch/cpu.h><br> #include <cpu/x86/lapic.h><br>-#include <soc/hudson.h><br>+#include <soc/southbridge.h><br> #include <amd_pci_util.h><br> <br> static void smp_add_mpc_entry(struct mp_config_table *mc, unsigned int length)<br>diff --git a/src/mainboard/google/kahlee/BiosCallOuts.c b/src/mainboard/google/kahlee/BiosCallOuts.c<br>index 7bef2f3..b32a984 100644<br>--- a/src/mainboard/google/kahlee/BiosCallOuts.c<br>+++ b/src/mainboard/google/kahlee/BiosCallOuts.c<br>@@ -16,7 +16,7 @@<br> #include <AGESA.h><br> #include <BiosCallOuts.h><br> #include <FchPlatform.h><br>-#include <soc/hudson.h><br>+#include <soc/southbridge.h><br> #include <stdlib.h><br> <br> extern const GPIO_CONTROL oem_kahlee_gpio[];<br>diff --git a/src/mainboard/google/kahlee/bootblock/BiosCallOuts.c b/src/mainboard/google/kahlee/bootblock/BiosCallOuts.c<br>index b70db1d..162fc50 100644<br>--- a/src/mainboard/google/kahlee/bootblock/BiosCallOuts.c<br>+++ b/src/mainboard/google/kahlee/bootblock/BiosCallOuts.c<br>@@ -16,7 +16,7 @@<br> #include <AGESA.h><br> #include <BiosCallOuts.h><br> #include <FchPlatform.h><br>-#include <soc/hudson.h><br>+#include <soc/southbridge.h><br> #include <stdlib.h><br> <br> extern const GPIO_CONTROL oem_kahlee_gpio[];<br>@@ -29,8 +29,8 @@<br> FCH_RESET_DATA_BLOCK *FchParams_reset;<br> FchParams_reset = (FCH_RESET_DATA_BLOCK *)FchData;<br> printk(BIOS_DEBUG, "Fch OEM config in INIT RESET ");<br>- FchParams_reset->FchReset.SataEnable = hudson_sata_enable();<br>- FchParams_reset->FchReset.IdeEnable = hudson_ide_enable();<br>+ FchParams_reset->FchReset.SataEnable = sb_sata_enable();<br>+ FchParams_reset->FchReset.IdeEnable = sb_ide_enable();<br> FchParams_reset->EarlyOemGpioTable = oem_kahlee_gpio;<br> printk(BIOS_DEBUG, "Done\n");<br> }<br>diff --git a/src/mainboard/google/kahlee/bootblock/bootblock.c b/src/mainboard/google/kahlee/bootblock/bootblock.c<br>index caa24d5..3041a8f 100644<br>--- a/src/mainboard/google/kahlee/bootblock/bootblock.c<br>+++ b/src/mainboard/google/kahlee/bootblock/bootblock.c<br>@@ -15,7 +15,7 @@<br> <br> #include <bootblock_common.h><br> #include <ec.h><br>-#include <soc/hudson.h><br>+#include <soc/southbridge.h><br> <br> void bootblock_mainboard_init(void)<br> {<br>@@ -23,5 +23,5 @@<br> mainboard_ec_init();<br> <br> /* Setup TPM decode before verstage */<br>- hudson_tpm_decode_spi();<br>+ sb_tpm_decode_spi();<br> }<br>diff --git a/src/mainboard/google/kahlee/ec.c b/src/mainboard/google/kahlee/ec.c<br>index 71c6e10..75ed1fa 100644<br>--- a/src/mainboard/google/kahlee/ec.c<br>+++ b/src/mainboard/google/kahlee/ec.c<br>@@ -18,7 +18,7 @@<br> #include <ec/google/chromeec/ec.h><br> #include "ec.h"<br> #include <rules.h><br>-#include <soc/hudson.h><br>+#include <soc/southbridge.h><br> <br> static void ramstage_ec_init(void)<br> {<br>diff --git a/src/mainboard/google/kahlee/gpio.c b/src/mainboard/google/kahlee/gpio.c<br>index 56a5e3d..b815ac3 100644<br>--- a/src/mainboard/google/kahlee/gpio.c<br>+++ b/src/mainboard/google/kahlee/gpio.c<br>@@ -15,7 +15,7 @@<br> <br> #include <AGESA.h><br> #include <FchPlatform.h><br>-#include <soc/hudson.h><br>+#include <soc/southbridge.h><br> #include <stdlib.h><br> <br> const GPIO_CONTROL oem_kahlee_gpio[] = {<br>diff --git a/src/mainboard/google/kahlee/mptable.c b/src/mainboard/google/kahlee/mptable.c<br>index f32b8da..c329558 100644<br>--- a/src/mainboard/google/kahlee/mptable.c<br>+++ b/src/mainboard/google/kahlee/mptable.c<br>@@ -23,7 +23,7 @@<br> #include <cpu/amd/amdfam15.h><br> #include <arch/cpu.h><br> #include <cpu/x86/lapic.h><br>-#include <soc/hudson.h><br>+#include <soc/southbridge.h><br> #include <amd_pci_util.h><br> <br> static void smp_add_mpc_entry(struct mp_config_table *mc, unsigned int length)<br>diff --git a/src/soc/amd/common/def_callouts.c b/src/soc/amd/common/def_callouts.c<br>index f923b13..fda0013 100644<br>--- a/src/soc/amd/common/def_callouts.c<br>+++ b/src/soc/amd/common/def_callouts.c<br>@@ -23,7 +23,7 @@<br> #include <agesawrapper.h><br> #include <BiosCallOuts.h><br> #include <dimmSpd.h><br>-#include <soc/hudson.h><br>+#include <soc/southbridge.h><br> <br> AGESA_STATUS GetBiosCallout(UINT32 Func, UINTN Data, VOID *ConfigPtr)<br> {<br>diff --git a/src/soc/amd/common/dimmSpd.h b/src/soc/amd/common/dimmSpd.h<br>index ea7a7e9..75a7990 100644<br>--- a/src/soc/amd/common/dimmSpd.h<br>+++ b/src/soc/amd/common/dimmSpd.h<br>@@ -20,7 +20,7 @@<br> AmdMemoryReadSPD(IN UINT32 Func, IN UINTN Data,<br> IN OUT AGESA_READ_SPD_PARAMS *SpdData);<br> <br>-int hudson_readSpd(int spdAddress, char *buf, size_t len);<br>+int sb_readSpd(int spdAddress, char *buf, size_t len);<br> int smbus_readSpd(int spdAddress, char *buf, size_t len);<br> <br> #endif<br>diff --git a/src/soc/amd/stoneyridge/Makefile.inc b/src/soc/amd/stoneyridge/Makefile.inc<br>index 30006b3..8fa5afb 100644<br>--- a/src/soc/amd/stoneyridge/Makefile.inc<br>+++ b/src/soc/amd/stoneyridge/Makefile.inc<br>@@ -66,7 +66,7 @@<br> ramstage-y += fixme.c<br> ramstage-y += gpio.c<br> ramstage-y += hda.c<br>-ramstage-y += hudson.c<br>+ramstage-y += southbridge.c<br> ramstage-$(CONFIG_STONEYRIDGE_IMC_FWM) += imc.c<br> ramstage-y += lpc.c<br> ramstage-y += model_15_init.c<br>diff --git a/src/soc/amd/stoneyridge/acpi.c b/src/soc/amd/stoneyridge/acpi.c<br>index 327faef..adf906b 100644<br>--- a/src/soc/amd/stoneyridge/acpi.c<br>+++ b/src/soc/amd/stoneyridge/acpi.c<br>@@ -28,7 +28,7 @@<br> #include <device/device.h><br> #include <device/pci.h><br> #include <soc/acpi.h><br>-#include <soc/hudson.h><br>+#include <soc/southbridge.h><br> #include <soc/nvs.h><br> #include <soc/smi.h><br> <br>@@ -85,7 +85,7 @@<br> fadt->dsdt = (u32) dsdt;<br> fadt->model = 0; /* reserved, should be 0 ACPI 3.0 */<br> fadt->preferred_pm_profile = FADT_PM_PROFILE;<br>- fadt->sci_int = 9; /* HUDSON - IRQ 09 - ACPI SCI */<br>+ fadt->sci_int = 9; /* IRQ 09 - ACPI SCI */<br> <br> if (IS_ENABLED(CONFIG_HAVE_SMI_HANDLER)) {<br> fadt->smi_cmd = ACPI_SMI_CTL_PORT;<br>@@ -112,7 +112,7 @@<br> fadt->pm2_cnt_blk = 0x0000;<br> fadt->pm_tmr_blk = ACPI_PM_TMR_BLK;<br> fadt->gpe0_blk = ACPI_GPE0_BLK;<br>- fadt->gpe1_blk = 0x0000; /* No gpe1 block in hudson */<br>+ fadt->gpe1_blk = 0x0000; /* No gpe1 block */<br> <br> fadt->pm1_evt_len = 4; /* 32 bits */<br> fadt->pm1_cnt_len = 2; /* 16 bits */<br>diff --git a/src/soc/amd/stoneyridge/acpi/fch.asl b/src/soc/amd/stoneyridge/acpi/fch.asl<br>index 1e0c889..6a815b3 100644<br>--- a/src/soc/amd/stoneyridge/acpi/fch.asl<br>+++ b/src/soc/amd/stoneyridge/acpi/fch.asl<br>@@ -157,7 +157,7 @@<br> <br> #if IS_ENABLED(CONFIG_ACPI_ENABLE_THERMAL_ZONE)<br> /* TODO: It is unstable. */<br>- #include "acpi/AmdImc.asl" /* Hudson IMC function */<br>+ #include "acpi/AmdImc.asl"<br> ITZE() /* enable IMC Fan Control*/<br> #endif<br> } /* End Method(_SB._INI) */<br>diff --git a/src/soc/amd/stoneyridge/bootblock/bootblock.c b/src/soc/amd/stoneyridge/bootblock/bootblock.c<br>index 473b118..3f01603 100644<br>--- a/src/soc/amd/stoneyridge/bootblock/bootblock.c<br>+++ b/src/soc/amd/stoneyridge/bootblock/bootblock.c<br>@@ -20,7 +20,7 @@<br> #include <bootblock_common.h><br> #include <agesawrapper.h><br> #include <agesawrapper_call.h><br>-#include <soc/hudson.h><br>+#include <soc/southbridge.h><br> <br> asmlinkage void bootblock_c_entry(uint64_t base_timestamp)<br> {<br>@@ -47,7 +47,7 @@<br> <br> post_code(0x90);<br> if (CONFIG_STONEYRIDGE_UART)<br>- configure_hudson_uart();<br>+ configure_stoneyridge_uart();<br> }<br> <br> void bootblock_soc_init(void)<br>diff --git a/src/soc/amd/stoneyridge/chip.c b/src/soc/amd/stoneyridge/chip.c<br>index 487201b..14f76b7 100644<br>--- a/src/soc/amd/stoneyridge/chip.c<br>+++ b/src/soc/amd/stoneyridge/chip.c<br>@@ -18,7 +18,7 @@<br> #include <cpu/cpu.h><br> #include <device/device.h><br> #include <device/pci.h><br>-#include <soc/hudson.h><br>+#include <soc/southbridge.h><br> #include <soc/northbridge.h><br> <br> static void cpu_bus_init(device_t dev)<br>@@ -59,17 +59,17 @@<br> else if (dev->path.type == DEVICE_PATH_CPU_CLUSTER)<br> dev->ops = &cpu_bus_ops;<br> else if (dev->path.type == DEVICE_PATH_PCI)<br>- hudson_enable(dev);<br>+ sb_enable(dev);<br> }<br> <br> static void soc_init(void *chip_info)<br> {<br>- hudson_init(chip_info);<br>+ southbridge_init(chip_info);<br> }<br> <br> static void soc_final(void *chip_info)<br> {<br>- hudson_final(chip_info);<br>+ southbridge_final(chip_info);<br> fam15_finalize(chip_info);<br> }<br> <br>diff --git a/src/soc/amd/stoneyridge/dimmSpd.c b/src/soc/amd/stoneyridge/dimmSpd.c<br>index a69b80c..ace22bb 100644<br>--- a/src/soc/amd/stoneyridge/dimmSpd.c<br>+++ b/src/soc/amd/stoneyridge/dimmSpd.c<br>@@ -43,7 +43,7 @@<br> [info->SocketId][info->MemChannelId][info->DimmId];<br> if (spdAddress == 0)<br> return AGESA_ERROR;<br>- int err = hudson_readSpd(spdAddress, (void *)info->Buffer, 128);<br>+ int err = sb_readSpd(spdAddress, (void *)info->Buffer, 128);<br> if (err)<br> return AGESA_ERROR;<br> return AGESA_SUCCESS;<br>diff --git a/src/soc/amd/stoneyridge/early_setup.c b/src/soc/amd/stoneyridge/early_setup.c<br>index c1a2978..5166a7f 100644<br>--- a/src/soc/amd/stoneyridge/early_setup.c<br>+++ b/src/soc/amd/stoneyridge/early_setup.c<br>@@ -21,13 +21,13 @@<br> #include <reset.h><br> #include <arch/cpu.h><br> #include <cbmem.h><br>-#include <soc/hudson.h><br>+#include <soc/southbridge.h><br> #include <soc/pci_devs.h><br> #include <Fch/Fch.h><br> #include <cpu/x86/msr.h><br> #include <delay.h><br> <br>-void configure_hudson_uart(void)<br>+void configure_stoneyridge_uart(void)<br> {<br> u8 byte;<br> <br>@@ -50,7 +50,7 @@<br> + 0x88, 0x01);<br> }<br> <br>-void hudson_pci_port80(void)<br>+void sb_pci_port80(void)<br> {<br> u8 byte;<br> pci_devfn_t dev;<br>@@ -62,7 +62,7 @@<br> pci_write_config8(dev, 0x4a, byte);<br> }<br> <br>-void hudson_lpc_port80(void)<br>+void sb_lpc_port80(void)<br> {<br> u8 byte;<br> pci_devfn_t dev;<br>@@ -81,7 +81,7 @@<br> pci_write_config8(dev, 0x4a, byte);<br> }<br> <br>-void hudson_lpc_decode(void)<br>+void sb_lpc_decode(void)<br> {<br> pci_devfn_t dev;<br> u32 tmp = 0;<br>@@ -222,7 +222,7 @@<br> return nvram_pos;<br> }<br> <br>-void hudson_clk_output_48Mhz(void)<br>+void sb_clk_output_48Mhz(void)<br> {<br> u32 ctrl;<br> <br>@@ -237,7 +237,7 @@<br> write32((void *)(ACPI_MMIO_BASE + MISC_BASE + FCH_MISC_REG40), ctrl);<br> }<br> <br>-static uintptr_t hudson_spibase(void)<br>+static uintptr_t sb_spibase(void)<br> {<br> /* Make sure the base address is predictable */<br> device_t dev = PCI_DEV(0, PCU_DEV, LPC_FUNC);<br>@@ -256,9 +256,9 @@<br> return (uintptr_t)base;<br> }<br> <br>-void hudson_set_spi100(u16 norm, u16 fast, u16 alt, u16 tpm)<br>+void sb_set_spi100(u16 norm, u16 fast, u16 alt, u16 tpm)<br> {<br>- uintptr_t base = hudson_spibase();<br>+ uintptr_t base = sb_spibase();<br> write16((void *)base + SPI100_SPEED_CONFIG,<br> (norm << SPI_NORM_SPEED_NEW_SH) |<br> (fast << SPI_FAST_SPEED_NEW_SH) |<br>@@ -267,33 +267,32 @@<br> write16((void *)base + SPI100_ENABLE, SPI_USE_SPI100);<br> }<br> <br>-void hudson_disable_4dw_burst(void)<br>+void sb_disable_4dw_burst(void)<br> {<br>- uintptr_t base = hudson_spibase();<br>+ uintptr_t base = sb_spibase();<br> write16((void *)base + SPI100_HOST_PREF_CONFIG,<br> read16((void *)base + SPI100_HOST_PREF_CONFIG)<br> & ~SPI_RD4DW_EN_HOST);<br> }<br> <br>-/* Hudson 1-3 only. For Hudson 1, call with fast=1 */<br>-void hudson_set_readspeed(u16 norm, u16 fast)<br>+void sb_set_readspeed(u16 norm, u16 fast)<br> {<br>- uintptr_t base = hudson_spibase();<br>+ uintptr_t base = sb_spibase();<br> write16((void *)base + SPI_CNTRL1, (read16((void *)base + SPI_CNTRL1)<br> & ~SPI_CNTRL1_SPEED_MASK)<br> | (norm << SPI_NORM_SPEED_SH)<br> | (fast << SPI_FAST_SPEED_SH));<br> }<br> <br>-void hudson_read_mode(u32 mode)<br>+void sb_read_mode(u32 mode)<br> {<br>- uintptr_t base = hudson_spibase();<br>+ uintptr_t base = sb_spibase();<br> write32((void *)base + SPI_CNTRL0,<br> (read32((void *)base + SPI_CNTRL0)<br> & ~SPI_READ_MODE_MASK) | mode);<br> }<br> <br>-void hudson_tpm_decode_spi(void)<br>+void sb_tpm_decode_spi(void)<br> {<br> device_t dev = PCI_DEV(0, PCU_DEV, LPC_FUNC); /* LPC device */<br> <br>@@ -308,10 +307,10 @@<br> * Hardware should enable LPC ROM by pin straps. This function does not<br> * handle the theoretically possible PCI ROM, FWH, or SPI ROM configurations.<br> *<br>- * The HUDSON power-on default is to map 512K ROM space.<br>+ * The southbridge power-on default is to map 512K ROM space.<br> *<br> */<br>-void hudson_enable_rom(void)<br>+void sb_enable_rom(void)<br> {<br> u8 reg8;<br> pci_devfn_t dev;<br>@@ -345,7 +344,7 @@<br> <br> void bootblock_fch_early_init(void)<br> {<br>- hudson_enable_rom();<br>- hudson_lpc_port80();<br>- hudson_lpc_decode();<br>+ sb_enable_rom();<br>+ sb_lpc_port80();<br>+ sb_lpc_decode();<br> }<br>diff --git a/src/soc/amd/stoneyridge/enable_usbdebug.c b/src/soc/amd/stoneyridge/enable_usbdebug.c<br>index 7ed6721..efe34e5 100644<br>--- a/src/soc/amd/stoneyridge/enable_usbdebug.c<br>+++ b/src/soc/amd/stoneyridge/enable_usbdebug.c<br>@@ -20,7 +20,7 @@<br> #include <arch/io.h><br> #include <device/pci_ehci.h><br> #include <device/pci_def.h><br>-#include <soc/hudson.h><br>+#include <soc/southbridge.h><br> <br> #define DEBUGPORT_MISC_CONTROL 0x80<br> <br>diff --git a/src/soc/amd/stoneyridge/hda.c b/src/soc/amd/stoneyridge/hda.c<br>index 2623236..b41b999 100644<br>--- a/src/soc/amd/stoneyridge/hda.c<br>+++ b/src/soc/amd/stoneyridge/hda.c<br>@@ -20,7 +20,7 @@<br> #include <device/pci_ops.h><br> #include <arch/io.h><br> #include <delay.h><br>-#include <soc/hudson.h><br>+#include <soc/southbridge.h><br> <br> static const unsigned short pci_device_ids[] = {<br> PCI_DEVICE_ID_AMD_SB900_HDA,<br>diff --git a/src/soc/amd/stoneyridge/include/soc/smi.h b/src/soc/amd/stoneyridge/include/soc/smi.h<br>index 7a3c804..193fb0c 100644<br>--- a/src/soc/amd/stoneyridge/include/soc/smi.h<br>+++ b/src/soc/amd/stoneyridge/include/soc/smi.h<br>@@ -54,12 +54,12 @@<br> write16((void *)(SMI_BASE + offset), value);<br> }<br> <br>-void hudson_configure_gevent_smi(uint8_t gevent, uint8_t mode, uint8_t level);<br>-void hudson_disable_gevent_smi(uint8_t gevent);<br>-void hudson_enable_acpi_cmd_smi(void);<br>+void configure_gevent_smi(uint8_t gevent, uint8_t mode, uint8_t level);<br>+void disable_gevent_smi(uint8_t gevent);<br>+void enable_acpi_cmd_smi(void);<br> <br> #ifndef __SMM__<br>-void hudson_enable_smi_generation(void);<br>+void enable_smi_generation(void);<br> #endif<br> <br> #endif /* _SOUTHBRIDGE_AMD_PI_STONEYRIDGE_SMI_H */<br>diff --git a/src/soc/amd/stoneyridge/include/soc/hudson.h b/src/soc/amd/stoneyridge/include/soc/southbridge.h<br>similarity index 88%<br>rename from src/soc/amd/stoneyridge/include/soc/hudson.h<br>rename to src/soc/amd/stoneyridge/include/soc/southbridge.h<br>index 48f5e0d..de481f0 100644<br>--- a/src/soc/amd/stoneyridge/include/soc/hudson.h<br>+++ b/src/soc/amd/stoneyridge/include/soc/southbridge.h<br>@@ -138,13 +138,11 @@<br> #define SPI_READ_MODE_DUAL122 (BIT(30) )<br> #define SPI_READ_MODE_QUAD144 (BIT(30) | BIT(18))<br> #define SPI_READ_MODE_NORMAL66 (BIT(30) | BIT(29) )<br>-/* Nominal and SPI_READ_MODE_FAST_HUDSON1 are the only valid choices for H1 */<br>-#define SPI_READ_MODE_FAST_HUDSON1 ( BIT(18))<br> #define SPI_READ_MODE_FAST (BIT(30) | BIT(29) | BIT(18))<br> #define SPI_ARB_ENABLE BIT(19)<br> <br> #define SPI_CNTRL1 0x0c<br>-/* Use SPI_SPEED_16M-SPI_SPEED_66M below for hudson and bolton */<br>+/* Use SPI_SPEED_16M-SPI_SPEED_66M below for the southbridge */<br> #define SPI_CNTRL1_SPEED_MASK (BIT(15) | BIT(14) | BIT(13) | BIT(12))<br> #define SPI_NORM_SPEED_SH 12<br> #define SPI_FAST_SPEED_SH 8<br>@@ -167,34 +165,34 @@<br> #define SPI100_HOST_PREF_CONFIG 0x2c<br> #define SPI_RD4DW_EN_HOST BIT(15)<br> <br>-static inline int hudson_sata_enable(void)<br>+static inline int sb_sata_enable(void)<br> {<br> /* True if IDE or AHCI. */<br> return (CONFIG_STONEYRIDGE_SATA_MODE == 0) ||<br> (CONFIG_STONEYRIDGE_SATA_MODE == 2);<br> }<br> <br>-static inline int hudson_ide_enable(void)<br>+static inline int sb_ide_enable(void)<br> {<br> /* True if IDE or LEGACY IDE. */<br> return (CONFIG_STONEYRIDGE_SATA_MODE == 0) ||<br> (CONFIG_STONEYRIDGE_SATA_MODE == 3);<br> }<br> <br>-void hudson_enable_rom(void);<br>-void configure_hudson_uart(void);<br>-void hudson_clk_output_48Mhz(void);<br>-void hudson_disable_4dw_burst(void);<br>-void hudson_enable(device_t dev);<br>-void hudson_final(void *chip_info);<br>-void hudson_init(void *chip_info);<br>-void hudson_lpc_port80(void);<br>-void hudson_lpc_decode(void);<br>-void hudson_pci_port80(void);<br>-void hudson_read_mode(u32 mode);<br>-void hudson_set_spi100(u16 norm, u16 fast, u16 alt, u16 tpm);<br>-void hudson_set_readspeed(u16 norm, u16 fast);<br>-void hudson_tpm_decode_spi(void);<br>+void sb_enable_rom(void);<br>+void configure_stoneyridge_uart(void);<br>+void sb_clk_output_48Mhz(void);<br>+void sb_disable_4dw_burst(void);<br>+void sb_enable(device_t dev);<br>+void southbridge_final(void *chip_info);<br>+void southbridge_init(void *chip_info);<br>+void sb_lpc_port80(void);<br>+void sb_lpc_decode(void);<br>+void sb_pci_port80(void);<br>+void sb_read_mode(u32 mode);<br>+void sb_set_spi100(u16 norm, u16 fast, u16 alt, u16 tpm);<br>+void sb_set_readspeed(u16 norm, u16 fast);<br>+void sb_tpm_decode_spi(void);<br> void lpc_wideio_512_window(uint16_t base);<br> void lpc_wideio_16_window(uint16_t base);<br> u8 pm_read8(u8 reg);<br>diff --git a/src/soc/amd/stoneyridge/lpc.c b/src/soc/amd/stoneyridge/lpc.c<br>index fae5c55..75cedfe 100644<br>--- a/src/soc/amd/stoneyridge/lpc.c<br>+++ b/src/soc/amd/stoneyridge/lpc.c<br>@@ -31,7 +31,7 @@<br> #include <pc80/i8259.h><br> #include <soc/acpi.h><br> #include <soc/pci_devs.h><br>-#include <soc/hudson.h><br>+#include <soc/southbridge.h><br> #include <soc/nvs.h><br> #include <vboot/vbnv.h><br> <br>@@ -105,7 +105,7 @@<br> pm_write8(PM_SERIRQ_CONF, byte);<br> }<br> <br>-static void hudson_lpc_read_resources(device_t dev)<br>+static void lpc_read_resources(device_t dev)<br> {<br> struct resource *res;<br> global_nvs_t *gnvs;<br>@@ -141,7 +141,7 @@<br> gnvs = cbmem_add(CBMEM_ID_ACPI_GNVS, sizeof(global_nvs_t));<br> }<br> <br>-static void hudson_lpc_set_resources(struct device *dev)<br>+static void lpc_set_resources(struct device *dev)<br> {<br> struct resource *res;<br> u32 spi_enable_bits;<br>@@ -162,7 +162,7 @@<br> * @param dev the device whose children's resources are to be enabled<br> *<br> */<br>-static void hudson_lpc_enable_childrens_resources(device_t dev)<br>+static void lpc_enable_childrens_resources(device_t dev)<br> {<br> struct bus *link;<br> u32 reg, reg_x;<br>@@ -218,7 +218,7 @@<br> base = res->base;<br> end = resource_end(res);<br> /* find a resource size */<br>- printk(BIOS_DEBUG, "hudson lpc decode:%s, base=0x%08x, end=0x%08x\n",<br>+ printk(BIOS_DEBUG, "Southbridge LPC decode:%s, base=0x%08x, end=0x%08x\n",<br> dev_path(child), base, end);<br> switch (base) {<br> case 0x60: /* KB */<br>@@ -342,10 +342,10 @@<br> pci_write_config8(dev, 0x74, wiosize);<br> }<br> <br>-static void hudson_lpc_enable_resources(device_t dev)<br>+static void lpc_enable_resources(device_t dev)<br> {<br> pci_dev_enable_resources(dev);<br>- hudson_lpc_enable_childrens_resources(dev);<br>+ lpc_enable_childrens_resources(dev);<br> }<br> <br> unsigned long acpi_fill_mcfg(unsigned long current)<br>@@ -359,9 +359,9 @@<br> };<br> <br> static struct device_operations lpc_ops = {<br>- .read_resources = hudson_lpc_read_resources,<br>- .set_resources = hudson_lpc_set_resources,<br>- .enable_resources = hudson_lpc_enable_resources,<br>+ .read_resources = lpc_read_resources,<br>+ .set_resources = lpc_set_resources,<br>+ .enable_resources = lpc_enable_resources,<br> .acpi_inject_dsdt_generator = southbridge_inject_dsdt,<br> .write_acpi_tables = southbridge_write_acpi_tables,<br> .init = lpc_init,<br>diff --git a/src/soc/amd/stoneyridge/reset.c b/src/soc/amd/stoneyridge/reset.c<br>index 8553025..73f944d 100644<br>--- a/src/soc/amd/stoneyridge/reset.c<br>+++ b/src/soc/amd/stoneyridge/reset.c<br>@@ -18,7 +18,7 @@<br> <br> #include <arch/io.h><br> #include <reset.h><br>-#include <soc/hudson.h><br>+#include <soc/southbridge.h><br> <br> #define HT_INIT_CONTROL 0x6c<br> #define HTIC_BIOSR_Detect (1 << 5)<br>diff --git a/src/soc/amd/stoneyridge/romstage.c b/src/soc/amd/stoneyridge/romstage.c<br>index 1380fb7..c69bbf6 100644<br>--- a/src/soc/amd/stoneyridge/romstage.c<br>+++ b/src/soc/amd/stoneyridge/romstage.c<br>@@ -19,7 +19,7 @@<br> #include <agesawrapper.h><br> #include <agesawrapper_call.h><br> #include <soc/northbridge.h><br>-#include <soc/hudson.h><br>+#include <soc/southbridge.h><br> #include <amdblocks/psp.h><br> <br> asmlinkage void car_stage_entry(void)<br>diff --git a/src/soc/amd/stoneyridge/sata.c b/src/soc/amd/stoneyridge/sata.c<br>index bd013c8..e2de3e6 100644<br>--- a/src/soc/amd/stoneyridge/sata.c<br>+++ b/src/soc/amd/stoneyridge/sata.c<br>@@ -20,7 +20,7 @@<br> #include <device/pci_ids.h><br> #include <device/pci_ops.h><br> #include <arch/io.h><br>-#include <soc/hudson.h><br>+#include <soc/southbridge.h><br> <br> <br> static void sata_init(struct device *dev)<br>diff --git a/src/soc/amd/stoneyridge/sm.c b/src/soc/amd/stoneyridge/sm.c<br>index 421151a..0c31a3e 100644<br>--- a/src/soc/amd/stoneyridge/sm.c<br>+++ b/src/soc/amd/stoneyridge/sm.c<br>@@ -24,7 +24,7 @@<br> #include <cpu/x86/lapic.h><br> #include <arch/ioapic.h><br> #include <stdlib.h><br>-#include <soc/hudson.h><br>+#include <soc/southbridge.h><br> #include <soc/smbus.h><br> <br> #define NMI_OFF 0<br>@@ -37,8 +37,8 @@<br> #endif<br> <br> /*<br>-* HUDSON enables all USB controllers by default in SMBUS Control.<br>-* HUDSON enables SATA by default in SMBUS Control.<br>+* The southbridge enables all USB controllers by default in SMBUS Control.<br>+* The southbridge enables SATA by default in SMBUS Control.<br> */<br> <br> static void sm_init(device_t dev)<br>@@ -108,11 +108,11 @@<br> .write_byte = lsmbus_write_byte,<br> };<br> <br>-static void hudson_sm_read_resources(device_t dev)<br>+static void sm_read_resources(device_t dev)<br> {<br> }<br> <br>-static void hudson_sm_set_resources(struct device *dev)<br>+static void sm_set_resources(struct device *dev)<br> {<br> }<br> <br>@@ -120,8 +120,8 @@<br> .set_subsystem = pci_dev_set_subsystem,<br> };<br> static struct device_operations smbus_ops = {<br>- .read_resources = hudson_sm_read_resources,<br>- .set_resources = hudson_sm_set_resources,<br>+ .read_resources = sm_read_resources,<br>+ .set_resources = sm_set_resources,<br> .enable_resources = pci_dev_enable_resources,<br> .init = sm_init,<br> .scan_bus = scan_smbus,<br>diff --git a/src/soc/amd/stoneyridge/smbus_spd.c b/src/soc/amd/stoneyridge/smbus_spd.c<br>index 73e6702..6669ccb 100644<br>--- a/src/soc/amd/stoneyridge/smbus_spd.c<br>+++ b/src/soc/amd/stoneyridge/smbus_spd.c<br>@@ -20,7 +20,7 @@<br> #include <Porting.h><br> #include <AGESA.h><br> #include <amdlib.h><br>-#include <soc/hudson.h><br>+#include <soc/southbridge.h><br> #include <dimmSpd.h><br> <br> /*-----------------------------------------------------------------------------<br>@@ -144,7 +144,7 @@<br> __outbyte(ioBase + 0x0e, 66000000 / 400000 / 4);<br> }<br> <br>-int hudson_readSpd(int spdAddress, char *buf, size_t len)<br>+int sb_readSpd(int spdAddress, char *buf, size_t len)<br> {<br> int ioBase = 0xb00;<br> setupFch(ioBase);<br>diff --git a/src/soc/amd/stoneyridge/smi.c b/src/soc/amd/stoneyridge/smi.c<br>index c92697c..31ca5d1 100644<br>--- a/src/soc/amd/stoneyridge/smi.c<br>+++ b/src/soc/amd/stoneyridge/smi.c<br>@@ -17,7 +17,7 @@<br> }<br> <br> /** Set the EOS bit and enable SMI generation from southbridge */<br>-void hudson_enable_smi_generation(void)<br>+void enable_smi_generation(void)<br> {<br> uint32_t reg = smi_read32(SMI_REG_SMITRIG0);<br> reg &= ~SMITRG0_SMIENB; /* Enable SMI generation */<br>diff --git a/src/soc/amd/stoneyridge/smi_util.c b/src/soc/amd/stoneyridge/smi_util.c<br>index fecaf90..822738c 100644<br>--- a/src/soc/amd/stoneyridge/smi_util.c<br>+++ b/src/soc/amd/stoneyridge/smi_util.c<br>@@ -39,7 +39,7 @@<br> * SMI_MODE_SMI generates an SMI. SMI_MODE_DISABLE disables events.<br> * @param level SMI_LVL_LOW or SMI_LVL_HIGH<br> */<br>-void hudson_configure_gevent_smi(uint8_t gevent, uint8_t mode, uint8_t level)<br>+void configure_gevent_smi(uint8_t gevent, uint8_t mode, uint8_t level)<br> {<br> uint32_t reg32;<br> /* GEVENT pins range from [0:23] */<br>@@ -59,7 +59,7 @@<br> }<br> <br> /** Disable events from given GEVENT pin */<br>-void hudson_disable_gevent_smi(uint8_t gevent)<br>+void disable_gevent_smi(uint8_t gevent)<br> {<br> /* GEVENT pins range from [0:23] */<br> if (gevent > 23) {<br>@@ -72,7 +72,7 @@<br> }<br> <br> /** Enable SMIs on writes to ACPI SMI command port */<br>-void hudson_enable_acpi_cmd_smi(void)<br>+void enable_acpi_cmd_smi(void)<br> {<br> configure_smi(STONEYRIDGE_SMI_ACPI_COMMAND, SMI_MODE_SMI);<br> }<br>diff --git a/src/soc/amd/stoneyridge/smihandler.c b/src/soc/amd/stoneyridge/smihandler.c<br>index 5a646a6..a8ff96a 100644<br>--- a/src/soc/amd/stoneyridge/smihandler.c<br>+++ b/src/soc/amd/stoneyridge/smihandler.c<br>@@ -9,9 +9,8 @@<br> #include <console/console.h><br> #include <cpu/x86/smm.h><br> #include <delay.h><br>-#include <soc/hudson.h><br> #include <soc/smi.h><br>-<br>+#include <soc/southbridge.h><br> <br> <br> #define SMI_0x88_ACPI_COMMAND (1 << 11)<br>@@ -25,7 +24,7 @@<br> SMI_SOURCE_0x90 = (1 << 5)<br> };<br> <br>-static void hudson_apmc_smi_handler(void)<br>+static void sb_apmc_smi_handler(void)<br> {<br> u32 reg32;<br> const uint8_t cmd = inb(ACPI_SMI_CTL_PORT);<br>@@ -88,7 +87,7 @@<br> <br> if (status & SMI_0x88_ACPI_COMMAND) {<br> /* Command received via ACPI SMI command port */<br>- hudson_apmc_smi_handler();<br>+ sb_apmc_smi_handler();<br> }<br> /* Clear events to prevent re-entering SMI if event isn't handled */<br> smi_write32(0x88, status);<br>diff --git a/src/soc/amd/stoneyridge/hudson.c b/src/soc/amd/stoneyridge/southbridge.c<br>similarity index 90%<br>rename from src/soc/amd/stoneyridge/hudson.c<br>rename to src/soc/amd/stoneyridge/southbridge.c<br>index 0eee351..5e36100 100644<br>--- a/src/soc/amd/stoneyridge/hudson.c<br>+++ b/src/soc/amd/stoneyridge/southbridge.c<br>@@ -25,7 +25,7 @@<br> #include <device/pci_ops.h><br> #include <cbmem.h><br> #include <amd_pci_util.h><br>-#include <soc/hudson.h><br>+#include <soc/southbridge.h><br> #include <soc/smbus.h><br> #include <soc/smi.h><br> #if IS_ENABLED(CONFIG_STONEYRIDGE_IMC_FWM)<br>@@ -60,12 +60,12 @@<br> return read16((void *)(PM_MMIO_BASE + reg));<br> }<br> <br>-void hudson_enable(device_t dev)<br>+void sb_enable(device_t dev)<br> {<br>- printk(BIOS_DEBUG, "hudson_enable()\n");<br>+ printk(BIOS_DEBUG, "%s\n", __func__);<br> }<br> <br>-static void hudson_init_acpi_ports(void)<br>+static void sb_init_acpi_ports(void)<br> {<br> /* We use some of these ports in SMM regardless of whether or not<br> * ACPI tables are generated. Enable these ports indiscriminately.<br>@@ -80,7 +80,7 @@<br> <br> if (IS_ENABLED(CONFIG_HAVE_SMI_HANDLER)) {<br> pm_write16(PM_ACPI_SMI_CMD, ACPI_SMI_CTL_PORT);<br>- hudson_enable_acpi_cmd_smi();<br>+ enable_acpi_cmd_smi();<br> } else {<br> pm_write16(PM_ACPI_SMI_CMD, 0);<br> }<br>@@ -91,12 +91,12 @@<br> pm_write8(PM_ACPI_CONF, BIT(0) | BIT(1) | BIT(4) | BIT(2));<br> }<br> <br>-void hudson_init(void *chip_info)<br>+void southbridge_init(void *chip_info)<br> {<br>- hudson_init_acpi_ports();<br>+ sb_init_acpi_ports();<br> }<br> <br>-void hudson_final(void *chip_info)<br>+void southbridge_final(void *chip_info)<br> {<br> #if IS_ENABLED(CONFIG_STONEYRIDGE_IMC_FWM)<br> agesawrapper_fchecfancontrolservice();<br>diff --git a/src/soc/amd/stoneyridge/uart.c b/src/soc/amd/stoneyridge/uart.c<br>index 7919207..9cc0c94 100644<br>--- a/src/soc/amd/stoneyridge/uart.c<br>+++ b/src/soc/amd/stoneyridge/uart.c<br>@@ -14,7 +14,7 @@<br> */<br> <br> #include <console/uart.h><br>-#include <soc/hudson.h><br>+#include <soc/southbridge.h><br> <br> uintptr_t uart_platform_base(int idx)<br> {<br>diff --git a/src/soc/amd/stoneyridge/usb.c b/src/soc/amd/stoneyridge/usb.c<br>index 6f27395..c1caf7d 100644<br>--- a/src/soc/amd/stoneyridge/usb.c<br>+++ b/src/soc/amd/stoneyridge/usb.c<br>@@ -20,7 +20,7 @@<br> #include <device/pci_ops.h><br> #include <device/pci_ehci.h><br> #include <arch/io.h><br>-#include <soc/hudson.h><br>+#include <soc/southbridge.h><br> <br> static struct pci_operations lops_pci = {<br> .set_subsystem = pci_dev_set_subsystem,<br></pre><p>To view, visit <a href="https://review.coreboot.org/20912">change 20912</a>. To unsubscribe, visit <a href="https://review.coreboot.org/settings">settings</a>.</p><div itemscope itemtype="http://schema.org/EmailMessage"><div itemscope itemprop="action" itemtype="http://schema.org/ViewAction"><link itemprop="url" href="https://review.coreboot.org/20912"/><meta itemprop="name" content="View Change"/></div></div>
<div style="display:none"> Gerrit-Project: coreboot </div>
<div style="display:none"> Gerrit-Branch: master </div>
<div style="display:none"> Gerrit-MessageType: newchange </div>
<div style="display:none"> Gerrit-Change-Id: Ide7a72dae69b881997101f1e37a1ac739901744d </div>
<div style="display:none"> Gerrit-Change-Number: 20912 </div>
<div style="display:none"> Gerrit-PatchSet: 1 </div>
<div style="display:none"> Gerrit-Owner: Marc Jones <marc@marcjonesconsulting.com> </div>