<p>Lijian Zhao has uploaded this change for <strong>review</strong>.</p><p><a href="https://review.coreboot.org/20914">View Change</a></p><pre style="font-family: monospace,monospace; white-space: pre-wrap;">soc/intel/cannonlake: Add ramstage SystemAgent support<br><br>Revered memory resource within SA, also perform necessary routine for<br>initialization during ramstage.<br><br>Change-Id: Ibaa7334b0d94fedc87e707a136c9537e2e6f57cb<br>Signed-off-by: Lijian Zhao <lijian.zhao@intel.com><br>---<br>M src/soc/intel/cannonlake/Makefile.inc<br>A src/soc/intel/cannonlake/systemagent.c<br>2 files changed, 62 insertions(+), 0 deletions(-)<br><br></pre><pre style="font-family: monospace,monospace; white-space: pre-wrap;">git pull ssh://review.coreboot.org:29418/coreboot refs/changes/14/20914/1</pre><pre style="font-family: monospace,monospace; white-space: pre-wrap;">diff --git a/src/soc/intel/cannonlake/Makefile.inc b/src/soc/intel/cannonlake/Makefile.inc<br>index 537a973..37434bc 100644<br>--- a/src/soc/intel/cannonlake/Makefile.inc<br>+++ b/src/soc/intel/cannonlake/Makefile.inc<br>@@ -19,6 +19,7 @@<br> <br> ramstage-y += cbmem.c<br> ramstage-$(CONFIG_PLATFORM_USES_FSP2_0) += reset.c<br>+ramstage-y += systemagent.c<br> ramstage-$(CONFIG_DRIVERS_UART_8250MEM) += uart.c<br> <br> CPPFLAGS_common += -I$(src)/soc/intel/cannonlake/include/fsp20<br>diff --git a/src/soc/intel/cannonlake/systemagent.c b/src/soc/intel/cannonlake/systemagent.c<br>new file mode 100644<br>index 0000000..d006fb5<br>--- /dev/null<br>+++ b/src/soc/intel/cannonlake/systemagent.c<br>@@ -0,0 +1,61 @@<br>+/*<br>+ * This file is part of the coreboot project.<br>+ *<br>+ * Copyright (C) 2007-2009 coresystems GmbH<br>+ * Copyright (C) 2014 Google Inc.<br>+ * Copyright (C) 2015-2017 Intel Corporation.<br>+ *<br>+ * This program is free software; you can redistribute it and/or modify<br>+ * it under the terms of the GNU General Public License as published by<br>+ * the Free Software Foundation; version 2 of the License.<br>+ *<br>+ * This program is distributed in the hope that it will be useful,<br>+ * but WITHOUT ANY WARRANTY; without even the implied warranty of<br>+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the<br>+ * GNU General Public License for more details.<br>+ */<br>+<br>+#include <console/console.h><br>+#include <delay.h><br>+#include <device/device.h><br>+#include <intelblocks/systemagent.h><br>+#include <soc/cpu.h><br>+#include <soc/iomap.h><br>+#include <soc/systemagent.h><br>+<br>+/*<br>+ * SoC implementation<br>+ *<br>+ * Add all known fixed memory ranges for Host Controller/Mmeory<br>+ * controller.<br>+ */<br>+void soc_add_fixed_mmio_resources(struct device *dev, int *index)<br>+{<br>+ static const struct sa_mmio_descriptor soc_fixed_resources[] = {<br>+             { PCIEXBAR, CONFIG_MMCONF_BASE_ADDRESS, CONFIG_SA_PCIEX_LENGTH,<br>+                              "PCIEXBAR" },<br>+              { MCHBAR, MCH_BASE_ADDRESS, MCH_BASE_SIZE, "MCHBAR" },<br>+             { DMIBAR, DMI_BASE_ADDRESS, DMI_BASE_SIZE, "DMIBAR" },<br>+             { EPBAR, EP_BASE_ADDRESS, EP_BASE_SIZE, "EPBAR" },<br>+         { REGBAR, REG_BASE_ADDRESS, REG_BASE_SIZE, "REGBAR" },<br>+             { EDRAMBAR, EDRAM_BASE_ADDRESS, EDRAM_BASE_SIZE, "EDRAMBAR" },<br>+     };<br>+<br>+        sa_add_fixed_mmio_resources(dev, index, soc_fixed_resources,<br>+                 ARRAY_SIZE(soc_fixed_resources));<br>+}<br>+<br>+/*<br>+ * SoC implementation<br>+ *<br>+ * Perform System Agent Initialization during Ramstage phase.<br>+ */<br>+void soc_systemagent_init(struct device *dev)<br>+{<br>+ /* Enable Power Aware Interrupt Routing */<br>+   enable_power_aware_intr();<br>+<br>+        /* Enable BIOS Reset CPL */<br>+  enable_bios_reset_cpl();<br>+}<br>+<br></pre><p>To view, visit <a href="https://review.coreboot.org/20914">change 20914</a>. To unsubscribe, visit <a href="https://review.coreboot.org/settings">settings</a>.</p><div itemscope itemtype="http://schema.org/EmailMessage"><div itemscope itemprop="action" itemtype="http://schema.org/ViewAction"><link itemprop="url" href="https://review.coreboot.org/20914"/><meta itemprop="name" content="View Change"/></div></div>

<div style="display:none"> Gerrit-Project: coreboot </div>
<div style="display:none"> Gerrit-Branch: master </div>
<div style="display:none"> Gerrit-MessageType: newchange </div>
<div style="display:none"> Gerrit-Change-Id: Ibaa7334b0d94fedc87e707a136c9537e2e6f57cb </div>
<div style="display:none"> Gerrit-Change-Number: 20914 </div>
<div style="display:none"> Gerrit-PatchSet: 1 </div>
<div style="display:none"> Gerrit-Owner: Lijian Zhao <lijian.zhao@intel.com> </div>