<p>frank vibrans has uploaded this change for <strong>review</strong>.</p><p><a href="https://review.coreboot.org/20916">View Change</a></p><pre style="font-family: monospace,monospace; white-space: pre-wrap;">Initial Kahlee SMM code.<br><br>This code implements SMM handling using an ASEG implementation.<br>There is no real functional capability in place. SMIs are simply<br>cleared and SMM is exited.<br><br>Change-Id: Ifeca4323626af6089ce23892e79b0e560d92c100<br>Signed-off-by: frank vibrans <frank.vibrans@scarletltd.com><br>---<br>M src/cpu/x86/smm/smmhandler.S<br>M src/include/cpu/x86/smm.h<br>M src/soc/amd/stoneyridge/Kconfig<br>M src/soc/amd/stoneyridge/include/soc/smi.h<br>M src/soc/amd/stoneyridge/model_15_init.c<br>M src/soc/amd/stoneyridge/smi.c<br>M src/soc/amd/stoneyridge/smihandler.c<br>7 files changed, 135 insertions(+), 3 deletions(-)<br><br></pre><pre style="font-family: monospace,monospace; white-space: pre-wrap;">git pull ssh://review.coreboot.org:29418/coreboot refs/changes/16/20916/1</pre><pre style="font-family: monospace,monospace; white-space: pre-wrap;">diff --git a/src/cpu/x86/smm/smmhandler.S b/src/cpu/x86/smm/smmhandler.S<br>index dd8a0c0..0617a0d 100644<br>--- a/src/cpu/x86/smm/smmhandler.S<br>+++ b/src/cpu/x86/smm/smmhandler.S<br>@@ -142,7 +142,8 @@<br> * without relying on the LAPIC ID.<br> */<br> #if IS_ENABLED(CONFIG_CPU_AMD_AGESA_FAMILY15_TN) \<br>- || IS_ENABLED(CONFIG_CPU_AMD_AGESA_FAMILY15_RL)<br>+ || IS_ENABLED(CONFIG_CPU_AMD_AGESA_FAMILY15_RL) \<br>+ || IS_ENABLED(CONFIG_CPU_AMD_AGESA_BINARY_PI)<br> /* LAPIC IDs start from 0x10; map that to the proper core index */<br> subl $0x10, %ecx<br> #endif<br>diff --git a/src/include/cpu/x86/smm.h b/src/include/cpu/x86/smm.h<br>index bd0e356..aea4100 100644<br>--- a/src/include/cpu/x86/smm.h<br>+++ b/src/include/cpu/x86/smm.h<br>@@ -37,6 +37,8 @@<br> * starts @ 0x7e00<br> */<br> #define SMM_AMD64_ARCH_OFFSET 0x7e00<br>+#define SMM_AMD64_SAVE_STATE_OFFSET \<br>+ SMM_SAVE_STATE_BEGIN(SMM_AMD64_ARCH_OFFSET)<br> <br> typedef struct {<br> u16 es_selector;<br>diff --git a/src/soc/amd/stoneyridge/Kconfig b/src/soc/amd/stoneyridge/Kconfig<br>index 0425beb..19aa1b2 100644<br>--- a/src/soc/amd/stoneyridge/Kconfig<br>+++ b/src/soc/amd/stoneyridge/Kconfig<br>@@ -281,6 +281,10 @@<br> to FEDC_6FFFh. UART controller 1 registers<br> range from FEDC_8000h to FEDC_8FFFh.<br> <br>+config HAVE_SMI_HANDLER<br>+ bool "Enable SMM and SMI handling"<br>+ default y<br>+<br> config SMM_TSEG_SIZE<br> hex<br> default 0x800000 if HAVE_SMI_HANDLER<br>diff --git a/src/soc/amd/stoneyridge/include/soc/smi.h b/src/soc/amd/stoneyridge/include/soc/smi.h<br>index 7a3c804..016ea4a 100644<br>--- a/src/soc/amd/stoneyridge/include/soc/smi.h<br>+++ b/src/soc/amd/stoneyridge/include/soc/smi.h<br>@@ -20,7 +20,24 @@<br> #define SMITRG0_EOS (1 << 28)<br> #define SMITRG0_SMIENB (1 << 31)<br> <br>+#define SMI_REG_GPESTAT 0x00 /* GPE event status */<br>+<br>+#define SMI_REG_SMISTAT0 0x80<br>+#define SMI_REG_SMISTAT1 0x84<br>+#define SMI_REG_SMISTAT2 0x88<br>+#define SMI_REG_SMISTAT3 0x8C<br>+#define SMI_REG_SMISTAT4 0x90<br>+<br> #define SMI_REG_CONTROL0 0xa0<br>+<br>+#define SMI_REG_SMICTRL2 0xA8 /* Routes FakeSMIs reported in SMIx84 */<br>+#define SMICTRL2_FAKES_EN 0x00000054 /* Enable FakeSMIs reported in SMIx84 */<br>+<br>+#define SMI_REG_SMICTRL8 0xC0 /* Routes FakeSMIs reported in SMIx90 */<br>+#define SMICTRL8_FAKES_EN 0x01500000 /* Enable FakeSMIs reported in SMIx90 */<br>+<br>+#define SMI_REG_SMICTRL9 0xC4 /* Routes trap events reported in SMIx90 */<br>+#define SMICTRL9_MTRAP_EN 0x00010000 /* Enable memory trap SMI reported in SMIx90 */<br> <br> enum smi_mode {<br> SMI_MODE_DISABLE = 0,<br>@@ -54,6 +71,9 @@<br> write16((void *)(SMI_BASE + offset), value);<br> }<br> <br>+void smm_southbridge_enable(void);<br>+void smm_southbridge_clear_state(void);<br>+<br> void hudson_configure_gevent_smi(uint8_t gevent, uint8_t mode, uint8_t level);<br> void hudson_disable_gevent_smi(uint8_t gevent);<br> void hudson_enable_acpi_cmd_smi(void);<br>diff --git a/src/soc/amd/stoneyridge/model_15_init.c b/src/soc/amd/stoneyridge/model_15_init.c<br>index a46f322..6003bef 100644<br>--- a/src/soc/amd/stoneyridge/model_15_init.c<br>+++ b/src/soc/amd/stoneyridge/model_15_init.c<br>@@ -27,6 +27,7 @@<br> #include <cpu/cpu.h><br> #include <cpu/x86/cache.h><br> #include <cpu/x86/mtrr.h><br>+#include <cpu/x86/smm.h><br> #include <cpu/amd/amdfam15.h><br> #include <arch/acpi.h><br> <br>@@ -54,6 +55,9 @@<br> u8 i;<br> msr_t msr;<br> int msrno;<br>+#if IS_ENABLED(CONFIG_HAVE_SMI_HANDLER)<br>+ unsigned int cpu_idx;<br>+#endif<br> #if IS_ENABLED(CONFIG_LOGICAL_CPUS)<br> u32 siblings;<br> #endif<br>@@ -114,6 +118,21 @@<br> wrmsr(NB_CFG_MSR, msr);<br> <br> <br>+ if (IS_ENABLED(CONFIG_HAVE_SMI_HANDLER)) {<br>+ cpu_idx = cpu_info()->index;<br>+ printk(BIOS_INFO, "Initializing SMM for CPU %u\n", cpu_idx);<br>+<br>+ /* Set SMM base address for this CPU */<br>+ msr = rdmsr(MSR_SMM_BASE);<br>+ msr.lo = SMM_BASE - (cpu_idx * 0x400);<br>+ wrmsr(MSR_SMM_BASE, msr);<br>+<br>+ /* Enable the SMM memory window */<br>+ msr = rdmsr(MSR_SMM_MASK);<br>+ msr.lo |= ((1 << 0) | (6 << 8)); /* Enable ASEG SMRAM Range as WB */<br>+ wrmsr(MSR_SMM_MASK, msr);<br>+ }<br>+<br> /* Write protect SMM space with SMMLOCK. */<br> msr = rdmsr(HWCR_MSR);<br> msr.lo |= (1 << 0);<br>diff --git a/src/soc/amd/stoneyridge/smi.c b/src/soc/amd/stoneyridge/smi.c<br>index c92697c..e8c1180 100644<br>--- a/src/soc/amd/stoneyridge/smi.c<br>+++ b/src/soc/amd/stoneyridge/smi.c<br>@@ -8,12 +8,22 @@<br> <br> <br> #include <console/console.h><br>+#include <arch/io.h><br> #include <cpu/cpu.h><br>+#include <cpu/x86/lapic.h><br>+#include <cpu/x86/msr.h><br>+#include <cpu/x86/mtrr.h><br>+#include <cpu/amd/mtrr.h><br>+#include <cpu/amd/msr.h><br>+#include <cpu/x86/cache.h><br>+#include <cpu/x86/smm.h><br> #include <soc/smi.h><br>+#include <string.h><br>+<br> <br> void smm_setup_structures(void *gnvs, void *tcg, void *smi1)<br> {<br>- printk(BIOS_DEBUG, "smm_setup_structures STUB!!!\n");<br>+ printk(BIOS_DEBUG, "smm_setup_structures - STUB.\n");<br> }<br> <br> /** Set the EOS bit and enable SMI generation from southbridge */<br>@@ -24,3 +34,57 @@<br> reg |= SMITRG0_EOS; /* Set EOS bit */<br> smi_write32(SMI_REG_SMITRIG0, reg);<br> }<br>+<br>+/* Sets up ASEG MTRR and copies the SMM code to the ASEG. */<br>+void smm_init(void)<br>+{<br>+<br>+ msr_t msr, syscfg_orig, mtrr_aseg_orig;<br>+<br>+ printk(BIOS_DEBUG, "SMM_mem_init\n");<br>+<br>+ /* Back up MSRs for later restore */<br>+ syscfg_orig = rdmsr(SYSCFG_MSR);<br>+ mtrr_aseg_orig = rdmsr(MTRR_FIX_16K_A0000);<br>+<br>+ /* MTRR changes don't like an enabled cache */<br>+ disable_cache();<br>+<br>+ msr = syscfg_orig;<br>+<br>+ /* Allow changes to MTRR extended attributes */<br>+ msr.lo |= SYSCFG_MSR_MtrrFixDramModEn;<br>+ /* turn the extended attributes off until we fix<br>+ * them so A0000 is routed to memory<br>+ */<br>+ msr.lo &= ~SYSCFG_MSR_MtrrFixDramEn;<br>+ wrmsr(SYSCFG_MSR, msr);<br>+<br>+ /* set DRAM access to 0xa0000-0xbffff to read, write, UC */<br>+ msr.hi = msr.lo = 0x18181818;<br>+ wrmsr(MTRR_FIX_16K_A0000, msr);<br>+<br>+ /* enable the extended features */<br>+ msr = syscfg_orig;<br>+ msr.lo |= SYSCFG_MSR_MtrrFixDramModEn;<br>+ msr.lo |= SYSCFG_MSR_MtrrFixDramEn;<br>+ wrmsr(SYSCFG_MSR, msr);<br>+<br>+ enable_cache();<br>+<br>+ /* copy the real SMM handler */<br>+ memcpy((void *)SMM_BASE, _binary_smm_start,<br>+ _binary_smm_end - _binary_smm_start);<br>+ wbinvd();<br>+<br>+ disable_cache();<br>+<br>+ /* Restore SYSCFG and MTRR */<br>+ wrmsr(SYSCFG_MSR, syscfg_orig);<br>+ wrmsr(MTRR_FIX_16K_A0000, mtrr_aseg_orig);<br>+<br>+ enable_cache();<br>+<br>+ /* CPU MSR are set in CPU init */<br>+}<br>+<br>diff --git a/src/soc/amd/stoneyridge/smihandler.c b/src/soc/amd/stoneyridge/smihandler.c<br>index 5a646a6..cb67801 100644<br>--- a/src/soc/amd/stoneyridge/smihandler.c<br>+++ b/src/soc/amd/stoneyridge/smihandler.c<br>@@ -110,8 +110,30 @@<br> smi_write32(0x90, status);<br> }<br> <br>+void smm_southbridge_enable(void)<br>+{<br>+}<br>+<br>+void smm_southbridge_clear_state(void)<br>+{<br>+ uint32_t reg = smi_read32(SMI_REG_GPESTAT);<br>+ smi_write32(SMI_REG_GPESTAT, reg);<br>+<br>+ reg = smi_read32(SMI_REG_SMISTAT0);<br>+ smi_write32(SMI_REG_SMISTAT0, reg);<br>+<br>+ reg = smi_read32(SMI_REG_SMISTAT1);<br>+ smi_write32(SMI_REG_SMISTAT1, reg);<br>+<br>+ reg = smi_read32(SMI_REG_SMISTAT2);<br>+ smi_write32(SMI_REG_SMISTAT2, reg);<br>+<br>+ reg = smi_read32(SMI_REG_SMISTAT4);<br>+ smi_write32(SMI_REG_SMISTAT4, reg);<br>+}<br>+<br> void southbridge_smi_handler(unsigned int node,<br>- smm_state_save_area_t *state_save)<br>+ smm_state_save_area_t *state_save)<br> {<br> const uint16_t smi_src = smi_read16(0x94);<br> <br></pre><p>To view, visit <a href="https://review.coreboot.org/20916">change 20916</a>. To unsubscribe, visit <a href="https://review.coreboot.org/settings">settings</a>.</p><div itemscope itemtype="http://schema.org/EmailMessage"><div itemscope itemprop="action" itemtype="http://schema.org/ViewAction"><link itemprop="url" href="https://review.coreboot.org/20916"/><meta itemprop="name" content="View Change"/></div></div>
<div style="display:none"> Gerrit-Project: coreboot </div>
<div style="display:none"> Gerrit-Branch: master </div>
<div style="display:none"> Gerrit-MessageType: newchange </div>
<div style="display:none"> Gerrit-Change-Id: Ifeca4323626af6089ce23892e79b0e560d92c100 </div>
<div style="display:none"> Gerrit-Change-Number: 20916 </div>
<div style="display:none"> Gerrit-PatchSet: 1 </div>
<div style="display:none"> Gerrit-Owner: frank vibrans <frank.vibrans@scarletltd.com> </div>