<p>Matt DeVillier has uploaded this change for <strong>review</strong>.</p><p><a href="https://review.coreboot.org/20891">View Change</a></p><pre style="font-family: monospace,monospace; white-space: pre-wrap;">soc/intel/braswell: Fix SPI write after FLOCKDN is set<br><br>The the spi controller initialization in finalize_chipset was failing<br>because FSP was setting FLOCKDN before finalize_chipset was called .<br>Hence moving finalize_chipset to get called from BS_POST_DEVICE so that it is<br>called before FSP notify function-Ready To Boot state<br><br>TEST: run flashrom with -VVV and observe supported opcodes and SPI<br>flash chip are reported correctly, and write/erase operations succeeed.<br><br>Original-Change-Id: I3c0297f3f2258cf77cf00db367f11ff4d1d9dc77<br>Original-Signed-off-by: Hannah Williams <hannah.williams@intel.com><br>Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org><br><br>Change-Id: I690fb4bf9e78bb58811c704179ba8b8f25ce95cc<br>Signed-off-by: Matt DeVillier <matt.devillier@gmail.com><br>---<br>M src/soc/intel/braswell/southcluster.c<br>1 file changed, 1 insertion(+), 2 deletions(-)<br><br></pre><pre style="font-family: monospace,monospace; white-space: pre-wrap;">git pull ssh://review.coreboot.org:29418/coreboot refs/changes/91/20891/1</pre><pre style="font-family: monospace,monospace; white-space: pre-wrap;">diff --git a/src/soc/intel/braswell/southcluster.c b/src/soc/intel/braswell/southcluster.c<br>index 1c450e9..0e2d5e2 100644<br>--- a/src/soc/intel/braswell/southcluster.c<br>+++ b/src/soc/intel/braswell/southcluster.c<br>@@ -508,5 +508,4 @@<br>   outb(APM_CNT_FINALIZE, APM_CNT);<br> }<br> <br>-BOOT_STATE_INIT_ENTRY(BS_OS_RESUME, BS_ON_ENTRY, finalize_chipset, NULL);<br>-BOOT_STATE_INIT_ENTRY(BS_PAYLOAD_LOAD, BS_ON_EXIT, finalize_chipset, NULL);<br>+BOOT_STATE_INIT_ENTRY(BS_POST_DEVICE, BS_ON_EXIT, finalize_chipset, NULL);<br></pre><p>To view, visit <a href="https://review.coreboot.org/20891">change 20891</a>. To unsubscribe, visit <a href="https://review.coreboot.org/settings">settings</a>.</p><div itemscope itemtype="http://schema.org/EmailMessage"><div itemscope itemprop="action" itemtype="http://schema.org/ViewAction"><link itemprop="url" href="https://review.coreboot.org/20891"/><meta itemprop="name" content="View Change"/></div></div>

<div style="display:none"> Gerrit-Project: coreboot </div>
<div style="display:none"> Gerrit-Branch: master </div>
<div style="display:none"> Gerrit-MessageType: newchange </div>
<div style="display:none"> Gerrit-Change-Id: I690fb4bf9e78bb58811c704179ba8b8f25ce95cc </div>
<div style="display:none"> Gerrit-Change-Number: 20891 </div>
<div style="display:none"> Gerrit-PatchSet: 1 </div>
<div style="display:none"> Gerrit-Owner: Matt DeVillier <matt.devillier@gmail.com> </div>
<div style="display:none"> Gerrit-Reviewer: Hannah Williams <hannah.williams@intel.com> </div>