<p>Furquan Shaikh has uploaded this change for <strong>review</strong>.</p><p><a href="https://review.coreboot.org/20884">View Change</a></p><pre style="font-family: monospace,monospace; white-space: pre-wrap;">soc/intel/common/uart: Refactor uart_common_init<br><br>1. Create a new function uart_lpss_init which takes the UART LPSS<br>controller out of reset and initializes and enables clock.<br><br>2. Instead of passing in m/n clock divider values as parameters to<br>uart_common_init, introduce Kconfig variables so that uart_lpss_init<br>can use the values directly without having to query the SoC.<br><br>BUG=b:64030366<br>TEST=Verified that UART still works on APL and KBL boards.<br><br>Change-Id: I74d01b0037d8c38fe6480c38ff2283d76097282a<br>Signed-off-by: Furquan Shaikh <furquan@chromium.org><br>---<br>M src/soc/intel/apollolake/Kconfig<br>M src/soc/intel/apollolake/include/soc/uart.h<br>M src/soc/intel/apollolake/uart_early.c<br>M src/soc/intel/common/block/include/intelblocks/uart.h<br>M src/soc/intel/common/block/uart/Kconfig<br>M src/soc/intel/common/block/uart/uart.c<br>M src/soc/intel/skylake/Kconfig<br>M src/soc/intel/skylake/bootblock/uart.c<br>8 files changed, 51 insertions(+), 21 deletions(-)<br><br></pre><pre style="font-family: monospace,monospace; white-space: pre-wrap;">git pull ssh://review.coreboot.org:29418/coreboot refs/changes/84/20884/1</pre><pre style="font-family: monospace,monospace; white-space: pre-wrap;">diff --git a/src/soc/intel/apollolake/Kconfig b/src/soc/intel/apollolake/Kconfig<br>index 2d8838a..ba311f5 100644<br>--- a/src/soc/intel/apollolake/Kconfig<br>+++ b/src/soc/intel/apollolake/Kconfig<br>@@ -350,4 +350,14 @@<br> Limits (RAPL) algorithm for a constant power management.<br> Set this config option to skip the RAPL configuration.<br> <br>+# M and N divisor values for clock frequency configuration.<br>+# These values get us a 1.836 MHz clock (ideally we want 1.843 MHz)<br>+config SOC_INTEL_COMMON_LPSS_UART_CLK_M_VAL<br>+ hex<br>+ default 0x25a<br>+<br>+config SOC_INTEL_COMMON_LPSS_UART_CLK_N_VAL<br>+ hex<br>+ default 0x7fff<br>+<br> endif<br>diff --git a/src/soc/intel/apollolake/include/soc/uart.h b/src/soc/intel/apollolake/include/soc/uart.h<br>index b2b1bb8..bf8b9d7 100644<br>--- a/src/soc/intel/apollolake/include/soc/uart.h<br>+++ b/src/soc/intel/apollolake/include/soc/uart.h<br>@@ -18,13 +18,6 @@<br> #ifndef _SOC_APOLLOLAKE_UART_H_<br> #define _SOC_APOLLOLAKE_UART_H_<br> <br>-/*<br>-* M and N divisor values for clock frequency configuration.<br>-* These values get us a 1.836 MHz clock (ideally we want 1.843 MHz)<br>-*/<br>-#define CLK_M_VAL 0x025a<br>-#define CLK_N_VAL 0x7fff<br>-<br> /* Initialize the console UART including the pads for the configured UART. */<br> void pch_uart_init(void);<br> <br>diff --git a/src/soc/intel/apollolake/uart_early.c b/src/soc/intel/apollolake/uart_early.c<br>index 4c143ad..d3c1b0d 100644<br>--- a/src/soc/intel/apollolake/uart_early.c<br>+++ b/src/soc/intel/apollolake/uart_early.c<br>@@ -69,6 +69,6 @@<br> gpio_configure_pads(&uart_gpios[pad_index * 2], 2);<br> <br> /* Program UART2 BAR0, command, reset and clock register */<br>- uart_common_init(uart, base, CLK_M_VAL, CLK_N_VAL);<br>+ uart_common_init(uart, base);<br> <br> }<br>diff --git a/src/soc/intel/common/block/include/intelblocks/uart.h b/src/soc/intel/common/block/include/intelblocks/uart.h<br>index b46edd7..9ec5004 100644<br>--- a/src/soc/intel/common/block/include/intelblocks/uart.h<br>+++ b/src/soc/intel/common/block/include/intelblocks/uart.h<br>@@ -19,8 +19,12 @@<br> #include <arch/io.h><br> #include <device/device.h><br> <br>-void uart_common_init(device_t dev, uintptr_t baseaddr,<br>- uint32_t clk_m_val, uint32_t clk_n_val);<br>+/*<br>+ * Common routine to initialize UART controller PCI config space, take it out of<br>+ * reset and configure M/N dividers.<br>+ */<br>+void uart_common_init(device_t dev, uintptr_t baseaddr);<br>+<br> <br> void pch_uart_read_resources(struct device *dev);<br> <br>diff --git a/src/soc/intel/common/block/uart/Kconfig b/src/soc/intel/common/block/uart/Kconfig<br>index 103659f..f4a0e4e 100644<br>--- a/src/soc/intel/common/block/uart/Kconfig<br>+++ b/src/soc/intel/common/block/uart/Kconfig<br>@@ -3,3 +3,15 @@<br> select SOC_INTEL_COMMON_BLOCK_LPSS<br> help<br> Intel Processor common UART support<br>+<br>+config SOC_INTEL_COMMON_BLOCK_UART_LPSS_CLK_M_VAL<br>+ depends on SOC_INTEL_COMMON_BLOCK_UART<br>+ hex<br>+ help<br>+ Clock m-divisor value for m/n divider<br>+<br>+config SOC_INTEL_COMMON_BLOCK_UART_LPSS_CLK_N_VAL<br>+ depends on SOC_INTEL_COMMON_BLOCK_UART<br>+ hex<br>+ help<br>+ Clock m-divisor value for m/n divider<br>diff --git a/src/soc/intel/common/block/uart/uart.c b/src/soc/intel/common/block/uart/uart.c<br>index e8f1bc8..be30464 100644<br>--- a/src/soc/intel/common/block/uart/uart.c<br>+++ b/src/soc/intel/common/block/uart/uart.c<br>@@ -19,8 +19,17 @@<br> #include <intelblocks/lpss.h><br> #include <intelblocks/uart.h><br> <br>-void uart_common_init(device_t dev, uintptr_t baseaddr, uint32_t clk_m_val,<br>- uint32_t clk_n_val)<br>+static void uart_lpss_init(uintptr_t baseaddr)<br>+{<br>+ /* Take UART out of reset */<br>+ lpss_reset_release(baseaddr);<br>+<br>+ /* Set M and N divisor inputs and enable clock */<br>+ lpss_clk_update(baseaddr, CONFIG_SOC_INTEL_COMMON_LPSS_UART_CLK_M_VAL,<br>+ CONFIG_SOC_INTEL_COMMON_LPSS_UART_CLK_N_VAL);<br>+}<br>+<br>+void uart_common_init(device_t dev, uintptr_t baseaddr)<br> {<br> /* Set UART base address */<br> pci_write_config32(dev, PCI_BASE_ADDRESS_0, baseaddr);<br>@@ -29,11 +38,8 @@<br> pci_write_config32(dev, PCI_COMMAND,<br> PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER);<br> <br>- /* Take UART out of reset */<br>- lpss_reset_release(baseaddr);<br>+ uart_lpss_init(baseaddr);<br> <br>- /* Set M and N divisor inputs and enable clock */<br>- lpss_clk_update(baseaddr, clk_m_val, clk_n_val);<br> }<br> <br> #if ENV_RAMSTAGE<br>diff --git a/src/soc/intel/skylake/Kconfig b/src/soc/intel/skylake/Kconfig<br>index 32c2654..f0402a9 100644<br>--- a/src/soc/intel/skylake/Kconfig<br>+++ b/src/soc/intel/skylake/Kconfig<br>@@ -317,4 +317,13 @@<br> int<br> default 100<br> <br>+# Clock divider parameters for 115200 baud rate<br>+config SOC_INTEL_COMMON_LPSS_UART_CLK_M_VAL<br>+ hex<br>+ default 0x30<br>+<br>+config SOC_INTEL_COMMON_LPSS_UART_CLK_N_VAL<br>+ hex<br>+ default 0xc35<br>+<br> endif<br>diff --git a/src/soc/intel/skylake/bootblock/uart.c b/src/soc/intel/skylake/bootblock/uart.c<br>index 26b81c0..b7ab241 100644<br>--- a/src/soc/intel/skylake/bootblock/uart.c<br>+++ b/src/soc/intel/skylake/bootblock/uart.c<br>@@ -31,10 +31,6 @@<br> #define PCR_SIO_PCH_LEGACY_UART1 (1 << 1)<br> #define PCR_SIO_PCH_LEGACY_UART2 (1 << 2)<br> <br>-/* Clock divider parameters for 115200 baud rate */<br>-#define CLK_M_VAL 0x30<br>-#define CLK_N_VAL 0xc35<br>-<br> /* UART2 pad configuration. Support RXD and TXD for now. */<br> static const struct pad_config uart2_pads[] = {<br> /* UART2_RXD */ PAD_CFG_NF(GPP_C20, NONE, DEEP, NF1),<br>@@ -45,7 +41,7 @@<br> {<br> uintptr_t base = uart_platform_base(CONFIG_UART_FOR_CONSOLE);<br> <br>- uart_common_init(PCH_DEV_UART2, base, CLK_M_VAL, CLK_N_VAL);<br>+ uart_common_init(PCH_DEV_UART2, base);<br> <br> /* Put UART2 in byte access mode for 16550 compatibility */<br> if (!IS_ENABLED(CONFIG_DRIVERS_UART_8250MEM_32))<br></pre><p>To view, visit <a href="https://review.coreboot.org/20884">change 20884</a>. To unsubscribe, visit <a href="https://review.coreboot.org/settings">settings</a>.</p><div itemscope itemtype="http://schema.org/EmailMessage"><div itemscope itemprop="action" itemtype="http://schema.org/ViewAction"><link itemprop="url" href="https://review.coreboot.org/20884"/><meta itemprop="name" content="View Change"/></div></div>
<div style="display:none"> Gerrit-Project: coreboot </div>
<div style="display:none"> Gerrit-Branch: master </div>
<div style="display:none"> Gerrit-MessageType: newchange </div>
<div style="display:none"> Gerrit-Change-Id: I74d01b0037d8c38fe6480c38ff2283d76097282a </div>
<div style="display:none"> Gerrit-Change-Number: 20884 </div>
<div style="display:none"> Gerrit-PatchSet: 1 </div>
<div style="display:none"> Gerrit-Owner: Furquan Shaikh <furquan@google.com> </div>