<p>Furquan Shaikh has uploaded this change for <strong>review</strong>.</p><p><a href="https://review.coreboot.org/20888">View Change</a></p><pre style="font-family: monospace,monospace; white-space: pre-wrap;">soc/intel/apollolake: Enable UART debug controller on S3 resume<br><br>1. Add a new variable to GNVS to store information during S3 suspend<br>whether UART debug controller is enabled.<br><br>2. On resume, read stored GNVS variable to decide if UART debug port<br>controller needs to be initialized.<br><br>3. Provide helper functions required by intel/common UARRT driver for<br>enabling controller on S3 resume.<br><br>BUG=b:64030366<br><br>Change-Id: Idd17dd0bd3c644383f273b465a16add184e3b171<br>Signed-off-by: Furquan Shaikh <furquan@chromium.org><br>---<br>M src/soc/intel/apollolake/Makefile.inc<br>M src/soc/intel/apollolake/acpi/globalnvs.asl<br>M src/soc/intel/apollolake/include/soc/nvs.h<br>M src/soc/intel/apollolake/uart.c<br>M src/soc/intel/common/block/smm/smihandler.c<br>5 files changed, 36 insertions(+), 4 deletions(-)<br><br></pre><pre style="font-family: monospace,monospace; white-space: pre-wrap;">git pull ssh://review.coreboot.org:29418/coreboot refs/changes/88/20888/1</pre><pre style="font-family: monospace,monospace; white-space: pre-wrap;">diff --git a/src/soc/intel/apollolake/Makefile.inc b/src/soc/intel/apollolake/Makefile.inc<br>index 07bbdcd..589b846 100644<br>--- a/src/soc/intel/apollolake/Makefile.inc<br>+++ b/src/soc/intel/apollolake/Makefile.inc<br>@@ -42,6 +42,7 @@<br> smm-y += smihandler.c<br> smm-y += spi.c<br> smm-y += uart_early.c<br>+smm-y += uart.c<br> <br> ramstage-$(CONFIG_HAVE_ACPI_TABLES) += acpi.c<br> ramstage-y += cpu.c<br>diff --git a/src/soc/intel/apollolake/acpi/globalnvs.asl b/src/soc/intel/apollolake/acpi/globalnvs.asl<br>index 1548c30..6431fae 100644<br>--- a/src/soc/intel/apollolake/acpi/globalnvs.asl<br>+++ b/src/soc/intel/apollolake/acpi/globalnvs.asl<br>@@ -41,6 +41,8 @@<br> PRT0, 32, // 0x25 - 0x28 - PERST_0 Address<br> SCDP, 8, // 0x29 - SD_CD GPIO portid<br> SCDO, 8, // 0x2A - GPIO pad offset relative to the community<br>+ UIOR, 8, // 0x2B - UART debug controller init on S3 resume<br>+<br> /* ChromeOS stuff (0x100 -> 0xfff, size 0xeff) */<br> Offset (0x100),<br> #include <vendorcode/google/chromeos/acpi/gnvs.asl><br>diff --git a/src/soc/intel/apollolake/include/soc/nvs.h b/src/soc/intel/apollolake/include/soc/nvs.h<br>index 56085b2..9a09800 100644<br>--- a/src/soc/intel/apollolake/include/soc/nvs.h<br>+++ b/src/soc/intel/apollolake/include/soc/nvs.h<br>@@ -42,7 +42,9 @@<br> uint32_t prt0; /* 0x25 - 0x28 - PERST_0 Address */<br> uint8_t scdp; /* 0x29 - SD_CD GPIO portid */<br> uint8_t scdo; /* 0x2A - GPIO pad offset relative to the community */<br>- uint8_t unused[213];<br>+ uint8_t uior; /* 0x2B - UART debug controller init on S3<br>+ resume */<br>+ uint8_t unused[212];<br> <br> /* ChromeOS specific (0x100 - 0xfff) */<br> chromeos_acpi_t chromeos;<br>diff --git a/src/soc/intel/apollolake/uart.c b/src/soc/intel/apollolake/uart.c<br>index 3db460a..14dc5f1 100644<br>--- a/src/soc/intel/apollolake/uart.c<br>+++ b/src/soc/intel/apollolake/uart.c<br>@@ -20,20 +20,44 @@<br> * shouldn't cause any fragmentation.<br> */<br> <br>+#include <cbmem.h><br> #include <device/device.h><br> #include <device/pci.h><br> #include <intelblocks/uart.h><br>+#include <soc/nvs.h><br> #include <soc/pci_devs.h><br> <br>+bool pch_uart_is_debug_controller(struct device *dev)<br>+{<br>+ return dev->path.pci.devfn == _PCH_DEVFN(UART,<br>+ CONFIG_UART_FOR_CONSOLE);<br>+}<br>+<br>+#if ENV_RAMSTAGE<br> void pch_uart_read_resources(struct device *dev)<br> {<br> pci_dev_read_resources(dev);<br> <br>- if ((IS_ENABLED(CONFIG_SOC_UART_DEBUG) &&<br>- dev->path.pci.devfn == _PCH_DEVFN(UART,<br>- CONFIG_UART_FOR_CONSOLE))) {<br>+ if (IS_ENABLED(CONFIG_SOC_UART_DEBUG) &&<br>+ pch_uart_is_debug_controller(dev)) {<br> /* will override existing resource. */<br> fixed_mem_resource(dev, PCI_BASE_ADDRESS_0,<br> CONFIG_CONSOLE_UART_BASE_ADDRESS >> 10, 4, 0);<br> }<br> }<br>+#endif<br>+<br>+bool pch_uart_init_debug_controller_on_resume(void)<br>+{<br>+ global_nvs_t *gnvs = cbmem_find(CBMEM_ID_ACPI_GNVS);<br>+<br>+ if (gnvs)<br>+ return !!gnvs->uior;<br>+<br>+ return false;<br>+}<br>+<br>+device_t pch_uart_get_debug_controller(void)<br>+{<br>+ return _PCH_DEV(UART, CONFIG_UART_FOR_CONSOLE);<br>+}<br>diff --git a/src/soc/intel/common/block/smm/smihandler.c b/src/soc/intel/common/block/smm/smihandler.c<br>index b620ff9..dde9b1f 100644<br>--- a/src/soc/intel/common/block/smm/smihandler.c<br>+++ b/src/soc/intel/common/block/smm/smihandler.c<br>@@ -22,6 +22,7 @@<br> #include <device/pci_def.h><br> #include <elog.h><br> #include <intelblocks/smihandler.h><br>+#include <intelblocks/uart.h><br> #include <soc/nvs.h><br> #include <soc/pm.h><br> #include <soc/gpio.h><br>@@ -160,6 +161,8 @@<br> case ACPI_S3:<br> printk(BIOS_DEBUG, "SMI#: Entering S3 (Suspend-To-RAM)\n");<br> <br>+ gnvs->uior = uart_debug_controller_is_initialized();<br>+<br> /* Invalidate the cache before going to S3 */<br> wbinvd();<br> break;<br></pre><p>To view, visit <a href="https://review.coreboot.org/20888">change 20888</a>. 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<div style="display:none"> Gerrit-Project: coreboot </div>
<div style="display:none"> Gerrit-Branch: master </div>
<div style="display:none"> Gerrit-MessageType: newchange </div>
<div style="display:none"> Gerrit-Change-Id: Idd17dd0bd3c644383f273b465a16add184e3b171 </div>
<div style="display:none"> Gerrit-Change-Number: 20888 </div>
<div style="display:none"> Gerrit-PatchSet: 1 </div>
<div style="display:none"> Gerrit-Owner: Furquan Shaikh <furquan@google.com> </div>