<p>Furquan Shaikh has uploaded this change for <strong>review</strong>.</p><p><a href="https://review.coreboot.org/20886">View Change</a></p><pre style="font-family: monospace,monospace; white-space: pre-wrap;">soc/intel/skylake: Enable UART debug controller on S3 resume<br><br>1. Add a new variable to GNVS to store information during S3 suspend<br>whether UART debug port controller is enabled.<br><br>2. On resume, read stored GNVS variable to decide if UART debug port<br>controller needs to be initialized.<br><br>3. Provide helpers functions required by intel/common UART driver for<br>enabling controller on S3 resume.<br><br>BUG=b:64030366<br>TEST=Verified behavior with different combinations:<br>1. Serial console enabled in coreboot: No change in behavior.<br>2. Serial console enabled only in kernel: Coreboot initializes debug<br>controller on S3 resume.<br>3. Serial console not enabled in coreboot and kernel: Coreboot skips<br>initialization of debug controller on S3 resume.<br><br>Change-Id: Iad1cc974bc396ecd55b05ebb6591eec6cedfa16c<br>---<br>M src/soc/intel/skylake/Makefile.inc<br>M src/soc/intel/skylake/acpi/globalnvs.asl<br>M src/soc/intel/skylake/include/soc/nvs.h<br>M src/soc/intel/skylake/smihandler.c<br>M src/soc/intel/skylake/uart.c<br>5 files changed, 27 insertions(+), 2 deletions(-)<br><br></pre><pre style="font-family: monospace,monospace; white-space: pre-wrap;">git pull ssh://review.coreboot.org:29418/coreboot refs/changes/86/20886/1</pre><pre style="font-family: monospace,monospace; white-space: pre-wrap;">diff --git a/src/soc/intel/skylake/Makefile.inc b/src/soc/intel/skylake/Makefile.inc<br>index 7f618d4..baf6f01 100644<br>--- a/src/soc/intel/skylake/Makefile.inc<br>+++ b/src/soc/intel/skylake/Makefile.inc<br>@@ -76,6 +76,7 @@<br> smm-y += smihandler.c<br> smm-$(CONFIG_SPI_FLASH_SMM) += spi.c<br> smm-$(CONFIG_UART_DEBUG) += uart_debug.c<br>+smm-y += uart.c<br> <br> postcar-y += memmap.c<br> postcar-$(CONFIG_UART_DEBUG) += uart_debug.c<br>diff --git a/src/soc/intel/skylake/acpi/globalnvs.asl b/src/soc/intel/skylake/acpi/globalnvs.asl<br>index d06269f..8a7606c 100644<br>--- a/src/soc/intel/skylake/acpi/globalnvs.asl<br>+++ b/src/soc/intel/skylake/acpi/globalnvs.asl<br>@@ -66,6 +66,7 @@<br> CID1, 16, // 0x3d - Wifi Country Identifier<br> U2WE, 16, // 0x3f - USB2 Wake Enable Bitmap<br> U3WE, 8, // 0x41 - USB3 Wake Enable Bitmap<br>+ UIOR, 8, // 0x42 - UART debug controller init on S3 resume<br> <br> /* ChromeOS specific */<br> Offset (0x100),<br>diff --git a/src/soc/intel/skylake/include/soc/nvs.h b/src/soc/intel/skylake/include/soc/nvs.h<br>index 4ca3d22..8272336 100644<br>--- a/src/soc/intel/skylake/include/soc/nvs.h<br>+++ b/src/soc/intel/skylake/include/soc/nvs.h<br>@@ -57,7 +57,8 @@<br> u16 cid1; /* 0x3d - Wifi Country Identifier */<br> u16 u2we; /* 0x3f - USB2 Wake Enable Bitmap */<br> u8 u3we; /* 0x41 - USB3 Wake Enable Bitmap */<br>- u8 unused[190];<br>+ u8 uior; /* 0x42 - UART debug controller init on S3 resume */<br>+ u8 unused[189];<br> <br> /* ChromeOS specific (0x100 - 0xfff) */<br> chromeos_acpi_t chromeos;<br>diff --git a/src/soc/intel/skylake/smihandler.c b/src/soc/intel/skylake/smihandler.c<br>index c4c4a7b..d87994e 100644<br>--- a/src/soc/intel/skylake/smihandler.c<br>+++ b/src/soc/intel/skylake/smihandler.c<br>@@ -24,6 +24,7 @@<br> #include <elog.h><br> #include <intelblocks/fast_spi.h><br> #include <intelblocks/pcr.h><br>+#include <intelblocks/uart.h><br> #include <delay.h><br> #include <device/pci_def.h><br> #include <elog.h><br>@@ -165,6 +166,8 @@<br> case ACPI_S3:<br> printk(BIOS_DEBUG, "SMI#: Entering S3 (Suspend-To-RAM)\n");<br> <br>+ gnvs->uior = uart_debug_controller_is_initialized();<br>+<br> /* Invalidate the cache before going to S3 */<br> wbinvd();<br> break;<br>diff --git a/src/soc/intel/skylake/uart.c b/src/soc/intel/skylake/uart.c<br>index 07326d5..f254400 100644<br>--- a/src/soc/intel/skylake/uart.c<br>+++ b/src/soc/intel/skylake/uart.c<br>@@ -14,16 +14,19 @@<br> * GNU General Public License for more details.<br> */<br> <br>+#include <cbmem.h><br> #include <device/pci.h><br> #include <intelblocks/uart.h><br> #include <soc/iomap.h><br>+#include <soc/nvs.h><br> #include <soc/pci_devs.h><br> <br>-static int pch_uart_is_debug(struct device *dev)<br>+bool pch_uart_is_debug(struct device *dev)<br> {<br> return dev->path.pci.devfn == PCH_DEVFN_UART2;<br> }<br> <br>+#if ENV_RAMSTAGE<br> void pch_uart_read_resources(struct device *dev)<br> {<br> pci_dev_read_resources(dev);<br>@@ -38,3 +41,19 @@<br> IORESOURCE_FIXED;<br> }<br> }<br>+#endif<br>+<br>+bool pch_uart_init_debug_controller_on_resume(void)<br>+{<br>+ global_nvs_t *gnvs = cbmem_find(CBMEM_ID_ACPI_GNVS);<br>+<br>+ if (gnvs)<br>+ return !!gnvs->uior;<br>+<br>+ return false;<br>+}<br>+<br>+device_t pch_uart_get_debug_controller(void)<br>+{<br>+ return PCH_DEV_UART2;<br>+}<br></pre><p>To view, visit <a href="https://review.coreboot.org/20886">change 20886</a>. To unsubscribe, visit <a href="https://review.coreboot.org/settings">settings</a>.</p><div itemscope itemtype="http://schema.org/EmailMessage"><div itemscope itemprop="action" itemtype="http://schema.org/ViewAction"><link itemprop="url" href="https://review.coreboot.org/20886"/><meta itemprop="name" content="View Change"/></div></div>
<div style="display:none"> Gerrit-Project: coreboot </div>
<div style="display:none"> Gerrit-Branch: master </div>
<div style="display:none"> Gerrit-MessageType: newchange </div>
<div style="display:none"> Gerrit-Change-Id: Iad1cc974bc396ecd55b05ebb6591eec6cedfa16c </div>
<div style="display:none"> Gerrit-Change-Number: 20886 </div>
<div style="display:none"> Gerrit-PatchSet: 1 </div>
<div style="display:none"> Gerrit-Owner: Furquan Shaikh <furquan@google.com> </div>