<p>Mariusz Szafranski has uploaded this change for <strong>review</strong>.</p><p><a href="https://review.coreboot.org/20862">View Change</a></p><pre style="font-family: monospace,monospace; white-space: pre-wrap;">mainboard/intel/harcuvar: Add support for Intel Harcuvar CRB<br><br>Intel Harcuvar CRB is a reference board for Denverton_NS SoC.<br><br>Change-Id: I088833e36e2d22d1fe1610b8dca1454092da511a<br>Signed-off-by: Mariusz Szafranski <mariuszx.szafranski@intel.com><br>---<br>A src/mainboard/intel/harcuvar/Kconfig<br>A src/mainboard/intel/harcuvar/Kconfig.name<br>A src/mainboard/intel/harcuvar/Makefile.inc<br>A src/mainboard/intel/harcuvar/acpi/mainboard.asl<br>A src/mainboard/intel/harcuvar/acpi/mainboard_pci_irqs.asl<br>A src/mainboard/intel/harcuvar/acpi/platform.asl<br>A src/mainboard/intel/harcuvar/acpi/thermal.asl<br>A src/mainboard/intel/harcuvar/acpi_tables.c<br>A src/mainboard/intel/harcuvar/board_info.txt<br>A src/mainboard/intel/harcuvar/boardid.c<br>A src/mainboard/intel/harcuvar/devicetree.cb<br>A src/mainboard/intel/harcuvar/dsdt.asl<br>A src/mainboard/intel/harcuvar/emmc.h<br>A src/mainboard/intel/harcuvar/fadt.c<br>A src/mainboard/intel/harcuvar/gpio.h<br>A src/mainboard/intel/harcuvar/harcuvar_boardid.h<br>A src/mainboard/intel/harcuvar/hsio.h<br>A src/mainboard/intel/harcuvar/ramstage.c<br>A src/mainboard/intel/harcuvar/romstage.c<br>A src/mainboard/intel/harcuvar/spd/Makefile.inc<br>A src/mainboard/intel/harcuvar/spd/micron_4GiB_dimm_MTA9ASF51272PZ-2G1A2.spd.hex<br>A src/mainboard/intel/harcuvar/spd/micron_4GiB_sodimm_MTA8ATF51264HZ-2G1A2.spd.hex<br>A src/mainboard/intel/harcuvar/spd/spd.c<br>A src/mainboard/intel/harcuvar/spd/spd.h<br>24 files changed, 3,323 insertions(+), 0 deletions(-)<br><br></pre><pre style="font-family: monospace,monospace; white-space: pre-wrap;">git pull ssh://review.coreboot.org:29418/coreboot refs/changes/62/20862/1</pre><pre style="font-family: monospace,monospace; white-space: pre-wrap;">diff --git a/src/mainboard/intel/harcuvar/Kconfig b/src/mainboard/intel/harcuvar/Kconfig<br>new file mode 100644<br>index 0000000..e753b89<br>--- /dev/null<br>+++ b/src/mainboard/intel/harcuvar/Kconfig<br>@@ -0,0 +1,63 @@<br>+##<br>+## This file is part of the coreboot project.<br>+##<br>+## Copyright (C) 2014 - 2017 Intel Corporation.<br>+##<br>+## This program is free software; you can redistribute it and/or modify<br>+## it under the terms of the GNU General Public License as published by<br>+## the Free Software Foundation; version 2 of the License.<br>+##<br>+## This program is distributed in the hope that it will be useful,<br>+## but WITHOUT ANY WARRANTY; without even the implied warranty of<br>+## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the<br>+## GNU General Public License for more details.<br>+##<br>+<br>+if BOARD_INTEL_HARCUVAR<br>+<br>+config BOARD_SPECIFIC_OPTIONS<br>+ def_bool y<br>+ select SOC_INTEL_DENVERTON_NS<br>+ select BOARD_ROMSIZE_KB_16384<br>+ select HAVE_ACPI_TABLES<br>+<br>+config MAINBOARD_DIR<br>+ string<br>+ default intel/harcuvar<br>+<br>+config MAINBOARD_PART_NUMBER<br>+ string<br>+ default "Harcuvar CRB"<br>+<br>+config MAINBOARD_VENDOR<br>+ string<br>+ default "Intel"<br>+<br>+config ENABLE_FSP_MEMORY_DOWN<br>+ bool "Enable Memory Down"<br>+ default n<br>+ help<br>+ Select this option to enable Memory Down function.<br>+<br>+config ENABLE_MEMORY_DOWN_CH0<br>+ depends on ENABLE_FSP_MEMORY_DOWN<br>+ bool "Enable Memory Down on DIMM Channel 0"<br>+ default y<br>+ help<br>+ Select this option to enable Memory Down on channel 0.<br>+<br>+config ENABLE_MEMORY_DOWN_CH1<br>+ depends on ENABLE_FSP_MEMORY_DOWN<br>+ bool "Enable Memory Down on DIMM Channel 1"<br>+ default y<br>+ help<br>+ Select this option to enable Memory Down on channel 1.<br>+<br>+config SPD_LOC<br>+ depends on ENABLE_FSP_MEMORY_DOWN<br>+ hex "SPD binary location in cbfs"<br>+ default 0xfffdf000<br>+ help<br>+ Location of SPD binary for memory down function.<br>+<br>+endif # BOARD_INTEL_HARCUVAR<br>diff --git a/src/mainboard/intel/harcuvar/Kconfig.name b/src/mainboard/intel/harcuvar/Kconfig.name<br>new file mode 100644<br>index 0000000..1e8ba8e<br>--- /dev/null<br>+++ b/src/mainboard/intel/harcuvar/Kconfig.name<br>@@ -0,0 +1,2 @@<br>+config BOARD_INTEL_HARCUVAR<br>+ bool "Harcuvar CRB"<br>diff --git a/src/mainboard/intel/harcuvar/Makefile.inc b/src/mainboard/intel/harcuvar/Makefile.inc<br>new file mode 100644<br>index 0000000..ba88569<br>--- /dev/null<br>+++ b/src/mainboard/intel/harcuvar/Makefile.inc<br>@@ -0,0 +1,25 @@<br>+##<br>+## This file is part of the coreboot project.<br>+##<br>+## Copyright (C) 2014 - 2017 Intel Corporation.<br>+##<br>+## This program is free software; you can redistribute it and/or modify<br>+## it under the terms of the GNU General Public License as published by<br>+## the Free Software Foundation; version 2 of the License.<br>+##<br>+## This program is distributed in the hope that it will be useful,<br>+## but WITHOUT ANY WARRANTY; without even the implied warranty of<br>+## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the<br>+## GNU General Public License for more details.<br>+##<br>+<br>+subdirs-$(CONFIG_ENABLE_FSP_MEMORY_DOWN) += spd<br>+<br>+romstage-y += boardid.c<br>+<br>+ramstage-y += ramstage.c<br>+ramstage-y += boardid.c<br>+ramstage-$(CONFIG_HAVE_ACPI_TABLES) += acpi_tables.c<br>+ramstage-$(CONFIG_HAVE_ACPI_TABLES) += fadt.c<br>+<br>+CPPFLAGS_common += -Isrc/mainboard/$(MAINBOARDDIR)/<br>diff --git a/src/mainboard/intel/harcuvar/acpi/mainboard.asl b/src/mainboard/intel/harcuvar/acpi/mainboard.asl<br>new file mode 100644<br>index 0000000..41da382<br>--- /dev/null<br>+++ b/src/mainboard/intel/harcuvar/acpi/mainboard.asl<br>@@ -0,0 +1,27 @@<br>+/*<br>+ * This file is part of the coreboot project.<br>+ *<br>+ * Copyright (C) 2011 Google Inc.<br>+ * Copyright (C) 2014 - 2017 Intel Corporation.<br>+ *<br>+ * This program is free software; you can redistribute it and/or modify<br>+ * it under the terms of the GNU General Public License as published by<br>+ * the Free Software Foundation; version 2 of the License.<br>+ *<br>+ * This program is distributed in the hope that it will be useful,<br>+ * but WITHOUT ANY WARRANTY; without even the implied warranty of<br>+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the<br>+ * GNU General Public License for more details.<br>+ *<br>+ */<br>+<br>+Scope (\_SB)<br>+{<br>+ Device (PWRB)<br>+ {<br>+ Name(_HID, EisaId("PNP0C0C"))<br>+<br>+ // Wake<br>+ Name(_PRW, Package(){0x1d, 0x05})<br>+ }<br>+}<br>diff --git a/src/mainboard/intel/harcuvar/acpi/mainboard_pci_irqs.asl b/src/mainboard/intel/harcuvar/acpi/mainboard_pci_irqs.asl<br>new file mode 100644<br>index 0000000..e253cea<br>--- /dev/null<br>+++ b/src/mainboard/intel/harcuvar/acpi/mainboard_pci_irqs.asl<br>@@ -0,0 +1,187 @@<br>+/*<br>+ * This file is part of the coreboot project.<br>+ *<br>+ * Copyright (C) 2014 - 2017 Intel Corporation.<br>+ *<br>+ * This program is free software; you can redistribute it and/or modify<br>+ * it under the terms of the GNU General Public License as published by<br>+ * the Free Software Foundation; version 2 of the License.<br>+ *<br>+ * This program is distributed in the hope that it will be useful,<br>+ * but WITHOUT ANY WARRANTY; without even the implied warranty of<br>+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the<br>+ * GNU General Public License for more details.<br>+ *<br>+ */<br>+<br>+/* This is board specific information: IRQ routing */<br>+<br>+// PCI Interrupt Routing<br>+Method(_PRT)<br>+{<br>+ If (PICM) {<br>+ Return (Package() {<br>+ // [GREG]: Global Registers<br>+ Package() { 0x0004ffff, 0, 0, 16 },<br>+<br>+ // [RCEC]: Root Complex Event Collector<br>+ Package() { 0x0005ffff, 0, 0, 23 },<br>+<br>+ // [VRP2]: Virtual root port 2<br>+ Package() { 0x0006ffff, 2, 0, 18 },<br>+<br>+ // [PEX0]: PCI Express Port 0<br>+ Package() { 0x0009ffff, 0, 0, 16 },<br>+<br>+ // [PEX1]: PCI Express Port 1<br>+ Package() { 0x000affff, 1, 0, 17 },<br>+<br>+ // [PEX2]: PCI Express Port 2<br>+ Package() { 0x000bffff, 2, 0, 18 },<br>+<br>+ // [PEX3]: PCI Express Port 3<br>+ Package() { 0x000cffff, 3, 0, 19 },<br>+<br>+ // [PEX4]: PCI Express Port 4<br>+ Package() { 0x000effff, 0, 0, 20 },<br>+<br>+ // [PEX5]: PCI Express Port 5<br>+ Package() { 0x000fffff, 1, 0, 21 },<br>+<br>+ // [PEX6]: PCI Express Port 6<br>+ Package() { 0x0010ffff, 2, 0, 22 },<br>+<br>+ // [PEX7]: PCI Express Port 7<br>+ Package() { 0x0011ffff, 3, 0, 23 },<br>+<br>+ // [SMB1]: SMBus controller<br>+ Package() { 0x0012ffff, 0, 0, 16 },<br>+<br>+ // [SAT0]: SATA controller 0<br>+ Package() { 0x0013ffff, 0, 0, 20 },<br>+<br>+ // [SAT1]: SATA controller 1<br>+ Package() { 0x0014ffff, 0, 0, 21 },<br>+<br>+ // [XHC0]: XHCI USB controller<br>+ Package() { 0x0015ffff, 0, 0, 19 },<br>+<br>+ // [VRP0]: Virtual root port 0<br>+ Package() { 0x0016ffff, 0, 0, 16 },<br>+<br>+ // [VRP1]: Virtual root port 1<br>+ Package() { 0x0017ffff, 1, 0, 17 },<br>+<br>+ // [HECI]: ME HECI<br>+ Package() { 0x0018ffff, 0, 0, 16 },<br>+<br>+ // [HEC2]: ME HECI2<br>+ Package() { 0x0018ffff, 1, 0, 17 },<br>+<br>+ // [MEKT]: MEKT on PCH<br>+ Package() { 0x0018ffff, 2, 0, 18 },<br>+<br>+ // [HEC3]: ME HECI3<br>+ Package() { 0x0018ffff, 3, 0, 19 },<br>+<br>+ // [UAR0]: UART 0<br>+ Package() { 0x001affff, 0, 0, 16 },<br>+<br>+ // [UAR1]: UART 1<br>+ Package() { 0x001affff, 1, 0, 17 },<br>+<br>+ // [UAR2]: UART 2<br>+ Package() { 0x001affff, 2, 0, 18 },<br>+<br>+ // [EMMC]: eMMC<br>+ Package() { 0x001cffff, 0, 0, 16 },<br>+<br>+ // [P2SB]: Primary to sideband bridge<br>+ // [SMB0]: SMBus controller<br>+ // [NPK0]: Northpeak DFX<br>+ Package() { 0x001fffff, 0, 0, 23 },<br>+ })<br>+ } Else {<br>+ Return (Package() {<br>+ // [GREG]: Global Registers 0:4.0<br>+ Package() { 0x0004ffff, 0, \_SB.PCI0.LPCB.LNKA, 0 },<br>+<br>+ // [RCEC]: Root Complex Event Collector 0:5.0<br>+ Package() { 0x0005ffff, 0, \_SB.PCI0.LPCB.LNKH, 0 },<br>+<br>+ // [VRP2]: Virtual root port 2 0:6.0<br>+ Package() { 0x0006ffff, 2, \_SB.PCI0.LPCB.LNKC, 0 },<br>+<br>+ // [PEX0]: PCI Express Port 0 0:9.0<br>+ Package() { 0x0009ffff, 0, \_SB.PCI0.LPCB.LNKA, 0 },<br>+<br>+ // [PEX1]: PCI Express Port 1 0:a.0<br>+ Package() { 0x000affff, 1, \_SB.PCI0.LPCB.LNKB, 0 },<br>+<br>+ // [PEX2]: PCI Express Port 2 0:b.0<br>+ Package() { 0x000bffff, 2, \_SB.PCI0.LPCB.LNKC, 0 },<br>+<br>+ // [PEX3]: PCI Express Port 3 0:c.0<br>+ Package() { 0x000cffff, 3, \_SB.PCI0.LPCB.LNKD, 0 },<br>+<br>+ // [PEX4]: PCI Express Port 4 0:e.0<br>+ Package() { 0x000effff, 0, \_SB.PCI0.LPCB.LNKE, 0 },<br>+<br>+ // [PEX5]: PCI Express Port 5 0:f.0<br>+ Package() { 0x000fffff, 1, \_SB.PCI0.LPCB.LNKF, 0 },<br>+<br>+ // [PEX6]: PCI Express Port 6 0:10.0<br>+ Package() { 0x0010ffff, 2, \_SB.PCI0.LPCB.LNKG, 0 },<br>+<br>+ // [PEX7]: PCI Express Port 7 0:11.0<br>+ Package() { 0x0011ffff, 3, \_SB.PCI0.LPCB.LNKH, 0 },<br>+<br>+ // [SMB1]: SMBus controller 0:12.0<br>+ Package() { 0x0012ffff, 0, \_SB.PCI0.LPCB.LNKA, 0 },<br>+<br>+ // [SAT0]: SATA controller 0 0:13.0<br>+ Package() { 0x0013ffff, 0, \_SB.PCI0.LPCB.LNKE, 0 },<br>+<br>+ // [SAT1]: SATA controller 1 0:14.0<br>+ Package() { 0x0014ffff, 0, \_SB.PCI0.LPCB.LNKF, 0 },<br>+<br>+ // [XHC0]: XHCI USB controller 0:15.0<br>+ Package() { 0x0015ffff, 0, \_SB.PCI0.LPCB.LNKD, 0 },<br>+<br>+ // [VRP0]: Virtual root port 0 0:16.0<br>+ Package() { 0x0016ffff, 0, \_SB.PCI0.LPCB.LNKA, 0 },<br>+<br>+ // [VRP1]: Virtual root port 1 0:17.0<br>+ Package() { 0x0017ffff, 1, \_SB.PCI0.LPCB.LNKB, 0 },<br>+<br>+ // [HECI]: ME HECI 0:18.0<br>+ Package() { 0x0018ffff, 0, \_SB.PCI0.LPCB.LNKA, 0 },<br>+<br>+ // [HEC2]: ME HECI2 0:18.1<br>+ Package() { 0x0018ffff, 1, \_SB.PCI0.LPCB.LNKB, 0 },<br>+<br>+ // [MEKT]: MEKT on PCH 0:18.2<br>+ Package() { 0x0018ffff, 2, \_SB.PCI0.LPCB.LNKC, 0 },<br>+<br>+ // [HEC3]: ME HECI3 0:18.3<br>+ Package() { 0x0018ffff, 3, \_SB.PCI0.LPCB.LNKD, 0 },<br>+<br>+ // [UAR0]: UART 0 0:1a.0<br>+ Package() { 0x001affff, 0, \_SB.PCI0.LPCB.LNKA, 0 },<br>+<br>+ // [UAR1]: UART 1 0:1a.1<br>+ Package() { 0x001affff, 1, \_SB.PCI0.LPCB.LNKB, 0 },<br>+<br>+ // [UAR2]: UART 2 0:1a.2<br>+ Package() { 0x001affff, 2, \_SB.PCI0.LPCB.LNKC, 0 },<br>+<br>+ // [EMMC]: eMMC 0:1c.0<br>+ Package() { 0x001cffff, 0, \_SB.PCI0.LPCB.LNKA, 0 },<br>+<br>+ // [P2SB]: Primary to sideband bridge<br>+ // [SMB0]: SMBus controller<br>+ // [NPK0]: Northpeak DFX<br>+ Package() { 0x001ffffF, 0, \_SB.PCI0.LPCB.LNKH, 0 },<br>+ })<br>+ }<br>+}<br>diff --git a/src/mainboard/intel/harcuvar/acpi/platform.asl b/src/mainboard/intel/harcuvar/acpi/platform.asl<br>new file mode 100644<br>index 0000000..ea66a9f<br>--- /dev/null<br>+++ b/src/mainboard/intel/harcuvar/acpi/platform.asl<br>@@ -0,0 +1,70 @@<br>+/*<br>+ * This file is part of the coreboot project.<br>+ *<br>+ * Copyright (C) 2007 - 2009 coresystems GmbH<br>+ * Copyright (C) 2012 The Chromium OS Authors. All rights reserved.<br>+ * Copyright (C) 2017 Intel Corporation.<br>+ *<br>+ * This program is free software; you can redistribute it and/or modify<br>+ * it under the terms of the GNU General Public License as published by<br>+ * the Free Software Foundation; version 2 of the License.<br>+ *<br>+ * This program is distributed in the hope that it will be useful,<br>+ * but WITHOUT ANY WARRANTY; without even the implied warranty of<br>+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the<br>+ * GNU General Public License for more details.<br>+ *<br>+ */<br>+<br>+/* The APM port can be used for generating software SMIs */<br>+<br>+OperationRegion (APMP, SystemIO, 0xb2, 2)<br>+Field (APMP, ByteAcc, NoLock, Preserve)<br>+{<br>+ APMC, 8, // APM command<br>+ APMS, 8 // APM status<br>+}<br>+<br>+/* Port 80 POST */<br>+<br>+OperationRegion (POST, SystemIO, 0x80, 1)<br>+Field (POST, ByteAcc, Lock, Preserve)<br>+{<br>+ DBG0, 8<br>+}<br>+<br>+/* SMI I/O Trap */<br>+Method(TRAP, 1, Serialized)<br>+{<br>+ Store (Arg0, SMIF) // SMI Function<br>+ Store (0, TRP0) // Generate trap<br>+ Return (SMIF) // Return value of SMI handler<br>+}<br>+<br>+/* The _PIC method is called by the OS to choose between interrupt<br>+ * routing via the i8259 interrupt controller or the APIC.<br>+ *<br>+ * _PIC is called with a parameter of 0 for i8259 configuration and<br>+ * with a parameter of 1 for Local Apic/IOAPIC configuration.<br>+ */<br>+<br>+Method(_PIC, 1)<br>+{<br>+ // Remember the OS' IRQ routing choice.<br>+ Store(Arg0, PICM)<br>+}<br>+<br>+/* The _PTS method (Prepare To Sleep) is called before the OS is<br>+ * entering a sleep state. The sleep state number is passed in Arg0<br>+ */<br>+<br>+Method(_PTS,1)<br>+{<br>+}<br>+<br>+/* The _WAK method is called on system wakeup */<br>+<br>+Method(_WAK,1)<br>+{<br>+ Return(Package(){0,0})<br>+}<br>diff --git a/src/mainboard/intel/harcuvar/acpi/thermal.asl b/src/mainboard/intel/harcuvar/acpi/thermal.asl<br>new file mode 100644<br>index 0000000..5f9164d<br>--- /dev/null<br>+++ b/src/mainboard/intel/harcuvar/acpi/thermal.asl<br>@@ -0,0 +1,21 @@<br>+/*<br>+ * This file is part of the coreboot project.<br>+ *<br>+ * Copyright (C) 2014 - 2017 Intel Corporation.<br>+ *<br>+ * This program is free software; you can redistribute it and/or modify<br>+ * it under the terms of the GNU General Public License as published by<br>+ * the Free Software Foundation; version 2 of the License.<br>+ *<br>+ * This program is distributed in the hope that it will be useful,<br>+ * but WITHOUT ANY WARRANTY; without even the implied warranty of<br>+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the<br>+ * GNU General Public License for more details.<br>+ *<br>+ */<br>+<br>+ // Thermal Zone<br>+<br>+Scope (\_TZ)<br>+{<br>+}<br>diff --git a/src/mainboard/intel/harcuvar/acpi_tables.c b/src/mainboard/intel/harcuvar/acpi_tables.c<br>new file mode 100644<br>index 0000000..020905c<br>--- /dev/null<br>+++ b/src/mainboard/intel/harcuvar/acpi_tables.c<br>@@ -0,0 +1,65 @@<br>+/*<br>+ * This file is part of the coreboot project.<br>+ *<br>+ * Copyright (C) 2012 The Chromium OS Authors. All rights reserved.<br>+ * Copyright (C) 2014 - 2017 Intel Corporation.<br>+ *<br>+ * This program is free software; you can redistribute it and/or modify<br>+ * it under the terms of the GNU General Public License as published by<br>+ * the Free Software Foundation; version 2 of the License.<br>+ *<br>+ * This program is distributed in the hope that it will be useful,<br>+ * but WITHOUT ANY WARRANTY; without even the implied warranty of<br>+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the<br>+ * GNU General Public License for more details.<br>+ *<br>+ */<br>+<br>+#include <types.h><br>+#include <string.h><br>+#include <cbmem.h><br>+#include <console/console.h><br>+#include <arch/acpi.h><br>+#include <arch/ioapic.h><br>+#include <arch/acpigen.h><br>+#include <arch/smp/mpspec.h><br>+#include <device/device.h><br>+#include <device/pci.h><br>+#include <device/pci_ids.h><br>+#include <cpu/cpu.h><br>+#include <cpu/x86/msr.h><br>+<br>+#include <soc/acpi.h><br>+#include <soc/nvs.h><br>+<br>+extern const unsigned char AmlCode[];<br>+<br>+void acpi_create_gnvs(global_nvs_t *gnvs)<br>+{<br>+ acpi_init_gnvs(gnvs);<br>+<br>+ /* Enable USB ports in S3 */<br>+ gnvs->s3u0 = 1;<br>+ gnvs->s3u1 = 1;<br>+<br>+ /* Disable USB ports in S5 */<br>+ gnvs->s5u0 = 0;<br>+ gnvs->s5u1 = 0;<br>+<br>+ /* TPM Present */<br>+ gnvs->tpmp = 0;<br>+}<br>+<br>+unsigned long acpi_fill_madt(unsigned long current)<br>+{<br>+ /* Local APICs */<br>+ current = acpi_create_madt_lapics(current);<br>+<br>+ /* IOAPIC */<br>+ current += acpi_create_madt_ioapic((acpi_madt_ioapic_t *)current, 2,<br>+ IO_APIC_ADDR, 0);<br>+<br>+ current = acpi_madt_irq_overrides(current);<br>+<br>+ return current;<br>+}<br>diff --git a/src/mainboard/intel/harcuvar/board_info.txt b/src/mainboard/intel/harcuvar/board_info.txt<br>new file mode 100644<br>index 0000000..ad42794<br>--- /dev/null<br>+++ b/src/mainboard/intel/harcuvar/board_info.txt<br>@@ -0,0 +1,6 @@<br>+Vendor name: Intel<br>+Board name: Harcuvar<br>+Category: eval<br>+ROM protocol: SPI<br>+ROM socketed: n<br>+Flashrom support: y<br>diff --git a/src/mainboard/intel/harcuvar/boardid.c b/src/mainboard/intel/harcuvar/boardid.c<br>new file mode 100644<br>index 0000000..7edf364<br>--- /dev/null<br>+++ b/src/mainboard/intel/harcuvar/boardid.c<br>@@ -0,0 +1,28 @@<br>+/*<br>+ * This file is part of the coreboot project.<br>+ *<br>+ * Copyright (C) 2015 - 2017 Intel Corporation.<br>+ *<br>+ * This program is free software; you can redistribute it and/or modify<br>+ * it under the terms of the GNU General Public License as published by<br>+ * the Free Software Foundation; version 2 of the License.<br>+ *<br>+ * This program is distributed in the hope that it will be useful,<br>+ * but WITHOUT ANY WARRANTY; without even the implied warranty of<br>+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the<br>+ * GNU General Public License for more details.<br>+ *<br>+ */<br>+<br>+#include <console/console.h><br>+<br>+#include "harcuvar_boardid.h"<br>+<br>+uint8_t board_id(void)<br>+{<br>+ int id = BoardIdHarcuvar;<br>+<br>+ printk(BIOS_SPEW, "Board ID: %#x.\n", id);<br>+<br>+ return id;<br>+}<br>diff --git a/src/mainboard/intel/harcuvar/devicetree.cb b/src/mainboard/intel/harcuvar/devicetree.cb<br>new file mode 100644<br>index 0000000..e1b68be<br>--- /dev/null<br>+++ b/src/mainboard/intel/harcuvar/devicetree.cb<br>@@ -0,0 +1,74 @@<br>+##<br>+## This file is part of the coreboot project.<br>+##<br>+## Copyright (C) 2014 - 2017 Intel Corporation.<br>+##<br>+## This program is free software; you can redistribute it and/or modify<br>+## it under the terms of the GNU General Public License as published by<br>+## the Free Software Foundation; version 2 of the License.<br>+##<br>+## This program is distributed in the hope that it will be useful,<br>+## but WITHOUT ANY WARRANTY; without even the implied warranty of<br>+## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the<br>+## GNU General Public License for more details.<br>+##<br>+<br>+chip soc/intel/denverton_ns<br>+<br>+ # configure pirq routing<br>+ register "pirqa_routing" = "11"<br>+ register "pirqb_routing" = "10"<br>+ register "pirqc_routing" = "11"<br>+ register "pirqd_routing" = "11"<br>+ register "pirqe_routing" = "11"<br>+ register "pirqf_routing" = "11"<br>+ register "pirqg_routing" = "11"<br>+ register "pirqh_routing" = "11"<br>+ # configure device interrupt routing<br>+ register "ir00_routing" = "0x3217" # IR00<br>+ register "ir01_routing" = "0x3210" # IR01<br>+ register "ir02_routing" = "0x3211" # IR02<br>+ register "ir03_routing" = "0x3217" # IR03<br>+ register "ir04_routing" = "0x3212" # IR04<br>+ register "ir05_routing" = "0x3210" # IR05<br>+ register "ir06_routing" = "0x3214" # IR06<br>+ register "ir07_routing" = "0x3210" # IR07<br>+ register "ir08_routing" = "0x7654" # IR08<br>+ register "ir09_routing" = "0x3213" # IR09<br>+ register "ir10_routing" = "0x3210" # IR10<br>+ register "ir11_routing" = "0x3215" # IR11<br>+ register "ir12_routing" = "0x3210" # IR12<br>+ # configure interrupt polarity control<br>+ register "ipc0" = "0x00ff4000" # IPC0, PIRQA-H (IRQ16-23) should always be ActiveLow<br>+ register "ipc1" = "0x00000000" # IPC1<br>+ register "ipc2" = "0x00000000" # IPC2<br>+ register "ipc3" = "0x00000000" # IPC3<br>+<br>+ device cpu_cluster 0 on<br>+ device lapic 0 on end<br>+ end<br>+<br>+ device domain 0 on<br>+ device pci 00.0 on end # Host Bridge<br>+ device pci 04.0 on end # RAS<br>+ device pci 05.0 on end # RCEC(Root Complex Event Collector)<br>+ device pci 06.0 on end # Virtual root port 2 (QAT)<br>+ device pci 09.0 on end # PCI Express Port 0, cluster #0, x8<br>+ device pci 0e.0 on end # PCI Express Port 4, cluster #1, x4<br>+ device pci 10.0 on end # PCI Express Port 6, cluster #1, x4<br>+ device pci 12.0 on end # SMBus Controller 1<br>+ device pci 14.0 on end # SATA Controller 1<br>+ device pci 15.0 on end # XHCI USB Controller<br>+ device pci 16.0 on end # Virtual root port 0 (10GBE0)<br>+ device pci 17.0 on end # Virtual root port 1 (10GBE1)<br>+ device pci 18.0 on end # CSME HECI 1<br>+ device pci 1a.0 on end # UART 0<br>+ device pci 1a.1 on end # UART 1<br>+ device pci 1a.2 on end # UART 2<br>+ device pci 1c.0 on end # eMMC<br>+ device pci 1f.0 on end # LPC bridge<br>+ device pci 1f.2 on end # PMC/ACPI<br>+ device pci 1f.4 on end # SMBus Controller 0<br>+ device pci 1f.5 on end # SPI Controller<br>+ end<br>+end<br>diff --git a/src/mainboard/intel/harcuvar/dsdt.asl b/src/mainboard/intel/harcuvar/dsdt.asl<br>new file mode 100644<br>index 0000000..4e66d17<br>--- /dev/null<br>+++ b/src/mainboard/intel/harcuvar/dsdt.asl<br>@@ -0,0 +1,53 @@<br>+/*<br>+ * This file is part of the coreboot project.<br>+ *<br>+ * Copyright (C) 2007 - 2009 coresystems GmbH<br>+ * Copyright 2011 Google Inc.<br>+ * Copyright (C) 2014 - 2017 Intel Corporation.<br>+ *<br>+ * This program is free software; you can redistribute it and/or modify<br>+ * it under the terms of the GNU General Public License as published by<br>+ * the Free Software Foundation; version 2 of the License.<br>+ *<br>+ * This program is distributed in the hope that it will be useful,<br>+ * but WITHOUT ANY WARRANTY; without even the implied warranty of<br>+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the<br>+ * GNU General Public License for more details.<br>+ *<br>+ */<br>+<br>+DefinitionBlock(<br>+ "dsdt.aml",<br>+ "DSDT",<br>+ 0x02, // DSDT revision: ACPI v2.0<br>+ "COREv4", // OEM id<br>+ "COREBOOT", // OEM table id<br>+ 0x20110725 // OEM revision<br>+)<br>+{<br>+ // Some generic macros<br>+ #include "acpi/platform.asl"<br>+ #include "acpi/mainboard.asl"<br>+<br>+ // General Purpose Events<br>+ //#include "acpi/gpe.asl"<br>+<br>+ // Thermal Handler<br>+ #include "acpi/thermal.asl"<br>+<br>+ // global NVS and variables<br>+ #include <soc/intel/denverton_ns/acpi/globalnvs.asl><br>+<br>+ #include <soc/intel/denverton_ns/acpi/cpu.asl><br>+<br>+ Scope (\_SB) {<br>+ Device (PCI0)<br>+ {<br>+ #include <soc/intel/denverton_ns/acpi/northcluster.asl><br>+ #include <soc/intel/denverton_ns/acpi/southcluster.asl><br>+ }<br>+ }<br>+<br>+ /* Chipset specific sleep states */<br>+ #include <soc/intel/denverton_ns/acpi/sleepstates.asl><br>+}<br>diff --git a/src/mainboard/intel/harcuvar/emmc.h b/src/mainboard/intel/harcuvar/emmc.h<br>new file mode 100644<br>index 0000000..9832191<br>--- /dev/null<br>+++ b/src/mainboard/intel/harcuvar/emmc.h<br>@@ -0,0 +1,34 @@<br>+/*<br>+ * This file is part of the coreboot project.<br>+ *<br>+ * Copyright (C) 2016 - 2017 Intel Corporation.<br>+ *<br>+ * This program is free software; you can redistribute it and/or modify<br>+ * it under the terms of the GNU General Public License as published by<br>+ * the Free Software Foundation; version 2 of the License.<br>+ *<br>+ * This program is distributed in the hope that it will be useful,<br>+ * but WITHOUT ANY WARRANTY; without even the implied warranty of<br>+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the<br>+ * GNU General Public License for more details.<br>+ *<br>+ */<br>+<br>+#ifndef _MAINBOARD_EMMC_H<br>+#define _MAINBOARD_EMMC_H<br>+<br>+#include <fsp/util.h><br>+<br>+#define DEFAULT_EMMC_DLL_SIGN 0x55aa<br>+<br>+#ifndef __ACPI__<br>+BL_EMMC_INFORMATION harcuvar_emmc_config[] = {<br>+ /*<br>+ * Default eMMC DLL configuration.<br>+ */<br>+ {DEFAULT_EMMC_DLL_SIGN,<br>+ {0x00000508, 0x00000c11, 0x1c2a2a2a, 0x00191e27, 0x00000a0a,<br>+ 0x00010013, 0x00000001} } };<br>+#endif<br>+<br>+#endif /* _MAINBOARD_EMMC_H */<br>diff --git a/src/mainboard/intel/harcuvar/fadt.c b/src/mainboard/intel/harcuvar/fadt.c<br>new file mode 100644<br>index 0000000..9f41f64<br>--- /dev/null<br>+++ b/src/mainboard/intel/harcuvar/fadt.c<br>@@ -0,0 +1,50 @@<br>+/*<br>+ * This file is part of the coreboot project.<br>+ *<br>+ * Copyright (C) 2007 - 2009 coresystems GmbH<br>+ * Copyright (C) 2014 - 2017 Intel Corporation.<br>+ *<br>+ * This program is free software; you can redistribute it and/or modify<br>+ * it under the terms of the GNU General Public License as published by<br>+ * the Free Software Foundation; version 2 of the License.<br>+ *<br>+ * This program is distributed in the hope that it will be useful,<br>+ * but WITHOUT ANY WARRANTY; without even the implied warranty of<br>+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the<br>+ * GNU General Public License for more details.<br>+ *<br>+ */<br>+<br>+#include <string.h><br>+#include <arch/acpi.h><br>+<br>+#include <soc/acpi.h><br>+#include <soc/soc_util.h><br>+<br>+void acpi_create_fadt(acpi_fadt_t *fadt, acpi_facs_t *facs, void *dsdt)<br>+{<br>+ acpi_header_t *header = &(fadt->header);<br>+<br>+ memset((void *)fadt, 0, sizeof(acpi_fadt_t));<br>+ memcpy_s(header->signature, "FACP", 4);<br>+ header->length = sizeof(acpi_fadt_t);<br>+ header->revision = 3;<br>+ memcpy_s(header->oem_id, OEM_ID, 6);<br>+ memcpy_s(header->oem_table_id, ACPI_TABLE_CREATOR, 8);<br>+ memcpy_s(header->asl_compiler_id, ASLC, 4);<br>+ header->asl_compiler_revision = 1;<br>+<br>+ fadt->firmware_ctrl = (unsigned long)facs;<br>+ fadt->dsdt = (unsigned long)dsdt;<br>+ fadt->model = 1;<br>+ fadt->preferred_pm_profile = PM_ENTERPRISE_SERVER;<br>+<br>+ fadt->x_firmware_ctl_l = (unsigned long)facs;<br>+ fadt->x_firmware_ctl_h = 0;<br>+ fadt->x_dsdt_l = (unsigned long)dsdt;<br>+ fadt->x_dsdt_h = 0;<br>+<br>+ acpi_fill_in_fadt(fadt);<br>+<br>+ header->checksum = acpi_checksum((void *)fadt, header->length);<br>+}<br>diff --git a/src/mainboard/intel/harcuvar/gpio.h b/src/mainboard/intel/harcuvar/gpio.h<br>new file mode 100644<br>index 0000000..a96b435<br>--- /dev/null<br>+++ b/src/mainboard/intel/harcuvar/gpio.h<br>@@ -0,0 +1,635 @@<br>+/*<br>+ * This file is part of the coreboot project.<br>+ *<br>+ * Copyright (C) 2014 - 2017 Intel Corporation.<br>+ *<br>+ * This program is free software; you can redistribute it and/or modify<br>+ * it under the terms of the GNU General Public License as published by<br>+ * the Free Software Foundation; version 2 of the License.<br>+ *<br>+ * This program is distributed in the hope that it will be useful,<br>+ * but WITHOUT ANY WARRANTY; without even the implied warranty of<br>+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the<br>+ * GNU General Public License for more details.<br>+ *<br>+ */<br>+<br>+#ifndef _MAINBOARD_GPIO_H<br>+#define _MAINBOARD_GPIO_H<br>+<br>+#include <soc/gpio.h><br>+<br>+#ifndef __ACPI__<br>+const struct pad_config harcuvar_gpio_table[] = {<br>+ // GBE0_SDP0 (GPIO_14)<br>+ {NORTH_ALL_GBE0_SDP0,<br>+ {GpioPadModeNative1, GpioHostOwnGpio, GpioDirInOut, GpioOutDefault,<br>+ GpioIntDefault, GpioResetDefault, GpioTermDefault, GpioLockDefault} },<br>+ // GBE1_SDP0 (GPIO_15)<br>+ {NORTH_ALL_GBE1_SDP0,<br>+ {GpioPadModeNative1, GpioHostOwnGpio, GpioDirInOut, GpioOutDefault,<br>+ GpioIntDefault, GpioResetDefault, GpioTermDefault, GpioLockDefault} },<br>+ // GBE2_I2C_CLK (GPIO_16)<br>+ {NORTH_ALL_GBE0_SDP1,<br>+ {GpioPadModeNative2, GpioHostOwnGpio, GpioDirOut, GpioOutDefault,<br>+ GpioIntDefault, GpioResetDefault, GpioTermDefault, GpioLockDefault} },<br>+ // GBE2_I2C_DATA (GPIO_17)<br>+ {NORTH_ALL_GBE1_SDP1,<br>+ {GpioPadModeNative2, GpioHostOwnGpio, GpioDirInOut, GpioOutDefault,<br>+ GpioIntDefault, GpioResetDefault, GpioTermDefault, GpioLockDefault} },<br>+ // GBE2_SDP0 (GPIO_18)<br>+ {NORTH_ALL_GBE0_SDP2,<br>+ {GpioPadModeNative2, GpioHostOwnGpio, GpioDirInOut, GpioOutDefault,<br>+ GpioIntDefault, GpioResetDefault, GpioTermDefault, GpioLockDefault} },<br>+ // GBE3_SDP0 (GPIO_19)<br>+ {NORTH_ALL_GBE1_SDP2,<br>+ {GpioPadModeNative2, GpioHostOwnGpio, GpioDirInOut, GpioOutDefault,<br>+ GpioIntDefault, GpioResetDefault, GpioTermDefault, GpioLockDefault} },<br>+ // GBE3_I2C_CLK (GPIO_20)<br>+ {NORTH_ALL_GBE0_SDP3,<br>+ {GpioPadModeNative2, GpioHostOwnGpio, GpioDirOut, GpioOutDefault,<br>+ GpioIntDefault, GpioResetDefault, GpioTermDefault, GpioLockDefault} },<br>+ // GBE3_I2C_DATA (GPIO_21)<br>+ {NORTH_ALL_GBE1_SDP3,<br>+ {GpioPadModeNative2, GpioHostOwnGpio, GpioDirInOut, GpioOutDefault,<br>+ GpioIntDefault, GpioResetDefault, GpioTermDefault, GpioLockDefault} },<br>+ // GBE2_LED0 (GPIO_22)<br>+ {NORTH_ALL_GBE2_LED0,<br>+ {GpioPadModeNative1, GpioHostOwnGpio, GpioDirOut, GpioOutDefault,<br>+ GpioIntDefault, GpioResetDefault, GpioTermDefault, GpioLockDefault} },<br>+ // GBE2_LED1 (GPIO_23)<br>+ {NORTH_ALL_GBE2_LED1,<br>+ {GpioPadModeNative1, GpioHostOwnGpio, GpioDirOut, GpioOutDefault,<br>+ GpioIntDefault, GpioResetDefault, GpioTermDefault, GpioLockDefault} },<br>+ // GBE0_I2C_CLK (GPIO_24)<br>+ {NORTH_ALL_GBE0_I2C_CLK,<br>+ {GpioPadModeNative1, GpioHostOwnGpio, GpioDirOut, GpioOutDefault,<br>+ GpioIntDefault, GpioResetDefault, GpioTermDefault, GpioLockDefault} },<br>+ // GBE0_I2C_DATA (GPIO_25)<br>+ {NORTH_ALL_GBE0_I2C_DATA,<br>+ {GpioPadModeNative1, GpioHostOwnGpio, GpioDirInOut, GpioOutDefault,<br>+ GpioIntDefault, GpioResetDefault, GpioTermDefault, GpioLockDefault} },<br>+ // GBE1_I2C_CLK (GPIO_26)<br>+ {NORTH_ALL_GBE1_I2C_CLK,<br>+ {GpioPadModeNative1, GpioHostOwnGpio, GpioDirOut, GpioOutDefault,<br>+ GpioIntDefault, GpioResetDefault, GpioTermDefault, GpioLockDefault} },<br>+ // GBE1_I2C_DATA (GPIO_27)<br>+ {NORTH_ALL_GBE1_I2C_DATA,<br>+ {GpioPadModeNative1, GpioHostOwnGpio, GpioDirInOut, GpioOutDefault,<br>+ GpioIntDefault, GpioResetDefault, GpioTermDefault, GpioLockDefault} },<br>+ // NCSI_RXD0 (GPIO_28)<br>+ {NORTH_ALL_NCSI_RXD0,<br>+ {GpioPadModeNative2, GpioHostOwnGpio, GpioDirIn, GpioOutDefault,<br>+ GpioIntDefault, GpioResetPwrGood, GpioTermDefault, GpioLockDefault} },<br>+ // NCSI_CLK_IN (GPIO_29)<br>+ {NORTH_ALL_NCSI_CLK_IN,<br>+ {GpioPadModeNative2, GpioHostOwnGpio, GpioDirIn, GpioOutDefault,<br>+ GpioIntDefault, GpioResetPwrGood, GpioTermDefault, GpioLockDefault} },<br>+ // NCSI_RXD1 (GPIO_30)<br>+ {NORTH_ALL_NCSI_RXD1,<br>+ {GpioPadModeNative2, GpioHostOwnGpio, GpioDirIn, GpioOutDefault,<br>+ GpioIntDefault, GpioResetPwrGood, GpioTermDefault, GpioLockDefault} },<br>+ // NCSI_CRS_DV (GPIO_31)<br>+ {NORTH_ALL_NCSI_CRS_DV,<br>+ {GpioPadModeNative2, GpioHostOwnGpio, GpioDirIn, GpioOutDefault,<br>+ GpioIntDefault, GpioResetPwrGood, GpioTermDefault, GpioLockDefault} },<br>+ // NCSI_ARB_IN (GPIO_32)<br>+ {NORTH_ALL_NCSI_ARB_IN,<br>+ {GpioPadModeNative2, GpioHostOwnGpio, GpioDirIn, GpioOutDefault,<br>+ GpioIntDefault, GpioResetPwrGood, GpioTermDefault, GpioLockDefault} },<br>+ // NCSI_TX_EN (GPIO_33)<br>+ {NORTH_ALL_NCSI_TX_EN,<br>+ {GpioPadModeNative2, GpioHostOwnGpio, GpioDirIn, GpioOutDefault,<br>+ GpioIntDefault, GpioResetPwrGood, GpioTermDefault, GpioLockDefault} },<br>+ // NCSI_TXD0 (GPIO_34)<br>+ {NORTH_ALL_NCSI_TXD0,<br>+ {GpioPadModeNative2, GpioHostOwnGpio, GpioDirOut, GpioOutDefault,<br>+ GpioIntDefault, GpioResetPwrGood, GpioTermDefault, GpioLockDefault} },<br>+ // NCSI_TXD1 (GPIO_35)<br>+ {NORTH_ALL_NCSI_TXD1,<br>+ {GpioPadModeNative2, GpioHostOwnGpio, GpioDirOut, GpioOutDefault,<br>+ GpioIntDefault, GpioResetPwrGood, GpioTermDefault, GpioLockDefault} },<br>+ // NCSI_ARB_OUT (GPIO_36)<br>+ {NORTH_ALL_NCSI_ARB_OUT,<br>+ {GpioPadModeNative2, GpioHostOwnGpio, GpioDirOut, GpioOutDefault,<br>+ GpioIntDefault, GpioResetPwrGood, GpioTermDefault, GpioLockDefault} },<br>+ // GBE0_LED0 (GPIO_37)<br>+ {NORTH_ALL_GBE0_LED0,<br>+ {GpioPadModeNative1, GpioHostOwnGpio, GpioDirOut, GpioOutDefault,<br>+ GpioIntDefault, GpioResetPwrGood, GpioTermDefault, GpioLockDefault} },<br>+ // GBE0_LED1 (GPIO_38)<br>+ {NORTH_ALL_GBE0_LED1,<br>+ {GpioPadModeNative1, GpioHostOwnGpio, GpioDirOut, GpioOutDefault,<br>+ GpioIntDefault, GpioResetPwrGood, GpioTermDefault, GpioLockDefault} },<br>+ // GBE1_LED0 (GPIO_39)<br>+ {NORTH_ALL_GBE1_LED0,<br>+ {GpioPadModeNative1, GpioHostOwnGpio, GpioDirOut, GpioOutDefault,<br>+ GpioIntDefault, GpioResetPwrGood, GpioTermDefault, GpioLockDefault} },<br>+ // GBE1_LED1 (GPIO_40)<br>+ {NORTH_ALL_GBE1_LED1,<br>+ {GpioPadModeNative1, GpioHostOwnGpio, GpioDirOut, GpioOutDefault,<br>+ GpioIntDefault, GpioResetPwrGood, GpioTermDefault, GpioLockDefault} },<br>+ // ADR-COMPLETE (GPIO_0)<br>+ {NORTH_ALL_GPIO_0,<br>+ {GpioPadModeNative3, GpioHostOwnGpio, GpioDirOut, GpioOutDefault,<br>+ GpioIntDefault, GpioResetDefault, GpioTermDefault, GpioLockDefault} },<br>+ // PCIE_CLKREQ0_N (GPIO_41)<br>+ {NORTH_ALL_PCIE_CLKREQ0_N,<br>+ {GpioPadModeNative1, GpioHostOwnGpio, GpioDirIn, GpioOutDefault,<br>+ GpioIntDefault, GpioResetDefault, GpioTermDefault, GpioLockDefault} },<br>+ // PCIE_CLKREQ1_N (GPIO_42)<br>+ {NORTH_ALL_PCIE_CLKREQ1_N,<br>+ {GpioPadModeNative1, GpioHostOwnGpio, GpioDirIn, GpioOutDefault,<br>+ GpioIntDefault, GpioResetDefault, GpioTermDefault, GpioLockDefault} },<br>+ // PCIE_CLKREQ2_N (GPIO_43)<br>+ {NORTH_ALL_PCIE_CLKREQ2_N,<br>+ {GpioPadModeNative1, GpioHostOwnGpio, GpioDirIn, GpioOutDefault,<br>+ GpioIntDefault, GpioResetDefault, GpioTermDefault, GpioLockDefault} },<br>+ // PCIE_CLKREQ3_N (GPIO_44)<br>+ {NORTH_ALL_PCIE_CLKREQ3_N,<br>+ {GpioPadModeNative1, GpioHostOwnGpio, GpioDirIn, GpioOutDefault,<br>+ GpioIntDefault, GpioResetDefault, GpioTermDefault, GpioLockDefault} },<br>+ // FORCE_POWER (GPIO_45)<br>+ {NORTH_ALL_PCIE_CLKREQ4_N,<br>+ {GpioPadModeGpio, GpioHostOwnGpio, GpioDirOut, GpioOutDefault,<br>+ GpioIntDefault, GpioResetDefault, GpioTermDefault, GpioLockDefault} },<br>+ // GBE_MDC (GPIO_1)<br>+ {NORTH_ALL_GPIO_1,<br>+ {GpioPadModeNative1, GpioHostOwnGpio, GpioDirOut, GpioOutDefault,<br>+ GpioIntDefault, GpioResetDefault, GpioTermDefault, GpioLockDefault} },<br>+ // GBE_MDIO (GPIO_2)<br>+ {NORTH_ALL_GPIO_2,<br>+ {GpioPadModeNative1, GpioHostOwnGpio, GpioDirInOut, GpioOutDefault,<br>+ GpioIntDefault, GpioResetDefault, GpioTermDefault, GpioLockDefault} },<br>+ // SVID_ALERT_N (GPIO_47)<br>+ {NORTH_ALL_SVID_ALERT_N,<br>+ {GpioPadModeNative1, GpioHostOwnGpio, GpioDirIn, GpioOutDefault,<br>+ GpioIntDefault, GpioResetDefault, GpioTermDefault, GpioLockDefault} },<br>+ // SVID_DATA (GPIO_48)<br>+ {NORTH_ALL_SVID_DATA,<br>+ {GpioPadModeNative1, GpioHostOwnGpio, GpioDirInOut, GpioOutDefault,<br>+ GpioIntDefault, GpioResetDefault, GpioTermDefault, GpioLockDefault} },<br>+ // SVID_CLK (GPIO_49)<br>+ {NORTH_ALL_SVID_CLK,<br>+ {GpioPadModeNative1, GpioHostOwnGpio, GpioDirOut, GpioOutDefault,<br>+ GpioIntDefault, GpioResetDefault, GpioTermDefault, GpioLockDefault} },<br>+ // THERMTRIP_N (GPIO_50)<br>+ {NORTH_ALL_THERMTRIP_N,<br>+ {GpioPadModeNative1, GpioHostOwnGpio, GpioDirOut, GpioOutDefault,<br>+ GpioIntDefault, GpioResetDefault, GpioTermDefault, GpioLockDefault} },<br>+ // PROCHOT_N (GPIO_51)<br>+ {NORTH_ALL_PROCHOT_N,<br>+ {GpioPadModeNative1, GpioHostOwnGpio, GpioDirIn, GpioOutDefault,<br>+ GpioIntDefault, GpioResetDefault, GpioTermDefault, GpioLockDefault} },<br>+ // MEMHOT_N (GPIO_52)<br>+ {NORTH_ALL_MEMHOT_N,<br>+ {GpioPadModeNative1, GpioHostOwnGpio, GpioDirIn, GpioOutDefault,<br>+ GpioIntDefault, GpioResetDefault, GpioTermDefault, GpioLockDefault} },<br>+ // DFX_PORT_CLK0 (GPIO_53)<br>+ {SOUTH_DFX_DFX_PORT_CLK0,<br>+ {GpioPadModeNative1, GpioHostOwnGpio, GpioDirOut, GpioOutDefault,<br>+ GpioIntDefault, GpioResetDefault, GpioTermDefault, GpioLockDefault} },<br>+ // DFX_PORT_CLK1 (GPIO_54)<br>+ {SOUTH_DFX_DFX_PORT_CLK1,<br>+ {GpioPadModeNative1, GpioHostOwnGpio, GpioDirOut, GpioOutDefault,<br>+ GpioIntDefault, GpioResetDefault, GpioTermDefault, GpioLockDefault} },<br>+ // DFX_PORT0 (GPIO_55)<br>+ {SOUTH_DFX_DFX_PORT0,<br>+ {GpioPadModeNative1, GpioHostOwnGpio, GpioDirInOut, GpioOutDefault,<br>+ GpioIntDefault, GpioResetDefault, GpioTermDefault, GpioLockDefault} },<br>+ // DFX_PORT1 (GPIO_56)<br>+ {SOUTH_DFX_DFX_PORT1,<br>+ {GpioPadModeNative1, GpioHostOwnGpio, GpioDirInOut, GpioOutDefault,<br>+ GpioIntDefault, GpioResetDefault, GpioTermDefault, GpioLockDefault} },<br>+ // DFX_PORT2 (GPIO_57)<br>+ {SOUTH_DFX_DFX_PORT2,<br>+ {GpioPadModeNative1, GpioHostOwnGpio, GpioDirInOut, GpioOutDefault,<br>+ GpioIntDefault, GpioResetDefault, GpioTermDefault, GpioLockDefault} },<br>+ // DFX_PORT3 (GPIO_58)<br>+ {SOUTH_DFX_DFX_PORT3,<br>+ {GpioPadModeNative1, GpioHostOwnGpio, GpioDirInOut, GpioOutDefault,<br>+ GpioIntDefault, GpioResetDefault, GpioTermDefault, GpioLockDefault} },<br>+ // DFX_PORT4 (GPIO_59)<br>+ {SOUTH_DFX_DFX_PORT4,<br>+ {GpioPadModeNative1, GpioHostOwnGpio, GpioDirInOut, GpioOutDefault,<br>+ GpioIntDefault, GpioResetDefault, GpioTermDefault, GpioLockDefault} },<br>+ // DFX_PORT5 (GPIO_60)<br>+ {SOUTH_DFX_DFX_PORT5,<br>+ {GpioPadModeNative1, GpioHostOwnGpio, GpioDirInOut, GpioOutDefault,<br>+ GpioIntDefault, GpioResetDefault, GpioTermDefault, GpioLockDefault} },<br>+ // DFX_PORT6 (GPIO_61)<br>+ {SOUTH_DFX_DFX_PORT6,<br>+ {GpioPadModeNative1, GpioHostOwnGpio, GpioDirInOut, GpioOutDefault,<br>+ GpioIntDefault, GpioResetDefault, GpioTermDefault, GpioLockDefault} },<br>+ // DFX_PORT7 (GPIO_62)<br>+ {SOUTH_DFX_DFX_PORT7,<br>+ {GpioPadModeNative1, GpioHostOwnGpio, GpioDirInOut, GpioOutDefault,<br>+ GpioIntDefault, GpioResetDefault, GpioTermDefault, GpioLockDefault} },<br>+ // DFX_PORT8 (GPIO_63)<br>+ {SOUTH_DFX_DFX_PORT8,<br>+ {GpioPadModeNative1, GpioHostOwnGpio, GpioDirInOut, GpioOutDefault,<br>+ GpioIntDefault, GpioResetDefault, GpioTermDefault, GpioLockDefault} },<br>+ // DFX_PORT9 (GPIO_134)<br>+ {SOUTH_DFX_DFX_PORT9,<br>+ {GpioPadModeNative1, GpioHostOwnGpio, GpioDirInOut, GpioOutDefault,<br>+ GpioIntDefault, GpioResetDefault, GpioTermDefault, GpioLockDefault} },<br>+ // DFX_PORT10 (GPIO_135)<br>+ {SOUTH_DFX_DFX_PORT10,<br>+ {GpioPadModeNative1, GpioHostOwnGpio, GpioDirInOut, GpioOutDefault,<br>+ GpioIntDefault, GpioResetDefault, GpioTermDefault, GpioLockDefault} },<br>+ // DFX_PORT11 (GPIO_136)<br>+ {SOUTH_DFX_DFX_PORT11,<br>+ {GpioPadModeNative1, GpioHostOwnGpio, GpioDirInOut, GpioOutDefault,<br>+ GpioIntDefault, GpioResetDefault, GpioTermDefault, GpioLockDefault} },<br>+ // DFX_PORT12 (GPIO_137)<br>+ {SOUTH_DFX_DFX_PORT12,<br>+ {GpioPadModeNative1, GpioHostOwnGpio, GpioDirInOut, GpioOutDefault,<br>+ GpioIntDefault, GpioResetDefault, GpioTermDefault, GpioLockDefault} },<br>+ // DFX_PORT13 (GPIO_138)<br>+ {SOUTH_DFX_DFX_PORT13,<br>+ {GpioPadModeNative1, GpioHostOwnGpio, GpioDirInOut, GpioOutDefault,<br>+ GpioIntDefault, GpioResetDefault, GpioTermDefault, GpioLockDefault} },<br>+ // DFX_PORT14 (GPIO_139)<br>+ {SOUTH_DFX_DFX_PORT14,<br>+ {GpioPadModeNative1, GpioHostOwnGpio, GpioDirInOut, GpioOutDefault,<br>+ GpioIntDefault, GpioResetDefault, GpioTermDefault, GpioLockDefault} },<br>+ // DFX_PORT15 (GPIO_140)<br>+ {SOUTH_DFX_DFX_PORT15,<br>+ {GpioPadModeNative1, GpioHostOwnGpio, GpioDirInOut, GpioOutDefault,<br>+ GpioIntDefault, GpioResetDefault, GpioTermDefault, GpioLockDefault} },<br>+ // SPI_TPM_CS_N (GPIO_12)<br>+ {SOUTH_GROUP0_GPIO_12,<br>+ {GpioPadModeNative1, GpioHostOwnGpio, GpioDirOut, GpioOutDefault,<br>+ GpioIntDefault, GpioResetDefault, GpioTermDefault, GpioLockDefault} },<br>+ // SMB5_GBE_ALRT_N (GPIO_13)<br>+ {SOUTH_GROUP0_SMB5_GBE_ALRT_N,<br>+ {GpioPadModeNative3, GpioHostOwnGpio, GpioDirIn, GpioOutDefault,<br>+ GpioIntDefault, GpioResetPwrGood, GpioTermDefault, GpioLockDefault} },<br>+ // SMI (GPIO_98)<br>+ {SOUTH_GROUP0_PCIE_CLKREQ5_N,<br>+ {GpioPadModeGpio, GpioHostOwnGpio, GpioDirIn, GpioOutDefault,<br>+ GpioIntSmi, GpioResetDefault, GpioTermDefault, GpioLockDefault} },<br>+ // NMI (GPIO_99)<br>+ {SOUTH_GROUP0_PCIE_CLKREQ6_N,<br>+ {GpioPadModeGpio, GpioHostOwnGpio, GpioDirIn, GpioOutDefault,<br>+ GpioIntNmi, GpioResetDefault, GpioTermDefault, GpioLockDefault} },<br>+ // GBE3_LED0 (GPIO_100)<br>+ {SOUTH_GROUP0_PCIE_CLKREQ7_N,<br>+ {GpioPadModeNative3, GpioHostOwnGpio, GpioDirOut, GpioOutDefault,<br>+ GpioIntDefault, GpioResetDefault, GpioTermDefault, GpioLockDefault} },<br>+ // UART0_RXD (GPIO_101)<br>+ {SOUTH_GROUP0_UART0_RXD,<br>+ {GpioPadModeNative1, GpioHostOwnGpio, GpioDirIn, GpioOutDefault,<br>+ GpioIntDefault, GpioResetDefault, GpioTermDefault, GpioLockDefault} },<br>+ // UART0_TXD (GPIO_102)<br>+ {SOUTH_GROUP0_UART0_TXD,<br>+ {GpioPadModeNative1, GpioHostOwnGpio, GpioDirOut, GpioOutDefault,<br>+ GpioIntDefault, GpioResetDefault, GpioTermDefault, GpioLockDefault} },<br>+ // SMB5_GBE_CLK (GPIO_103)<br>+ {SOUTH_GROUP0_SMB5_GBE_CLK,<br>+ {GpioPadModeNative3, GpioHostOwnGpio, GpioDirOut, GpioOutDefault,<br>+ GpioIntDefault, GpioResetPwrGood, GpioTermDefault, GpioLockDefault} },<br>+ // SMB_GBE_DATA (GPIO_104)<br>+ {SOUTH_GROUP0_SMB5_GBE_DATA,<br>+ {GpioPadModeNative3, GpioHostOwnGpio, GpioDirInOut, GpioOutDefault,<br>+ GpioIntDefault, GpioResetPwrGood, GpioTermDefault, GpioLockDefault} },<br>+ // ERROR2_N (GPIO_105)<br>+ {SOUTH_GROUP0_ERROR2_N,<br>+ {GpioPadModeNative1, GpioHostOwnGpio, GpioDirOut, GpioOutDefault,<br>+ GpioIntDefault, GpioResetDefault, GpioTermDefault, GpioLockDefault} },<br>+ // ERROR1_N (GPIO_106)<br>+ {SOUTH_GROUP0_ERROR1_N,<br>+ {GpioPadModeNative1, GpioHostOwnGpio, GpioDirOut, GpioOutDefault,<br>+ GpioIntDefault, GpioResetDefault, GpioTermDefault, GpioLockDefault} },<br>+ // ERROR0_N (GPIO_107)<br>+ {SOUTH_GROUP0_ERROR0_N,<br>+ {GpioPadModeNative1, GpioHostOwnGpio, GpioDirOut, GpioOutDefault,<br>+ GpioIntDefault, GpioResetDefault, GpioTermDefault, GpioLockDefault} },<br>+ // IERR_N (CATERR_N) (GPIO_108)<br>+ {SOUTH_GROUP0_IERR_N,<br>+ {GpioPadModeNative1, GpioHostOwnGpio, GpioDirOut, GpioOutDefault,<br>+ GpioIntDefault, GpioResetDefault, GpioTermDefault, GpioLockDefault} },<br>+ // MCERR_N (GPIO_109)<br>+ {SOUTH_GROUP0_MCERR_N,<br>+ {GpioPadModeNative1, GpioHostOwnGpio, GpioDirOut, GpioOutDefault,<br>+ GpioIntDefault, GpioResetDefault, GpioTermDefault, GpioLockDefault} },<br>+ // SMB0_LEG_CLK (GPIO_110)<br>+ {SOUTH_GROUP0_SMB0_LEG_CLK,<br>+ {GpioPadModeNative1, GpioHostOwnGpio, GpioDirOut, GpioOutDefault,<br>+ GpioIntDefault, GpioResetDefault, GpioTermDefault, GpioLockDefault} },<br>+ // SMB0_LEG_DATA (GPIO_111)<br>+ {SOUTH_GROUP0_SMB0_LEG_DATA,<br>+ {GpioPadModeNative1, GpioHostOwnGpio, GpioDirInOut, GpioOutDefault,<br>+ GpioIntDefault, GpioResetDefault, GpioTermDefault, GpioLockDefault} },<br>+ // SMB0_LEG_ALRT_N (GPIO_112)<br>+ {SOUTH_GROUP0_SMB0_LEG_ALRT_N,<br>+ {GpioPadModeNative1, GpioHostOwnGpio, GpioDirIn, GpioOutDefault,<br>+ GpioIntDefault, GpioResetDefault, GpioTermDefault, GpioLockDefault} },<br>+ // SMB1_HOST_DATA (GPIO_113)<br>+ {SOUTH_GROUP0_SMB1_HOST_DATA,<br>+ {GpioPadModeNative1, GpioHostOwnGpio, GpioDirInOut, GpioOutDefault,<br>+ GpioIntDefault, GpioResetDefault, GpioTermDefault, GpioLockDefault} },<br>+ // SMB1_HOST_CLK (GPIO_114)<br>+ {SOUTH_GROUP0_SMB1_HOST_CLK,<br>+ {GpioPadModeNative1, GpioHostOwnGpio, GpioDirOut, GpioOutDefault,<br>+ GpioIntDefault, GpioResetDefault, GpioTermDefault, GpioLockDefault} },<br>+ // SMB2_PECI_DATA (GPIO_115)<br>+ {SOUTH_GROUP0_SMB2_PECI_DATA,<br>+ {GpioPadModeNative1, GpioHostOwnGpio, GpioDirInOut, GpioOutDefault,<br>+ GpioIntDefault, GpioResetDefault, GpioTermDefault, GpioLockDefault} },<br>+ // SMB2_PECI_CLK (GPIO_116)<br>+ {SOUTH_GROUP0_SMB2_PECI_CLK,<br>+ {GpioPadModeNative1, GpioHostOwnGpio, GpioDirOut, GpioOutDefault,<br>+ GpioIntDefault, GpioResetDefault, GpioTermDefault, GpioLockDefault} },<br>+ // SMB4_CSME0_DATA (GPIO_117)<br>+ {SOUTH_GROUP0_SMB4_CSME0_DATA,<br>+ {GpioPadModeNative1, GpioHostOwnGpio, GpioDirInOut, GpioOutDefault,<br>+ GpioIntDefault, GpioResetDefault, GpioTermDefault, GpioLockDefault} },<br>+ // SMB4_CSME0_CLK (GPIO_118)<br>+ {SOUTH_GROUP0_SMB4_CSME0_CLK,<br>+ {GpioPadModeNative1, GpioHostOwnGpio, GpioDirOut, GpioOutDefault,<br>+ GpioIntDefault, GpioResetDefault, GpioTermDefault, GpioLockDefault} },<br>+ // SMB4_CSME0_ALRT_N (GPIO_119)<br>+ {SOUTH_GROUP0_SMB4_CSME0_ALRT_N,<br>+ {GpioPadModeNative1, GpioHostOwnGpio, GpioDirIn, GpioOutDefault,<br>+ GpioIntDefault, GpioResetDefault, GpioTermDefault, GpioLockDefault} },<br>+ // USB_OC0_N (GPIO_120)<br>+ {SOUTH_GROUP0_USB_OC0_N,<br>+ {GpioPadModeNative1, GpioHostOwnGpio, GpioDirIn, GpioOutDefault,<br>+ GpioIntDefault, GpioResetDefault, GpioTermDefault, GpioLockDefault} },<br>+ // FLEX_CLK_SE0 (GPIO_121)<br>+ {SOUTH_GROUP0_FLEX_CLK_SE0,<br>+ {GpioPadModeNative1, GpioHostOwnGpio, GpioDirOut, GpioOutDefault,<br>+ GpioIntDefault, GpioResetDefault, GpioTermDefault, GpioLockDefault} },<br>+ // FLEX_CLK_SE1 (GPIO_122)<br>+ {SOUTH_GROUP0_FLEX_CLK_SE1,<br>+ {GpioPadModeNative1, GpioHostOwnGpio, GpioDirOut, GpioOutDefault,<br>+ GpioIntDefault, GpioResetDefault, GpioTermDefault, GpioLockDefault} },<br>+ // GBE3_LED1 (GPIO_4)<br>+ {SOUTH_GROUP0_GPIO_4,<br>+ {GpioPadModeNative3, GpioHostOwnGpio, GpioDirOut, GpioOutDefault,<br>+ GpioIntDefault, GpioResetDefault, GpioTermDefault, GpioLockDefault} },<br>+ // SMB3_IE0_CLK (GPIO_5)<br>+ {SOUTH_GROUP0_GPIO_5,<br>+ {GpioPadModeNative1, GpioHostOwnGpio, GpioDirOut, GpioOutDefault,<br>+ GpioIntDefault, GpioResetDefault, GpioTermDefault, GpioLockDefault} },<br>+ // SMB3_IE0_DATA (GPIO_6)<br>+ {SOUTH_GROUP0_GPIO_6,<br>+ {GpioPadModeNative1, GpioHostOwnGpio, GpioDirInOut, GpioOutDefault,<br>+ GpioIntDefault, GpioResetDefault, GpioTermDefault, GpioLockDefault} },<br>+ // SMB3_IE0_ALERT_N (GPIO_7)<br>+ {SOUTH_GROUP0_GPIO_7,<br>+ {GpioPadModeNative1, GpioHostOwnGpio, GpioDirIn, GpioOutDefault,<br>+ GpioIntDefault, GpioResetDefault, GpioTermDefault, GpioLockDefault} },<br>+ // SATA0_LED (GPIO_90)<br>+ {SOUTH_GROUP0_SATA0_LED_N,<br>+ {GpioPadModeNative1, GpioHostOwnGpio, GpioDirOut, GpioOutDefault,<br>+ GpioIntDefault, GpioResetDefault, GpioTermDefault, GpioLockDefault} },<br>+ // SATA1_LED (GPIO_91)<br>+ {SOUTH_GROUP0_SATA1_LED_N,<br>+ {GpioPadModeNative1, GpioHostOwnGpio, GpioDirOut, GpioOutDefault,<br>+ GpioIntDefault, GpioResetDefault, GpioTermDefault, GpioLockDefault} },<br>+ // SATA_PDETECT0 (GPIO_92)<br>+ {SOUTH_GROUP0_SATA_PDETECT0,<br>+ {GpioPadModeNative1, GpioHostOwnGpio, GpioDirIn, GpioOutDefault,<br>+ GpioIntDefault, GpioResetDefault, GpioTermDefault, GpioLockDefault} },<br>+ // SATA_PDETECT1 (GPIO_93)<br>+ {SOUTH_GROUP0_SATA_PDETECT1,<br>+ {GpioPadModeNative1, GpioHostOwnGpio, GpioDirIn, GpioOutDefault,<br>+ GpioIntDefault, GpioResetDefault, GpioTermDefault, GpioLockDefault} },<br>+ // UART1_RTS (GPIO_94)<br>+ {SOUTH_GROUP0_SATA0_SDOUT,<br>+ {GpioPadModeNative1, GpioHostOwnGpio, GpioDirOut, GpioOutDefault,<br>+ GpioIntDefault, GpioResetDefault, GpioTermDefault, GpioLockDefault} },<br>+ // UART1_CTS (GPIO_95)<br>+ {SOUTH_GROUP0_SATA1_SDOUT,<br>+ {GpioPadModeNative1, GpioHostOwnGpio, GpioDirIn, GpioOutDefault,<br>+ GpioIntDefault, GpioResetDefault, GpioTermDefault, GpioLockDefault} },<br>+ // UART1_RXD (GPIO_96)<br>+ {SOUTH_GROUP0_UART1_RXD,<br>+ {GpioPadModeNative1, GpioHostOwnGpio, GpioDirIn, GpioOutDefault,<br>+ GpioIntDefault, GpioResetDefault, GpioTermDefault, GpioLockDefault} },<br>+ // UART1_TXD (GPIO_97)<br>+ {SOUTH_GROUP0_UART1_TXD,<br>+ {GpioPadModeNative1, GpioHostOwnGpio, GpioDirOut, GpioOutDefault,<br>+ GpioIntDefault, GpioResetDefault, GpioTermDefault, GpioLockDefault} },<br>+ // SMB6_CSME1_DATA (GPIO_8)<br>+ {SOUTH_GROUP0_GPIO_8,<br>+ {GpioPadModeNative3, GpioHostOwnGpio, GpioDirInOut, GpioOutDefault,<br>+ GpioIntDefault, GpioResetDefault, GpioTermDefault, GpioLockDefault} },<br>+ // SMB6_CSME1_CLK (GPIO_9)<br>+ {SOUTH_GROUP0_GPIO_9,<br>+ {GpioPadModeNative3, GpioHostOwnGpio, GpioDirOut, GpioOutDefault,<br>+ GpioIntDefault, GpioResetDefault, GpioTermDefault, GpioLockDefault} },<br>+ // TCK (GPIO_141)<br>+ {SOUTH_GROUP0_TCK,<br>+ {GpioPadModeNative1, GpioHostOwnGpio, GpioDirIn, GpioOutDefault,<br>+ GpioIntDefault, GpioResetDefault, GpioTermDefault, GpioLockDefault} },<br>+ // TRST_N (GPIO_142)<br>+ {SOUTH_GROUP0_TRST_N,<br>+ {GpioPadModeNative1, GpioHostOwnGpio, GpioDirIn, GpioOutDefault,<br>+ GpioIntDefault, GpioResetDefault, GpioTermDefault, GpioLockDefault} },<br>+ // TMS (GPIO_143)<br>+ {SOUTH_GROUP0_TMS,<br>+ {GpioPadModeNative1, GpioHostOwnGpio, GpioDirIn, GpioOutDefault,<br>+ GpioIntDefault, GpioResetDefault, GpioTermDefault, GpioLockDefault} },<br>+ // TDI (GPIO_144)<br>+ {SOUTH_GROUP0_TDI,<br>+ {GpioPadModeNative1, GpioHostOwnGpio, GpioDirIn, GpioOutDefault,<br>+ GpioIntDefault, GpioResetDefault, GpioTermDefault, GpioLockDefault} },<br>+ // TDO (GPIO_145)<br>+ {SOUTH_GROUP0_TDO,<br>+ {GpioPadModeNative1, GpioHostOwnGpio, GpioDirOut, GpioOutDefault,<br>+ GpioIntDefault, GpioResetDefault, GpioTermDefault, GpioLockDefault} },<br>+ // CX_PRDY_N (GPIO_146)<br>+ {SOUTH_GROUP0_CX_PRDY_N,<br>+ {GpioPadModeNative1, GpioHostOwnGpio, GpioDirOut, GpioOutDefault,<br>+ GpioIntDefault, GpioResetDefault, GpioTermDefault, GpioLockDefault} },<br>+ // CX-PREQ_N (GPIO_147)<br>+ {SOUTH_GROUP0_CX_PREQ_N,<br>+ {GpioPadModeNative1, GpioHostOwnGpio, GpioDirIn, GpioOutDefault,<br>+ GpioIntDefault, GpioResetDefault, GpioTermDefault, GpioLockDefault} },<br>+ // ME_RECVR_HDR (GPIO_148)<br>+ {SOUTH_GROUP0_CTBTRIGINOUT,<br>+ {GpioPadModeGpio, GpioHostOwnGpio, GpioDirIn, GpioOutDefault,<br>+ GpioIntDefault, GpioResetDefault, GpioTermDefault, GpioLockDefault} },<br>+ // ADV_DBG_DFX_HDR (GPIO_149)<br>+ {SOUTH_GROUP0_CTBTRIGOUT,<br>+ {GpioPadModeGpio, GpioHostOwnGpio, GpioDirIn, GpioOutDefault,<br>+ GpioIntDefault, GpioResetDefault, GpioTermDefault, GpioLockDefault} },<br>+ // LAD2_SPI_IRQ_N (GPIO_150)<br>+ {SOUTH_GROUP0_DFX_SPARE2,<br>+ {GpioPadModeGpio, GpioHostOwnGpio, GpioDirInOut, GpioOutDefault,<br>+ GpioIntDefault, GpioResetDefault, GpioTermDefault, GpioLockDefault} },<br>+ // SMB_PECI_ALRT_N (GPIO_151)<br>+ {SOUTH_GROUP0_DFX_SPARE3,<br>+ {GpioPadModeGpio, GpioHostOwnGpio, GpioDirIn, GpioOutDefault,<br>+ GpioIntDefault, GpioResetDefault, GpioTermDefault, GpioLockDefault} },<br>+ // SMB_CSME1_ALRT_N (GPIO_152)<br>+ {SOUTH_GROUP0_DFX_SPARE4,<br>+ {GpioPadModeGpio, GpioHostOwnGpio, GpioDirIn, GpioOutDefault,<br>+ GpioIntDefault, GpioResetDefault, GpioTermDefault, GpioLockDefault} },<br>+ // SUSPWRDNACK (GPIO_79)<br>+ {SOUTH_GROUP1_SUSPWRDNACK,<br>+ {GpioPadModeNative1, GpioHostOwnGpio, GpioDirOut, GpioOutDefault,<br>+ GpioIntDefault, GpioResetDefault, GpioTermDefault, GpioLockDefault} },<br>+ // PMU_SUSCLK (GPIO_80)<br>+ {SOUTH_GROUP1_PMU_SUSCLK,<br>+ {GpioPadModeNative1, GpioHostOwnGpio, GpioDirOut, GpioOutDefault,<br>+ GpioIntDefault, GpioResetDefault, GpioTermDefault, GpioLockDefault} },<br>+ // ADR_TRIGGER_N (GPIO_81)<br>+ {SOUTH_GROUP1_ADR_TRIGGER,<br>+ {GpioPadModeNative1, GpioHostOwnGpio, GpioDirIn, GpioOutDefault,<br>+ GpioIntDefault, GpioResetDefault, GpioTermDefault, GpioLockDefault} },<br>+ // PMU_SLP_S45_N (GPIO_82)<br>+ {SOUTH_GROUP1_PMU_SLP_S45_N,<br>+ {GpioPadModeNative1, GpioHostOwnGpio, GpioDirOut, GpioOutDefault,<br>+ GpioIntDefault, GpioResetDefault, GpioTermDefault, GpioLockDefault} },<br>+ // PMU_SLP_S3_N (GPIO_83)<br>+ {SOUTH_GROUP1_PMU_SLP_S3_N,<br>+ {GpioPadModeNative1, GpioHostOwnGpio, GpioDirOut, GpioOutDefault,<br>+ GpioIntDefault, GpioResetDefault, GpioTermDefault, GpioLockDefault} },<br>+ // PMU_WAKE_N (GPIO_84)<br>+ {SOUTH_GROUP1_PMU_WAKE_N,<br>+ {GpioPadModeNative1, GpioHostOwnGpio, GpioDirIn, GpioOutDefault,<br>+ GpioIntDefault, GpioResetDefault, GpioTermDefault, GpioLockDefault} },<br>+ // PMU_PWRBTN_N (GPIO_85)<br>+ {SOUTH_GROUP1_PMU_PWRBTN_N,<br>+ {GpioPadModeNative1, GpioHostOwnGpio, GpioDirIn, GpioOutDefault,<br>+ GpioIntDefault, GpioResetDefault, GpioTermDefault, GpioLockDefault} },<br>+ // PMU_RESETBUTTON_N (GPIO_86)<br>+ {SOUTH_GROUP1_PMU_RESETBUTTON_N,<br>+ {GpioPadModeNative1, GpioHostOwnGpio, GpioDirIn, GpioOutDefault,<br>+ GpioIntDefault, GpioResetDefault, GpioTermDefault, GpioLockDefault} },<br>+ // PMU_PLTRST_N (GPIO_87)<br>+ {SOUTH_GROUP1_PMU_PLTRST_N,<br>+ {GpioPadModeNative1, GpioHostOwnGpio, GpioDirOut, GpioOutDefault,<br>+ GpioIntDefault, GpioResetDefault, GpioTermDefault, GpioLockDefault} },<br>+ // PMU_SUS_STAT_N (GPIO_88)<br>+ {SOUTH_GROUP1_SUS_STAT_N,<br>+ {GpioPadModeNative1, GpioHostOwnGpio, GpioDirOut, GpioOutDefault,<br>+ GpioIntDefault, GpioResetDefault, GpioTermDefault, GpioLockDefault} },<br>+ // TDB_CIO_PLUG_EVENT (GPIO_89)<br>+ {SOUTH_GROUP1_SLP_S0IX_N,<br>+ {GpioPadModeGpio, GpioHostOwnGpio, GpioDirIn, GpioOutDefault,<br>+ GpioIntDefault, GpioResetDefault, GpioTermDefault, GpioLockDefault} },<br>+ // SPI_CS0_N (GPIO_72)<br>+ {SOUTH_GROUP1_SPI_CS0_N,<br>+ {GpioPadModeNative1, GpioHostOwnGpio, GpioDirOut, GpioOutDefault,<br>+ GpioIntDefault, GpioResetDefault, GpioTermDefault, GpioLockDefault} },<br>+ // SPI_CS1_N (GPIO_73)<br>+ {SOUTH_GROUP1_SPI_CS1_N,<br>+ {GpioPadModeNative1, GpioHostOwnGpio, GpioDirOut, GpioOutDefault,<br>+ GpioIntDefault, GpioResetDefault, GpioTermDefault, GpioLockDefault} },<br>+ // SPI_MOSI_IO0 (GPIO_74)<br>+ {SOUTH_GROUP1_SPI_MOSI_IO0,<br>+ {GpioPadModeNative1, GpioHostOwnGpio, GpioDirInOut, GpioOutDefault,<br>+ GpioIntDefault, GpioResetDefault, GpioTermDefault, GpioLockDefault} },<br>+ // SPI_MISO_IO1 (GPIO_75)<br>+ {SOUTH_GROUP1_SPI_MISO_IO1,<br>+ {GpioPadModeNative1, GpioHostOwnGpio, GpioDirInOut, GpioOutDefault,<br>+ GpioIntDefault, GpioResetDefault, GpioTermDefault, GpioLockDefault} },<br>+ // SPI_IO2 (GPIO_76)<br>+ {SOUTH_GROUP1_SPI_IO2,<br>+ {GpioPadModeNative1, GpioHostOwnGpio, GpioDirOut, GpioOutDefault,<br>+ GpioIntDefault, GpioResetDefault, GpioTermDefault, GpioLockDefault} },<br>+ // SPI_IO3 (GPIO_77)<br>+ {SOUTH_GROUP1_SPI_IO3,<br>+ {GpioPadModeNative1, GpioHostOwnGpio, GpioDirOut, GpioOutDefault,<br>+ GpioIntDefault, GpioResetDefault, GpioTermDefault, GpioLockDefault} },<br>+ // SPI_CLK (GPIO_78)<br>+ {SOUTH_GROUP1_SPI_CLK,<br>+ {GpioPadModeNative1, GpioHostOwnGpio, GpioDirOut, GpioOutDefault,<br>+ GpioIntDefault, GpioResetDefault, GpioTermDefault, GpioLockDefault} },<br>+ // LPC_AD0 (GPIO_64)<br>+ {SOUTH_GROUP1_ESPI_IO0,<br>+ {GpioPadModeNative2, GpioHostOwnGpio, GpioDirInOut, GpioOutDefault,<br>+ GpioIntDefault, GpioResetDefault, GpioTermDefault, GpioLockDefault} },<br>+ // LPC_AD1 (GPIO_65)<br>+ {SOUTH_GROUP1_ESPI_IO1,<br>+ {GpioPadModeNative2, GpioHostOwnGpio, GpioDirInOut, GpioOutDefault,<br>+ GpioIntDefault, GpioResetDefault, GpioTermDefault, GpioLockDefault} },<br>+ // LPC_AD2 (GPIO_66)<br>+ {SOUTH_GROUP1_ESPI_IO2,<br>+ {GpioPadModeNative2, GpioHostOwnGpio, GpioDirInOut, GpioOutDefault,<br>+ GpioIntDefault, GpioResetDefault, GpioTermDefault, GpioLockDefault} },<br>+ // LPC_AD3 (GPIO_67)<br>+ {SOUTH_GROUP1_ESPI_IO3,<br>+ {GpioPadModeNative2, GpioHostOwnGpio, GpioDirInOut, GpioOutDefault,<br>+ GpioIntDefault, GpioResetDefault, GpioTermDefault, GpioLockDefault} },<br>+ // LPC_FRAME_N (GPIO_68)<br>+ {SOUTH_GROUP1_ESPI_CS0_N,<br>+ {GpioPadModeNative2, GpioHostOwnGpio, GpioDirOut, GpioOutDefault,<br>+ GpioIntDefault, GpioResetDefault, GpioTermDefault, GpioLockDefault} },<br>+ // LPC_CLKOUT0 (GPIO_69)<br>+ {SOUTH_GROUP1_ESPI_CLK,<br>+ {GpioPadModeNative2, GpioHostOwnGpio, GpioDirOut, GpioOutDefault,<br>+ GpioIntDefault, GpioResetDefault, GpioTermDefault, GpioLockDefault} },<br>+ // LPC_CLKOUT1 (GPIO_70)<br>+ {SOUTH_GROUP1_ESPI_RST_N,<br>+ {GpioPadModeNative2, GpioHostOwnGpio, GpioDirOut, GpioOutDefault,<br>+ GpioIntDefault, GpioResetDefault, GpioTermDefault, GpioLockDefault} },<br>+ // LPC_CLKRUN_N (GPIO_71)<br>+ {SOUTH_GROUP1_ESPI_ALRT0_N,<br>+ {GpioPadModeNative2, GpioHostOwnGpio, GpioDirOut, GpioOutDefault,<br>+ GpioIntDefault, GpioResetDefault, GpioTermDefault, GpioLockDefault} },<br>+ // MFG_MODE_HDR (GPIO_10)<br>+ {SOUTH_GROUP1_GPIO_10,<br>+ {GpioPadModeGpio, GpioHostOwnGpio, GpioDirIn, GpioOutDefault,<br>+ GpioIntDefault, GpioResetDefault, GpioTermDefault, GpioLockDefault} },<br>+ // LPC_SERIRQ (GPIO_11)<br>+ {SOUTH_GROUP1_GPIO_11,<br>+ {GpioPadModeNative2, GpioHostOwnGpio, GpioDirInOut, GpioOutDefault,<br>+ GpioIntDefault, GpioResetDefault, GpioTermDefault, GpioLockDefault} },<br>+ // EMMC-CMD (GPIO_123)<br>+ {SOUTH_GROUP1_EMMC_CMD,<br>+ {GpioPadModeNative1, GpioHostOwnGpio, GpioDirOut, GpioOutDefault,<br>+ GpioIntDefault, GpioResetDefault, GpioTermWpu20K, GpioLockDefault} },<br>+ // EMMC-CSTROBE (GPIO_124)<br>+ {SOUTH_GROUP1_EMMC_STROBE,<br>+ {GpioPadModeNative1, GpioHostOwnGpio, GpioDirOut, GpioOutDefault,<br>+ GpioIntDefault, GpioResetDefault, GpioTermDefault, GpioLockDefault} },<br>+ // EMMC-CLK (GPIO_125)<br>+ {SOUTH_GROUP1_EMMC_CLK,<br>+ {GpioPadModeNative1, GpioHostOwnGpio, GpioDirOut, GpioOutDefault,<br>+ GpioIntDefault, GpioResetDefault, GpioTermWpd20K, GpioLockDefault} },<br>+ // EMMC-D0 (GPIO_126)<br>+ {SOUTH_GROUP1_EMMC_D0,<br>+ {GpioPadModeNative1, GpioHostOwnGpio, GpioDirInOut, GpioOutDefault,<br>+ GpioIntDefault, GpioResetDefault, GpioTermWpu20K, GpioLockDefault} },<br>+ // EMMC-D1 (GPIO_127)<br>+ {SOUTH_GROUP1_EMMC_D1,<br>+ {GpioPadModeNative1, GpioHostOwnGpio, GpioDirInOut, GpioOutDefault,<br>+ GpioIntDefault, GpioResetDefault, GpioTermWpu20K, GpioLockDefault} },<br>+ // EMMC-D2 (GPIO_128)<br>+ {SOUTH_GROUP1_EMMC_D2,<br>+ {GpioPadModeNative1, GpioHostOwnGpio, GpioDirInOut, GpioOutDefault,<br>+ GpioIntDefault, GpioResetDefault, GpioTermWpu20K, GpioLockDefault} },<br>+ // EMMC-D3 (GPIO_129)<br>+ {SOUTH_GROUP1_EMMC_D3,<br>+ {GpioPadModeNative1, GpioHostOwnGpio, GpioDirInOut, GpioOutDefault,<br>+ GpioIntDefault, GpioResetDefault, GpioTermWpu20K, GpioLockDefault} },<br>+ // EMMC-D4 (GPIO_130)<br>+ {SOUTH_GROUP1_EMMC_D4,<br>+ {GpioPadModeNative1, GpioHostOwnGpio, GpioDirInOut, GpioOutDefault,<br>+ GpioIntDefault, GpioResetDefault, GpioTermWpu20K, GpioLockDefault} },<br>+ // EMMC-D5 (GPIO_131)<br>+ {SOUTH_GROUP1_EMMC_D5,<br>+ {GpioPadModeNative1, GpioHostOwnGpio, GpioDirInOut, GpioOutDefault,<br>+ GpioIntDefault, GpioResetDefault, GpioTermWpu20K, GpioLockDefault} },<br>+ // EMMC-D6 (GPIO_132)<br>+ {SOUTH_GROUP1_EMMC_D6,<br>+ {GpioPadModeNative1, GpioHostOwnGpio, GpioDirInOut, GpioOutDefault,<br>+ GpioIntDefault, GpioResetDefault, GpioTermWpu20K, GpioLockDefault} },<br>+ // EMMC-D7 (GPIO_133)<br>+ {SOUTH_GROUP1_EMMC_D7,<br>+ {GpioPadModeNative1, GpioHostOwnGpio, GpioDirInOut, GpioOutDefault,<br>+ GpioIntDefault, GpioResetDefault, GpioTermWpu20K, GpioLockDefault} },<br>+ // IE_ROM GPIO (GPIO_3)<br>+ {SOUTH_GROUP1_GPIO_3,<br>+ {GpioPadModeGpio, GpioHostOwnGpio, GpioDirOut, GpioOutDefault,<br>+ GpioIntDefault, GpioResetDefault, GpioTermDefault, GpioLockDefault} },<br>+};<br>+#endif<br>+<br>+#endif /* _MAINBOARD_GPIO_H */<br>diff --git a/src/mainboard/intel/harcuvar/harcuvar_boardid.h b/src/mainboard/intel/harcuvar/harcuvar_boardid.h<br>new file mode 100644<br>index 0000000..3bcd60c<br>--- /dev/null<br>+++ b/src/mainboard/intel/harcuvar/harcuvar_boardid.h<br>@@ -0,0 +1,26 @@<br>+/*<br>+ * This file is part of the coreboot project.<br>+ *<br>+ * Copyright (C) 2015 - 2017 Intel Corporation.<br>+ *<br>+ * This program is free software; you can redistribute it and/or modify<br>+ * it under the terms of the GNU General Public License as published by<br>+ * the Free Software Foundation; version 2 of the License.<br>+ *<br>+ * This program is distributed in the hope that it will be useful,<br>+ * but WITHOUT ANY WARRANTY; without even the implied warranty of<br>+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the<br>+ * GNU General Public License for more details.<br>+ *<br>+ */<br>+<br>+#ifndef HARCUVAR_MAINBOARD_BOARD_H<br>+#define HARCUVAR_MAINBOARD_BOARD_H<br>+<br>+#include <stdint.h><br>+<br>+#define BoardIdHarcuvar 0x52<br>+<br>+uint8_t board_id(void);<br>+<br>+#endif /* MAINBOARD_BOARD_H */<br>diff --git a/src/mainboard/intel/harcuvar/hsio.h b/src/mainboard/intel/harcuvar/hsio.h<br>new file mode 100644<br>index 0000000..ce059fd<br>--- /dev/null<br>+++ b/src/mainboard/intel/harcuvar/hsio.h<br>@@ -0,0 +1,624 @@<br>+/*<br>+ * This file is part of the coreboot project.<br>+ *<br>+ * Copyright (C) 2016-2017 Intel Corporation.<br>+ *<br>+ * This program is free software; you can redistribute it and/or modify<br>+ * it under the terms of the GNU General Public License as published by<br>+ * the Free Software Foundation; version 2 of the License.<br>+ *<br>+ * This program is distributed in the hope that it will be useful,<br>+ * but WITHOUT ANY WARRANTY; without even the implied warranty of<br>+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the<br>+ * GNU General Public License for more details.<br>+ *<br>+ */<br>+<br>+#ifndef _MAINBOARD_HSIO_H<br>+#define _MAINBOARD_HSIO_H<br>+<br>+#include <fsp/util.h><br>+<br>+#ifndef __ACPI__<br>+const BL_HSIO_INFORMATION harcuvar_hsio_config[] = {<br>+ /*<br>+ * Supported Lanes:<br>+ * 20<br>+ *<br>+ * Bifurcation:<br>+ * PCIE cluster #0: x8<br>+ * PCIE cluster #1: x4x4<br>+ *<br>+ * FIA MUX config:<br>+ * Lane[00:07]->x8 PCIE slot<br>+ * Lane[08:11]->a x4 PCIe slot<br>+ * Lane[12:15]->a 2nd x4 PCIe slot<br>+ * Lane[16]->a SATA connector with pin7 to 5V adapter capable<br>+ * Lane[17:18] -> 2 SATA connectors<br>+ * Lane[19]->USB3 rear I/O panel connector<br>+ */<br>+<br>+ /* SKU HSIO 20 (pcie [0-15] sata [16-18] usb [19]) */<br>+ {BL_SKU_HSIO_20,<br>+ {PCIE_BIF_CTRL_x8, PCIE_BIF_CTRL_x4x4},<br>+ {/* ME_FIA_MUX_CONFIG */<br>+ {BL_FIA_LANE_CONFIG(BL_ME_FIA_MUX_LANE_PCIE, BL_FIA_LANE00) |<br>+ BL_FIA_LANE_CONFIG(BL_ME_FIA_MUX_LANE_PCIE, BL_FIA_LANE01) |<br>+ BL_FIA_LANE_CONFIG(BL_ME_FIA_MUX_LANE_PCIE, BL_FIA_LANE02) |<br>+ BL_FIA_LANE_CONFIG(BL_ME_FIA_MUX_LANE_PCIE, BL_FIA_LANE03) |<br>+ BL_FIA_LANE_CONFIG(BL_ME_FIA_MUX_LANE_PCIE, BL_FIA_LANE04) |<br>+ BL_FIA_LANE_CONFIG(BL_ME_FIA_MUX_LANE_PCIE, BL_FIA_LANE05) |<br>+ BL_FIA_LANE_CONFIG(BL_ME_FIA_MUX_LANE_PCIE, BL_FIA_LANE06) |<br>+ BL_FIA_LANE_CONFIG(BL_ME_FIA_MUX_LANE_PCIE, BL_FIA_LANE07) |<br>+ BL_FIA_LANE_CONFIG(BL_ME_FIA_MUX_LANE_PCIE, BL_FIA_LANE08) |<br>+ BL_FIA_LANE_CONFIG(BL_ME_FIA_MUX_LANE_PCIE, BL_FIA_LANE09) |<br>+ BL_FIA_LANE_CONFIG(BL_ME_FIA_MUX_LANE_PCIE, BL_FIA_LANE10) |<br>+ BL_FIA_LANE_CONFIG(BL_ME_FIA_MUX_LANE_PCIE, BL_FIA_LANE11) |<br>+ BL_FIA_LANE_CONFIG(BL_ME_FIA_MUX_LANE_PCIE, BL_FIA_LANE12) |<br>+ BL_FIA_LANE_CONFIG(BL_ME_FIA_MUX_LANE_PCIE, BL_FIA_LANE13) |<br>+ BL_FIA_LANE_CONFIG(BL_ME_FIA_MUX_LANE_PCIE, BL_FIA_LANE14) |<br>+ BL_FIA_LANE_CONFIG(BL_ME_FIA_MUX_LANE_PCIE, BL_FIA_LANE15) |<br>+ BL_FIA_LANE_CONFIG(BL_ME_FIA_MUX_LANE_SATA, BL_FIA_LANE16) |<br>+ BL_FIA_LANE_CONFIG(BL_ME_FIA_MUX_LANE_SATA, BL_FIA_LANE17) |<br>+ BL_FIA_LANE_CONFIG(BL_ME_FIA_MUX_LANE_SATA, BL_FIA_LANE18) |<br>+ BL_FIA_LANE_CONFIG(BL_ME_FIA_MUX_LANE_XHCI, BL_FIA_LANE19)},<br>+<br>+ /* ME_FIA_SATA_CONFIG */<br>+ {BL_FIA_SATA_LANE_CONFIG(BL_ME_FIA_SATA_CONTROLLER_LANE_NOT_ASSIGNED,<br>+ BL_FIA_SATA_LANE04) |<br>+ BL_FIA_SATA_LANE_CONFIG(BL_ME_FIA_SATA_CONTROLLER_LANE_NOT_ASSIGNED,<br>+ BL_FIA_SATA_LANE05) |<br>+ BL_FIA_SATA_LANE_CONFIG(BL_ME_FIA_SATA_CONTROLLER_LANE_NOT_ASSIGNED,<br>+ BL_FIA_SATA_LANE06) |<br>+ BL_FIA_SATA_LANE_CONFIG(BL_ME_FIA_SATA_CONTROLLER_LANE_NOT_ASSIGNED,<br>+ BL_FIA_SATA_LANE07) |<br>+ BL_FIA_SATA_LANE_CONFIG(BL_ME_FIA_SATA_CONTROLLER_LANE_NOT_ASSIGNED,<br>+ BL_FIA_SATA_LANE08) |<br>+ BL_FIA_SATA_LANE_CONFIG(BL_ME_FIA_SATA_CONTROLLER_LANE_NOT_ASSIGNED,<br>+ BL_FIA_SATA_LANE09) |<br>+ BL_FIA_SATA_LANE_CONFIG(BL_ME_FIA_SATA_CONTROLLER_LANE_NOT_ASSIGNED,<br>+ BL_FIA_SATA_LANE10) |<br>+ BL_FIA_SATA_LANE_CONFIG(BL_ME_FIA_SATA_CONTROLLER_LANE_NOT_ASSIGNED,<br>+ BL_FIA_SATA_LANE11) |<br>+ BL_FIA_SATA_LANE_CONFIG(BL_ME_FIA_SATA_CONTROLLER_LANE_NOT_ASSIGNED,<br>+ BL_FIA_SATA_LANE12) |<br>+ BL_FIA_SATA_LANE_CONFIG(BL_ME_FIA_SATA_CONTROLLER_LANE_NOT_ASSIGNED,<br>+ BL_FIA_SATA_LANE13) |<br>+ BL_FIA_SATA_LANE_CONFIG(BL_ME_FIA_SATA_CONTROLLER_LANE_NOT_ASSIGNED,<br>+ BL_FIA_SATA_LANE14) |<br>+ BL_FIA_SATA_LANE_CONFIG(BL_ME_FIA_SATA_CONTROLLER_LANE_NOT_ASSIGNED,<br>+ BL_FIA_SATA_LANE15) |<br>+ BL_FIA_SATA_LANE_CONFIG(BL_ME_FIA_SATA_CONTROLLER_LANE_ASSIGNED,<br>+ BL_FIA_SATA_LANE16) |<br>+ BL_FIA_SATA_LANE_CONFIG(BL_ME_FIA_SATA_CONTROLLER_LANE_ASSIGNED,<br>+ BL_FIA_SATA_LANE17) |<br>+ BL_FIA_SATA_LANE_CONFIG(BL_ME_FIA_SATA_CONTROLLER_LANE_ASSIGNED,<br>+ BL_FIA_SATA_LANE18) |<br>+ BL_FIA_SATA_LANE_CONFIG(BL_ME_FIA_SATA_CONTROLLER_LANE_NOT_ASSIGNED,<br>+ BL_FIA_SATA_LANE19)},<br>+<br>+ /* ME_FIA_PCIE_ROOT_PORTS_CONFIG */<br>+ {BL_FIA_PCIE_ROOT_PORT_CONFIG(BL_ME_FIA_PCIE_ROOT_PORT_STATE,<br>+ BL_ME_FIA_PCIE_ROOT_PORT_ENABLED,<br>+ BL_FIA_PCIE_ROOT_PORT_0) |<br>+ BL_FIA_PCIE_ROOT_PORT_CONFIG(BL_ME_FIA_PCIE_ROOT_PORT_STATE,<br>+ BL_ME_FIA_PCIE_ROOT_PORT_DISABLED,<br>+ BL_FIA_PCIE_ROOT_PORT_1) |<br>+ BL_FIA_PCIE_ROOT_PORT_CONFIG(BL_ME_FIA_PCIE_ROOT_PORT_STATE,<br>+ BL_ME_FIA_PCIE_ROOT_PORT_DISABLED,<br>+ BL_FIA_PCIE_ROOT_PORT_2) |<br>+ BL_FIA_PCIE_ROOT_PORT_CONFIG(BL_ME_FIA_PCIE_ROOT_PORT_STATE,<br>+ BL_ME_FIA_PCIE_ROOT_PORT_DISABLED,<br>+ BL_FIA_PCIE_ROOT_PORT_3) |<br>+ BL_FIA_PCIE_ROOT_PORT_CONFIG(BL_ME_FIA_PCIE_ROOT_PORT_STATE,<br>+ BL_ME_FIA_PCIE_ROOT_PORT_ENABLED,<br>+ BL_FIA_PCIE_ROOT_PORT_4) |<br>+ BL_FIA_PCIE_ROOT_PORT_CONFIG(BL_ME_FIA_PCIE_ROOT_PORT_STATE,<br>+ BL_ME_FIA_PCIE_ROOT_PORT_DISABLED,<br>+ BL_FIA_PCIE_ROOT_PORT_5) |<br>+ BL_FIA_PCIE_ROOT_PORT_CONFIG(BL_ME_FIA_PCIE_ROOT_PORT_STATE,<br>+ BL_ME_FIA_PCIE_ROOT_PORT_ENABLED,<br>+ BL_FIA_PCIE_ROOT_PORT_6) |<br>+ BL_FIA_PCIE_ROOT_PORT_CONFIG(BL_ME_FIA_PCIE_ROOT_PORT_STATE,<br>+ BL_ME_FIA_PCIE_ROOT_PORT_DISABLED,<br>+ BL_FIA_PCIE_ROOT_PORT_7) |<br>+ BL_FIA_PCIE_ROOT_PORT_CONFIG(<br>+ BL_ME_FIA_PCIE_ROOT_PORT_LINK_WIDTH,<br>+ BL_ME_FIA_PCIE_ROOT_PORT_LINK_WIDTH_BICTRL,<br>+ BL_FIA_PCIE_ROOT_PORT_0) |<br>+ BL_FIA_PCIE_ROOT_PORT_CONFIG(<br>+ BL_ME_FIA_PCIE_ROOT_PORT_LINK_WIDTH,<br>+ BL_ME_FIA_PCIE_ROOT_PORT_LINK_WIDTH_BICTRL,<br>+ BL_FIA_PCIE_ROOT_PORT_1) |<br>+ BL_FIA_PCIE_ROOT_PORT_CONFIG(<br>+ BL_ME_FIA_PCIE_ROOT_PORT_LINK_WIDTH,<br>+ BL_ME_FIA_PCIE_ROOT_PORT_LINK_WIDTH_BICTRL,<br>+ BL_FIA_PCIE_ROOT_PORT_2) |<br>+ BL_FIA_PCIE_ROOT_PORT_CONFIG(<br>+ BL_ME_FIA_PCIE_ROOT_PORT_LINK_WIDTH,<br>+ BL_ME_FIA_PCIE_ROOT_PORT_LINK_WIDTH_BICTRL,<br>+ BL_FIA_PCIE_ROOT_PORT_3) |<br>+ BL_FIA_PCIE_ROOT_PORT_CONFIG(<br>+ BL_ME_FIA_PCIE_ROOT_PORT_LINK_WIDTH,<br>+ BL_ME_FIA_PCIE_ROOT_PORT_LINK_WIDTH_BICTRL,<br>+ BL_FIA_PCIE_ROOT_PORT_4) |<br>+ BL_FIA_PCIE_ROOT_PORT_CONFIG(<br>+ BL_ME_FIA_PCIE_ROOT_PORT_LINK_WIDTH,<br>+ BL_ME_FIA_PCIE_ROOT_PORT_LINK_WIDTH_BICTRL,<br>+ BL_FIA_PCIE_ROOT_PORT_5) |<br>+ BL_FIA_PCIE_ROOT_PORT_CONFIG(<br>+ BL_ME_FIA_PCIE_ROOT_PORT_LINK_WIDTH,<br>+ BL_ME_FIA_PCIE_ROOT_PORT_LINK_WIDTH_BICTRL,<br>+ BL_FIA_PCIE_ROOT_PORT_6) |<br>+ BL_FIA_PCIE_ROOT_PORT_CONFIG(<br>+ BL_ME_FIA_PCIE_ROOT_PORT_LINK_WIDTH,<br>+ BL_ME_FIA_PCIE_ROOT_PORT_LINK_WIDTH_BICTRL,<br>+ BL_FIA_PCIE_ROOT_PORT_7)} } },<br>+<br>+ /* SKU HSIO 12 (pcie [0-3, 8-9, 12-13] sata [16-18] usb [19]) */<br>+ {BL_SKU_HSIO_12,<br>+ {PCIE_BIF_CTRL_x4x4, PCIE_BIF_CTRL_x2x2x2x2},<br>+ {/*ME_FIA_MUX_CONFIG */<br>+ {BL_FIA_LANE_CONFIG(BL_ME_FIA_MUX_LANE_PCIE, BL_FIA_LANE00) |<br>+ BL_FIA_LANE_CONFIG(BL_ME_FIA_MUX_LANE_PCIE, BL_FIA_LANE01) |<br>+ BL_FIA_LANE_CONFIG(BL_ME_FIA_MUX_LANE_PCIE, BL_FIA_LANE02) |<br>+ BL_FIA_LANE_CONFIG(BL_ME_FIA_MUX_LANE_PCIE, BL_FIA_LANE03) |<br>+ BL_FIA_LANE_CONFIG(BL_ME_FIA_MUX_LANE_DISCONNECTED, BL_FIA_LANE04) |<br>+ BL_FIA_LANE_CONFIG(BL_ME_FIA_MUX_LANE_DISCONNECTED, BL_FIA_LANE05) |<br>+ BL_FIA_LANE_CONFIG(BL_ME_FIA_MUX_LANE_DISCONNECTED, BL_FIA_LANE06) |<br>+ BL_FIA_LANE_CONFIG(BL_ME_FIA_MUX_LANE_DISCONNECTED, BL_FIA_LANE07) |<br>+ BL_FIA_LANE_CONFIG(BL_ME_FIA_MUX_LANE_PCIE, BL_FIA_LANE08) |<br>+ BL_FIA_LANE_CONFIG(BL_ME_FIA_MUX_LANE_PCIE, BL_FIA_LANE09) |<br>+ BL_FIA_LANE_CONFIG(BL_ME_FIA_MUX_LANE_DISCONNECTED, BL_FIA_LANE10) |<br>+ BL_FIA_LANE_CONFIG(BL_ME_FIA_MUX_LANE_DISCONNECTED, BL_FIA_LANE11) |<br>+ BL_FIA_LANE_CONFIG(BL_ME_FIA_MUX_LANE_PCIE, BL_FIA_LANE12) |<br>+ BL_FIA_LANE_CONFIG(BL_ME_FIA_MUX_LANE_PCIE, BL_FIA_LANE13) |<br>+ BL_FIA_LANE_CONFIG(BL_ME_FIA_MUX_LANE_DISCONNECTED, BL_FIA_LANE14) |<br>+ BL_FIA_LANE_CONFIG(BL_ME_FIA_MUX_LANE_DISCONNECTED, BL_FIA_LANE15) |<br>+ BL_FIA_LANE_CONFIG(BL_ME_FIA_MUX_LANE_SATA, BL_FIA_LANE16) |<br>+ BL_FIA_LANE_CONFIG(BL_ME_FIA_MUX_LANE_SATA, BL_FIA_LANE17) |<br>+ BL_FIA_LANE_CONFIG(BL_ME_FIA_MUX_LANE_SATA, BL_FIA_LANE18) |<br>+ BL_FIA_LANE_CONFIG(BL_ME_FIA_MUX_LANE_XHCI, BL_FIA_LANE19)},<br>+<br>+ /* ME_FIA_SATA_CONFIG */<br>+ {BL_FIA_SATA_LANE_CONFIG(BL_ME_FIA_SATA_CONTROLLER_LANE_NOT_ASSIGNED,<br>+ BL_FIA_SATA_LANE04) |<br>+ BL_FIA_SATA_LANE_CONFIG(BL_ME_FIA_SATA_CONTROLLER_LANE_NOT_ASSIGNED,<br>+ BL_FIA_SATA_LANE05) |<br>+ BL_FIA_SATA_LANE_CONFIG(BL_ME_FIA_SATA_CONTROLLER_LANE_NOT_ASSIGNED,<br>+ BL_FIA_SATA_LANE06) |<br>+ BL_FIA_SATA_LANE_CONFIG(BL_ME_FIA_SATA_CONTROLLER_LANE_NOT_ASSIGNED,<br>+ BL_FIA_SATA_LANE07) |<br>+ BL_FIA_SATA_LANE_CONFIG(BL_ME_FIA_SATA_CONTROLLER_LANE_NOT_ASSIGNED,<br>+ BL_FIA_SATA_LANE08) |<br>+ BL_FIA_SATA_LANE_CONFIG(BL_ME_FIA_SATA_CONTROLLER_LANE_NOT_ASSIGNED,<br>+ BL_FIA_SATA_LANE09) |<br>+ BL_FIA_SATA_LANE_CONFIG(BL_ME_FIA_SATA_CONTROLLER_LANE_NOT_ASSIGNED,<br>+ BL_FIA_SATA_LANE10) |<br>+ BL_FIA_SATA_LANE_CONFIG(BL_ME_FIA_SATA_CONTROLLER_LANE_NOT_ASSIGNED,<br>+ BL_FIA_SATA_LANE11) |<br>+ BL_FIA_SATA_LANE_CONFIG(BL_ME_FIA_SATA_CONTROLLER_LANE_NOT_ASSIGNED,<br>+ BL_FIA_SATA_LANE12) |<br>+ BL_FIA_SATA_LANE_CONFIG(BL_ME_FIA_SATA_CONTROLLER_LANE_NOT_ASSIGNED,<br>+ BL_FIA_SATA_LANE13) |<br>+ BL_FIA_SATA_LANE_CONFIG(BL_ME_FIA_SATA_CONTROLLER_LANE_NOT_ASSIGNED,<br>+ BL_FIA_SATA_LANE14) |<br>+ BL_FIA_SATA_LANE_CONFIG(BL_ME_FIA_SATA_CONTROLLER_LANE_NOT_ASSIGNED,<br>+ BL_FIA_SATA_LANE15) |<br>+ BL_FIA_SATA_LANE_CONFIG(BL_ME_FIA_SATA_CONTROLLER_LANE_ASSIGNED,<br>+ BL_FIA_SATA_LANE16) |<br>+ BL_FIA_SATA_LANE_CONFIG(BL_ME_FIA_SATA_CONTROLLER_LANE_ASSIGNED,<br>+ BL_FIA_SATA_LANE17) |<br>+ BL_FIA_SATA_LANE_CONFIG(BL_ME_FIA_SATA_CONTROLLER_LANE_ASSIGNED,<br>+ BL_FIA_SATA_LANE18) |<br>+ BL_FIA_SATA_LANE_CONFIG(BL_ME_FIA_SATA_CONTROLLER_LANE_NOT_ASSIGNED,<br>+ BL_FIA_SATA_LANE19)},<br>+<br>+ /* ME_FIA_PCIE_ROOT_PORTS_CONFIG */<br>+ {BL_FIA_PCIE_ROOT_PORT_CONFIG(BL_ME_FIA_PCIE_ROOT_PORT_STATE,<br>+ BL_ME_FIA_PCIE_ROOT_PORT_ENABLED,<br>+ BL_FIA_PCIE_ROOT_PORT_0) |<br>+ BL_FIA_PCIE_ROOT_PORT_CONFIG(BL_ME_FIA_PCIE_ROOT_PORT_STATE,<br>+ BL_ME_FIA_PCIE_ROOT_PORT_DISABLED,<br>+ BL_FIA_PCIE_ROOT_PORT_1) |<br>+ BL_FIA_PCIE_ROOT_PORT_CONFIG(BL_ME_FIA_PCIE_ROOT_PORT_STATE,<br>+ BL_ME_FIA_PCIE_ROOT_PORT_DISABLED,<br>+ BL_FIA_PCIE_ROOT_PORT_2) |<br>+ BL_FIA_PCIE_ROOT_PORT_CONFIG(BL_ME_FIA_PCIE_ROOT_PORT_STATE,<br>+ BL_ME_FIA_PCIE_ROOT_PORT_DISABLED,<br>+ BL_FIA_PCIE_ROOT_PORT_3) |<br>+ BL_FIA_PCIE_ROOT_PORT_CONFIG(BL_ME_FIA_PCIE_ROOT_PORT_STATE,<br>+ BL_ME_FIA_PCIE_ROOT_PORT_ENABLED,<br>+ BL_FIA_PCIE_ROOT_PORT_4) |<br>+ BL_FIA_PCIE_ROOT_PORT_CONFIG(BL_ME_FIA_PCIE_ROOT_PORT_STATE,<br>+ BL_ME_FIA_PCIE_ROOT_PORT_DISABLED,<br>+ BL_FIA_PCIE_ROOT_PORT_5) |<br>+ BL_FIA_PCIE_ROOT_PORT_CONFIG(BL_ME_FIA_PCIE_ROOT_PORT_STATE,<br>+ BL_ME_FIA_PCIE_ROOT_PORT_ENABLED,<br>+ BL_FIA_PCIE_ROOT_PORT_6) |<br>+ BL_FIA_PCIE_ROOT_PORT_CONFIG(BL_ME_FIA_PCIE_ROOT_PORT_STATE,<br>+ BL_ME_FIA_PCIE_ROOT_PORT_DISABLED,<br>+ BL_FIA_PCIE_ROOT_PORT_7) |<br>+ BL_FIA_PCIE_ROOT_PORT_CONFIG(<br>+ BL_ME_FIA_PCIE_ROOT_PORT_LINK_WIDTH,<br>+ BL_ME_FIA_PCIE_ROOT_PORT_LINK_WIDTH_BICTRL,<br>+ BL_FIA_PCIE_ROOT_PORT_0) |<br>+ BL_FIA_PCIE_ROOT_PORT_CONFIG(<br>+ BL_ME_FIA_PCIE_ROOT_PORT_LINK_WIDTH,<br>+ BL_ME_FIA_PCIE_ROOT_PORT_LINK_WIDTH_BICTRL,<br>+ BL_FIA_PCIE_ROOT_PORT_1) |<br>+ BL_FIA_PCIE_ROOT_PORT_CONFIG(<br>+ BL_ME_FIA_PCIE_ROOT_PORT_LINK_WIDTH,<br>+ BL_ME_FIA_PCIE_ROOT_PORT_LINK_WIDTH_BICTRL,<br>+ BL_FIA_PCIE_ROOT_PORT_2) |<br>+ BL_FIA_PCIE_ROOT_PORT_CONFIG(<br>+ BL_ME_FIA_PCIE_ROOT_PORT_LINK_WIDTH,<br>+ BL_ME_FIA_PCIE_ROOT_PORT_LINK_WIDTH_BICTRL,<br>+ BL_FIA_PCIE_ROOT_PORT_3) |<br>+ BL_FIA_PCIE_ROOT_PORT_CONFIG(<br>+ BL_ME_FIA_PCIE_ROOT_PORT_LINK_WIDTH,<br>+ BL_ME_FIA_PCIE_ROOT_PORT_LINK_WIDTH_BICTRL,<br>+ BL_FIA_PCIE_ROOT_PORT_4) |<br>+ BL_FIA_PCIE_ROOT_PORT_CONFIG(<br>+ BL_ME_FIA_PCIE_ROOT_PORT_LINK_WIDTH,<br>+ BL_ME_FIA_PCIE_ROOT_PORT_LINK_WIDTH_BICTRL,<br>+ BL_FIA_PCIE_ROOT_PORT_5) |<br>+ BL_FIA_PCIE_ROOT_PORT_CONFIG(<br>+ BL_ME_FIA_PCIE_ROOT_PORT_LINK_WIDTH,<br>+ BL_ME_FIA_PCIE_ROOT_PORT_LINK_WIDTH_BICTRL,<br>+ BL_FIA_PCIE_ROOT_PORT_6) |<br>+ BL_FIA_PCIE_ROOT_PORT_CONFIG(<br>+ BL_ME_FIA_PCIE_ROOT_PORT_LINK_WIDTH,<br>+ BL_ME_FIA_PCIE_ROOT_PORT_LINK_WIDTH_BICTRL,<br>+ BL_FIA_PCIE_ROOT_PORT_7)} } },<br>+<br>+ /* SKU HSIO 10 (pcie [0-3, 8-9, 12] sata [16-17] usb [19]) */<br>+ {BL_SKU_HSIO_10,<br>+ {PCIE_BIF_CTRL_x4x4, PCIE_BIF_CTRL_x2x2x2x2},<br>+ {/* ME_FIA_MUX_CONFIG */<br>+ {BL_FIA_LANE_CONFIG(BL_ME_FIA_MUX_LANE_PCIE, BL_FIA_LANE00) |<br>+ BL_FIA_LANE_CONFIG(BL_ME_FIA_MUX_LANE_PCIE, BL_FIA_LANE01) |<br>+ BL_FIA_LANE_CONFIG(BL_ME_FIA_MUX_LANE_PCIE, BL_FIA_LANE02) |<br>+ BL_FIA_LANE_CONFIG(BL_ME_FIA_MUX_LANE_PCIE, BL_FIA_LANE03) |<br>+ BL_FIA_LANE_CONFIG(BL_ME_FIA_MUX_LANE_DISCONNECTED, BL_FIA_LANE04) |<br>+ BL_FIA_LANE_CONFIG(BL_ME_FIA_MUX_LANE_DISCONNECTED, BL_FIA_LANE05) |<br>+ BL_FIA_LANE_CONFIG(BL_ME_FIA_MUX_LANE_DISCONNECTED, BL_FIA_LANE06) |<br>+ BL_FIA_LANE_CONFIG(BL_ME_FIA_MUX_LANE_DISCONNECTED, BL_FIA_LANE07) |<br>+ BL_FIA_LANE_CONFIG(BL_ME_FIA_MUX_LANE_PCIE, BL_FIA_LANE08) |<br>+ BL_FIA_LANE_CONFIG(BL_ME_FIA_MUX_LANE_PCIE, BL_FIA_LANE09) |<br>+ BL_FIA_LANE_CONFIG(BL_ME_FIA_MUX_LANE_DISCONNECTED, BL_FIA_LANE10) |<br>+ BL_FIA_LANE_CONFIG(BL_ME_FIA_MUX_LANE_DISCONNECTED, BL_FIA_LANE11) |<br>+ BL_FIA_LANE_CONFIG(BL_ME_FIA_MUX_LANE_PCIE, BL_FIA_LANE12) |<br>+ BL_FIA_LANE_CONFIG(BL_ME_FIA_MUX_LANE_DISCONNECTED, BL_FIA_LANE13) |<br>+ BL_FIA_LANE_CONFIG(BL_ME_FIA_MUX_LANE_DISCONNECTED, BL_FIA_LANE14) |<br>+ BL_FIA_LANE_CONFIG(BL_ME_FIA_MUX_LANE_DISCONNECTED, BL_FIA_LANE15) |<br>+ BL_FIA_LANE_CONFIG(BL_ME_FIA_MUX_LANE_SATA, BL_FIA_LANE16) |<br>+ BL_FIA_LANE_CONFIG(BL_ME_FIA_MUX_LANE_SATA, BL_FIA_LANE17) |<br>+ BL_FIA_LANE_CONFIG(BL_ME_FIA_MUX_LANE_DISCONNECTED, BL_FIA_LANE18) |<br>+ BL_FIA_LANE_CONFIG(BL_ME_FIA_MUX_LANE_XHCI, BL_FIA_LANE19)},<br>+<br>+ /* ME_FIA_SATA_CONFIG */<br>+ {BL_FIA_SATA_LANE_CONFIG(BL_ME_FIA_SATA_CONTROLLER_LANE_NOT_ASSIGNED,<br>+ BL_FIA_SATA_LANE04) |<br>+ BL_FIA_SATA_LANE_CONFIG(BL_ME_FIA_SATA_CONTROLLER_LANE_NOT_ASSIGNED,<br>+ BL_FIA_SATA_LANE05) |<br>+ BL_FIA_SATA_LANE_CONFIG(BL_ME_FIA_SATA_CONTROLLER_LANE_NOT_ASSIGNED,<br>+ BL_FIA_SATA_LANE06) |<br>+ BL_FIA_SATA_LANE_CONFIG(BL_ME_FIA_SATA_CONTROLLER_LANE_NOT_ASSIGNED,<br>+ BL_FIA_SATA_LANE07) |<br>+ BL_FIA_SATA_LANE_CONFIG(BL_ME_FIA_SATA_CONTROLLER_LANE_NOT_ASSIGNED,<br>+ BL_FIA_SATA_LANE08) |<br>+ BL_FIA_SATA_LANE_CONFIG(BL_ME_FIA_SATA_CONTROLLER_LANE_NOT_ASSIGNED,<br>+ BL_FIA_SATA_LANE09) |<br>+ BL_FIA_SATA_LANE_CONFIG(BL_ME_FIA_SATA_CONTROLLER_LANE_NOT_ASSIGNED,<br>+ BL_FIA_SATA_LANE10) |<br>+ BL_FIA_SATA_LANE_CONFIG(BL_ME_FIA_SATA_CONTROLLER_LANE_NOT_ASSIGNED,<br>+ BL_FIA_SATA_LANE11) |<br>+ BL_FIA_SATA_LANE_CONFIG(BL_ME_FIA_SATA_CONTROLLER_LANE_NOT_ASSIGNED,<br>+ BL_FIA_SATA_LANE12) |<br>+ BL_FIA_SATA_LANE_CONFIG(BL_ME_FIA_SATA_CONTROLLER_LANE_NOT_ASSIGNED,<br>+ BL_FIA_SATA_LANE13) |<br>+ BL_FIA_SATA_LANE_CONFIG(BL_ME_FIA_SATA_CONTROLLER_LANE_NOT_ASSIGNED,<br>+ BL_FIA_SATA_LANE14) |<br>+ BL_FIA_SATA_LANE_CONFIG(BL_ME_FIA_SATA_CONTROLLER_LANE_NOT_ASSIGNED,<br>+ BL_FIA_SATA_LANE15) |<br>+ BL_FIA_SATA_LANE_CONFIG(BL_ME_FIA_SATA_CONTROLLER_LANE_ASSIGNED,<br>+ BL_FIA_SATA_LANE16) |<br>+ BL_FIA_SATA_LANE_CONFIG(BL_ME_FIA_SATA_CONTROLLER_LANE_ASSIGNED,<br>+ BL_FIA_SATA_LANE17) |<br>+ BL_FIA_SATA_LANE_CONFIG(BL_ME_FIA_SATA_CONTROLLER_LANE_NOT_ASSIGNED,<br>+ BL_FIA_SATA_LANE18) |<br>+ BL_FIA_SATA_LANE_CONFIG(BL_ME_FIA_SATA_CONTROLLER_LANE_NOT_ASSIGNED,<br>+ BL_FIA_SATA_LANE19)},<br>+<br>+ /* ME_FIA_PCIE_ROOT_PORTS_CONFIG */<br>+ {BL_FIA_PCIE_ROOT_PORT_CONFIG(BL_ME_FIA_PCIE_ROOT_PORT_STATE,<br>+ BL_ME_FIA_PCIE_ROOT_PORT_ENABLED,<br>+ BL_FIA_PCIE_ROOT_PORT_0) |<br>+ BL_FIA_PCIE_ROOT_PORT_CONFIG(BL_ME_FIA_PCIE_ROOT_PORT_STATE,<br>+ BL_ME_FIA_PCIE_ROOT_PORT_DISABLED,<br>+ BL_FIA_PCIE_ROOT_PORT_1) |<br>+ BL_FIA_PCIE_ROOT_PORT_CONFIG(BL_ME_FIA_PCIE_ROOT_PORT_STATE,<br>+ BL_ME_FIA_PCIE_ROOT_PORT_DISABLED,<br>+ BL_FIA_PCIE_ROOT_PORT_2) |<br>+ BL_FIA_PCIE_ROOT_PORT_CONFIG(BL_ME_FIA_PCIE_ROOT_PORT_STATE,<br>+ BL_ME_FIA_PCIE_ROOT_PORT_DISABLED,<br>+ BL_FIA_PCIE_ROOT_PORT_3) |<br>+ BL_FIA_PCIE_ROOT_PORT_CONFIG(BL_ME_FIA_PCIE_ROOT_PORT_STATE,<br>+ BL_ME_FIA_PCIE_ROOT_PORT_ENABLED,<br>+ BL_FIA_PCIE_ROOT_PORT_4) |<br>+ BL_FIA_PCIE_ROOT_PORT_CONFIG(BL_ME_FIA_PCIE_ROOT_PORT_STATE,<br>+ BL_ME_FIA_PCIE_ROOT_PORT_DISABLED,<br>+ BL_FIA_PCIE_ROOT_PORT_5) |<br>+ BL_FIA_PCIE_ROOT_PORT_CONFIG(BL_ME_FIA_PCIE_ROOT_PORT_STATE,<br>+ BL_ME_FIA_PCIE_ROOT_PORT_ENABLED,<br>+ BL_FIA_PCIE_ROOT_PORT_6) |<br>+ BL_FIA_PCIE_ROOT_PORT_CONFIG(BL_ME_FIA_PCIE_ROOT_PORT_STATE,<br>+ BL_ME_FIA_PCIE_ROOT_PORT_DISABLED,<br>+ BL_FIA_PCIE_ROOT_PORT_7) |<br>+ BL_FIA_PCIE_ROOT_PORT_CONFIG(<br>+ BL_ME_FIA_PCIE_ROOT_PORT_LINK_WIDTH,<br>+ BL_ME_FIA_PCIE_ROOT_PORT_LINK_WIDTH_BICTRL,<br>+ BL_FIA_PCIE_ROOT_PORT_0) |<br>+ BL_FIA_PCIE_ROOT_PORT_CONFIG(<br>+ BL_ME_FIA_PCIE_ROOT_PORT_LINK_WIDTH,<br>+ BL_ME_FIA_PCIE_ROOT_PORT_LINK_WIDTH_BICTRL,<br>+ BL_FIA_PCIE_ROOT_PORT_1) |<br>+ BL_FIA_PCIE_ROOT_PORT_CONFIG(<br>+ BL_ME_FIA_PCIE_ROOT_PORT_LINK_WIDTH,<br>+ BL_ME_FIA_PCIE_ROOT_PORT_LINK_WIDTH_BICTRL,<br>+ BL_FIA_PCIE_ROOT_PORT_2) |<br>+ BL_FIA_PCIE_ROOT_PORT_CONFIG(<br>+ BL_ME_FIA_PCIE_ROOT_PORT_LINK_WIDTH,<br>+ BL_ME_FIA_PCIE_ROOT_PORT_LINK_WIDTH_BICTRL,<br>+ BL_FIA_PCIE_ROOT_PORT_3) |<br>+ BL_FIA_PCIE_ROOT_PORT_CONFIG(<br>+ BL_ME_FIA_PCIE_ROOT_PORT_LINK_WIDTH,<br>+ BL_ME_FIA_PCIE_ROOT_PORT_LINK_WIDTH_BICTRL,<br>+ BL_FIA_PCIE_ROOT_PORT_4) |<br>+ BL_FIA_PCIE_ROOT_PORT_CONFIG(<br>+ BL_ME_FIA_PCIE_ROOT_PORT_LINK_WIDTH,<br>+ BL_ME_FIA_PCIE_ROOT_PORT_LINK_WIDTH_BICTRL,<br>+ BL_FIA_PCIE_ROOT_PORT_5) |<br>+ BL_FIA_PCIE_ROOT_PORT_CONFIG(BL_ME_FIA_PCIE_ROOT_PORT_LINK_WIDTH,<br>+ BL_ME_FIA_PCIE_ROOT_PORT_LINK_X1,<br>+ BL_FIA_PCIE_ROOT_PORT_6) |<br>+ BL_FIA_PCIE_ROOT_PORT_CONFIG(<br>+ BL_ME_FIA_PCIE_ROOT_PORT_LINK_WIDTH,<br>+ BL_ME_FIA_PCIE_ROOT_PORT_LINK_WIDTH_BICTRL,<br>+ BL_FIA_PCIE_ROOT_PORT_7)} } },<br>+<br>+ /* SKU HSIO 8 (pcie [0-1, 8-9, 12] sata [16-17] usb [19]) */<br>+ {BL_SKU_HSIO_08,<br>+ {PCIE_BIF_CTRL_x2x2x2x2, PCIE_BIF_CTRL_x2x2x2x2},<br>+ {/* ME_FIA_MUX_CONFIG */<br>+ {BL_FIA_LANE_CONFIG(BL_ME_FIA_MUX_LANE_PCIE, BL_FIA_LANE00) |<br>+ BL_FIA_LANE_CONFIG(BL_ME_FIA_MUX_LANE_PCIE, BL_FIA_LANE01) |<br>+ BL_FIA_LANE_CONFIG(BL_ME_FIA_MUX_LANE_DISCONNECTED, BL_FIA_LANE02) |<br>+ BL_FIA_LANE_CONFIG(BL_ME_FIA_MUX_LANE_DISCONNECTED, BL_FIA_LANE03) |<br>+ BL_FIA_LANE_CONFIG(BL_ME_FIA_MUX_LANE_DISCONNECTED, BL_FIA_LANE04) |<br>+ BL_FIA_LANE_CONFIG(BL_ME_FIA_MUX_LANE_DISCONNECTED, BL_FIA_LANE05) |<br>+ BL_FIA_LANE_CONFIG(BL_ME_FIA_MUX_LANE_DISCONNECTED, BL_FIA_LANE06) |<br>+ BL_FIA_LANE_CONFIG(BL_ME_FIA_MUX_LANE_DISCONNECTED, BL_FIA_LANE07) |<br>+ BL_FIA_LANE_CONFIG(BL_ME_FIA_MUX_LANE_PCIE, BL_FIA_LANE08) |<br>+ BL_FIA_LANE_CONFIG(BL_ME_FIA_MUX_LANE_PCIE, BL_FIA_LANE09) |<br>+ BL_FIA_LANE_CONFIG(BL_ME_FIA_MUX_LANE_DISCONNECTED, BL_FIA_LANE10) |<br>+ BL_FIA_LANE_CONFIG(BL_ME_FIA_MUX_LANE_DISCONNECTED, BL_FIA_LANE11) |<br>+ BL_FIA_LANE_CONFIG(BL_ME_FIA_MUX_LANE_PCIE, BL_FIA_LANE12) |<br>+ BL_FIA_LANE_CONFIG(BL_ME_FIA_MUX_LANE_DISCONNECTED, BL_FIA_LANE13) |<br>+ BL_FIA_LANE_CONFIG(BL_ME_FIA_MUX_LANE_DISCONNECTED, BL_FIA_LANE14) |<br>+ BL_FIA_LANE_CONFIG(BL_ME_FIA_MUX_LANE_DISCONNECTED, BL_FIA_LANE15) |<br>+ BL_FIA_LANE_CONFIG(BL_ME_FIA_MUX_LANE_SATA, BL_FIA_LANE16) |<br>+ BL_FIA_LANE_CONFIG(BL_ME_FIA_MUX_LANE_SATA, BL_FIA_LANE17) |<br>+ BL_FIA_LANE_CONFIG(BL_ME_FIA_MUX_LANE_DISCONNECTED, BL_FIA_LANE18) |<br>+ BL_FIA_LANE_CONFIG(BL_ME_FIA_MUX_LANE_XHCI, BL_FIA_LANE19)},<br>+<br>+ /* ME_FIA_SATA_CONFIG */<br>+ {BL_FIA_SATA_LANE_CONFIG(BL_ME_FIA_SATA_CONTROLLER_LANE_NOT_ASSIGNED,<br>+ BL_FIA_SATA_LANE04) |<br>+ BL_FIA_SATA_LANE_CONFIG(BL_ME_FIA_SATA_CONTROLLER_LANE_NOT_ASSIGNED,<br>+ BL_FIA_SATA_LANE05) |<br>+ BL_FIA_SATA_LANE_CONFIG(BL_ME_FIA_SATA_CONTROLLER_LANE_NOT_ASSIGNED,<br>+ BL_FIA_SATA_LANE06) |<br>+ BL_FIA_SATA_LANE_CONFIG(BL_ME_FIA_SATA_CONTROLLER_LANE_NOT_ASSIGNED,<br>+ BL_FIA_SATA_LANE07) |<br>+ BL_FIA_SATA_LANE_CONFIG(BL_ME_FIA_SATA_CONTROLLER_LANE_NOT_ASSIGNED,<br>+ BL_FIA_SATA_LANE08) |<br>+ BL_FIA_SATA_LANE_CONFIG(BL_ME_FIA_SATA_CONTROLLER_LANE_NOT_ASSIGNED,<br>+ BL_FIA_SATA_LANE09) |<br>+ BL_FIA_SATA_LANE_CONFIG(BL_ME_FIA_SATA_CONTROLLER_LANE_NOT_ASSIGNED,<br>+ BL_FIA_SATA_LANE10) |<br>+ BL_FIA_SATA_LANE_CONFIG(BL_ME_FIA_SATA_CONTROLLER_LANE_NOT_ASSIGNED,<br>+ BL_FIA_SATA_LANE11) |<br>+ BL_FIA_SATA_LANE_CONFIG(BL_ME_FIA_SATA_CONTROLLER_LANE_NOT_ASSIGNED,<br>+ BL_FIA_SATA_LANE12) |<br>+ BL_FIA_SATA_LANE_CONFIG(BL_ME_FIA_SATA_CONTROLLER_LANE_NOT_ASSIGNED,<br>+ BL_FIA_SATA_LANE13) |<br>+ BL_FIA_SATA_LANE_CONFIG(BL_ME_FIA_SATA_CONTROLLER_LANE_NOT_ASSIGNED,<br>+ BL_FIA_SATA_LANE14) |<br>+ BL_FIA_SATA_LANE_CONFIG(BL_ME_FIA_SATA_CONTROLLER_LANE_NOT_ASSIGNED,<br>+ BL_FIA_SATA_LANE15) |<br>+ BL_FIA_SATA_LANE_CONFIG(BL_ME_FIA_SATA_CONTROLLER_LANE_ASSIGNED,<br>+ BL_FIA_SATA_LANE16) |<br>+ BL_FIA_SATA_LANE_CONFIG(BL_ME_FIA_SATA_CONTROLLER_LANE_ASSIGNED,<br>+ BL_FIA_SATA_LANE17) |<br>+ BL_FIA_SATA_LANE_CONFIG(BL_ME_FIA_SATA_CONTROLLER_LANE_NOT_ASSIGNED,<br>+ BL_FIA_SATA_LANE18) |<br>+ BL_FIA_SATA_LANE_CONFIG(BL_ME_FIA_SATA_CONTROLLER_LANE_NOT_ASSIGNED,<br>+ BL_FIA_SATA_LANE19)},<br>+<br>+ /* ME_FIA_PCIE_ROOT_PORTS_CONFIG */<br>+ {BL_FIA_PCIE_ROOT_PORT_CONFIG(BL_ME_FIA_PCIE_ROOT_PORT_STATE,<br>+ BL_ME_FIA_PCIE_ROOT_PORT_ENABLED,<br>+ BL_FIA_PCIE_ROOT_PORT_0) |<br>+ BL_FIA_PCIE_ROOT_PORT_CONFIG(BL_ME_FIA_PCIE_ROOT_PORT_STATE,<br>+ BL_ME_FIA_PCIE_ROOT_PORT_DISABLED,<br>+ BL_FIA_PCIE_ROOT_PORT_1) |<br>+ BL_FIA_PCIE_ROOT_PORT_CONFIG(BL_ME_FIA_PCIE_ROOT_PORT_STATE,<br>+ BL_ME_FIA_PCIE_ROOT_PORT_DISABLED,<br>+ BL_FIA_PCIE_ROOT_PORT_2) |<br>+ BL_FIA_PCIE_ROOT_PORT_CONFIG(BL_ME_FIA_PCIE_ROOT_PORT_STATE,<br>+ BL_ME_FIA_PCIE_ROOT_PORT_DISABLED,<br>+ BL_FIA_PCIE_ROOT_PORT_3) |<br>+ BL_FIA_PCIE_ROOT_PORT_CONFIG(BL_ME_FIA_PCIE_ROOT_PORT_STATE,<br>+ BL_ME_FIA_PCIE_ROOT_PORT_ENABLED,<br>+ BL_FIA_PCIE_ROOT_PORT_4) |<br>+ BL_FIA_PCIE_ROOT_PORT_CONFIG(BL_ME_FIA_PCIE_ROOT_PORT_STATE,<br>+ BL_ME_FIA_PCIE_ROOT_PORT_DISABLED,<br>+ BL_FIA_PCIE_ROOT_PORT_5) |<br>+ BL_FIA_PCIE_ROOT_PORT_CONFIG(BL_ME_FIA_PCIE_ROOT_PORT_STATE,<br>+ BL_ME_FIA_PCIE_ROOT_PORT_ENABLED,<br>+ BL_FIA_PCIE_ROOT_PORT_6) |<br>+ BL_FIA_PCIE_ROOT_PORT_CONFIG(BL_ME_FIA_PCIE_ROOT_PORT_STATE,<br>+ BL_ME_FIA_PCIE_ROOT_PORT_DISABLED,<br>+ BL_FIA_PCIE_ROOT_PORT_7) |<br>+ BL_FIA_PCIE_ROOT_PORT_CONFIG(<br>+ BL_ME_FIA_PCIE_ROOT_PORT_LINK_WIDTH,<br>+ BL_ME_FIA_PCIE_ROOT_PORT_LINK_WIDTH_BICTRL,<br>+ BL_FIA_PCIE_ROOT_PORT_0) |<br>+ BL_FIA_PCIE_ROOT_PORT_CONFIG(<br>+ BL_ME_FIA_PCIE_ROOT_PORT_LINK_WIDTH,<br>+ BL_ME_FIA_PCIE_ROOT_PORT_LINK_WIDTH_BICTRL,<br>+ BL_FIA_PCIE_ROOT_PORT_1) |<br>+ BL_FIA_PCIE_ROOT_PORT_CONFIG(<br>+ BL_ME_FIA_PCIE_ROOT_PORT_LINK_WIDTH,<br>+ BL_ME_FIA_PCIE_ROOT_PORT_LINK_WIDTH_BICTRL,<br>+ BL_FIA_PCIE_ROOT_PORT_2) |<br>+ BL_FIA_PCIE_ROOT_PORT_CONFIG(<br>+ BL_ME_FIA_PCIE_ROOT_PORT_LINK_WIDTH,<br>+ BL_ME_FIA_PCIE_ROOT_PORT_LINK_WIDTH_BICTRL,<br>+ BL_FIA_PCIE_ROOT_PORT_3) |<br>+ BL_FIA_PCIE_ROOT_PORT_CONFIG(<br>+ BL_ME_FIA_PCIE_ROOT_PORT_LINK_WIDTH,<br>+ BL_ME_FIA_PCIE_ROOT_PORT_LINK_WIDTH_BICTRL,<br>+ BL_FIA_PCIE_ROOT_PORT_4) |<br>+ BL_FIA_PCIE_ROOT_PORT_CONFIG(<br>+ BL_ME_FIA_PCIE_ROOT_PORT_LINK_WIDTH,<br>+ BL_ME_FIA_PCIE_ROOT_PORT_LINK_WIDTH_BICTRL,<br>+ BL_FIA_PCIE_ROOT_PORT_5) |<br>+ BL_FIA_PCIE_ROOT_PORT_CONFIG(BL_ME_FIA_PCIE_ROOT_PORT_LINK_WIDTH,<br>+ BL_ME_FIA_PCIE_ROOT_PORT_LINK_X1,<br>+ BL_FIA_PCIE_ROOT_PORT_6) |<br>+ BL_FIA_PCIE_ROOT_PORT_CONFIG(<br>+ BL_ME_FIA_PCIE_ROOT_PORT_LINK_WIDTH,<br>+ BL_ME_FIA_PCIE_ROOT_PORT_LINK_WIDTH_BICTRL,<br>+ BL_FIA_PCIE_ROOT_PORT_7)} } },<br>+<br>+ /* SKU HSIO 6 (pcie [0-1, 8, 12] sata [16] usb [19]) */<br>+ {BL_SKU_HSIO_06,<br>+ {PCIE_BIF_CTRL_x2x2x2x2, PCIE_BIF_CTRL_x2x2x2x2},<br>+ {/* ME_FIA_MUX_CONFIG */<br>+ {BL_FIA_LANE_CONFIG(BL_ME_FIA_MUX_LANE_PCIE, BL_FIA_LANE00) |<br>+ BL_FIA_LANE_CONFIG(BL_ME_FIA_MUX_LANE_PCIE, BL_FIA_LANE01) |<br>+ BL_FIA_LANE_CONFIG(BL_ME_FIA_MUX_LANE_DISCONNECTED, BL_FIA_LANE02) |<br>+ BL_FIA_LANE_CONFIG(BL_ME_FIA_MUX_LANE_DISCONNECTED, BL_FIA_LANE03) |<br>+ BL_FIA_LANE_CONFIG(BL_ME_FIA_MUX_LANE_DISCONNECTED, BL_FIA_LANE04) |<br>+ BL_FIA_LANE_CONFIG(BL_ME_FIA_MUX_LANE_DISCONNECTED, BL_FIA_LANE05) |<br>+ BL_FIA_LANE_CONFIG(BL_ME_FIA_MUX_LANE_DISCONNECTED, BL_FIA_LANE06) |<br>+ BL_FIA_LANE_CONFIG(BL_ME_FIA_MUX_LANE_DISCONNECTED, BL_FIA_LANE07) |<br>+ BL_FIA_LANE_CONFIG(BL_ME_FIA_MUX_LANE_PCIE, BL_FIA_LANE08) |<br>+ BL_FIA_LANE_CONFIG(BL_ME_FIA_MUX_LANE_DISCONNECTED, BL_FIA_LANE09) |<br>+ BL_FIA_LANE_CONFIG(BL_ME_FIA_MUX_LANE_DISCONNECTED, BL_FIA_LANE10) |<br>+ BL_FIA_LANE_CONFIG(BL_ME_FIA_MUX_LANE_DISCONNECTED, BL_FIA_LANE11) |<br>+ BL_FIA_LANE_CONFIG(BL_ME_FIA_MUX_LANE_PCIE, BL_FIA_LANE12) |<br>+ BL_FIA_LANE_CONFIG(BL_ME_FIA_MUX_LANE_DISCONNECTED, BL_FIA_LANE13) |<br>+ BL_FIA_LANE_CONFIG(BL_ME_FIA_MUX_LANE_DISCONNECTED, BL_FIA_LANE14) |<br>+ BL_FIA_LANE_CONFIG(BL_ME_FIA_MUX_LANE_DISCONNECTED, BL_FIA_LANE15) |<br>+ BL_FIA_LANE_CONFIG(BL_ME_FIA_MUX_LANE_SATA, BL_FIA_LANE16) |<br>+ BL_FIA_LANE_CONFIG(BL_ME_FIA_MUX_LANE_DISCONNECTED, BL_FIA_LANE17) |<br>+ BL_FIA_LANE_CONFIG(BL_ME_FIA_MUX_LANE_DISCONNECTED, BL_FIA_LANE18) |<br>+ BL_FIA_LANE_CONFIG(BL_ME_FIA_MUX_LANE_XHCI, BL_FIA_LANE19)},<br>+<br>+ /* ME_FIA_SATA_CONFIG */<br>+ {BL_FIA_SATA_LANE_CONFIG(BL_ME_FIA_SATA_CONTROLLER_LANE_NOT_ASSIGNED,<br>+ BL_FIA_SATA_LANE04) |<br>+ BL_FIA_SATA_LANE_CONFIG(BL_ME_FIA_SATA_CONTROLLER_LANE_NOT_ASSIGNED,<br>+ BL_FIA_SATA_LANE05) |<br>+ BL_FIA_SATA_LANE_CONFIG(BL_ME_FIA_SATA_CONTROLLER_LANE_NOT_ASSIGNED,<br>+ BL_FIA_SATA_LANE06) |<br>+ BL_FIA_SATA_LANE_CONFIG(BL_ME_FIA_SATA_CONTROLLER_LANE_NOT_ASSIGNED,<br>+ BL_FIA_SATA_LANE07) |<br>+ BL_FIA_SATA_LANE_CONFIG(BL_ME_FIA_SATA_CONTROLLER_LANE_NOT_ASSIGNED,<br>+ BL_FIA_SATA_LANE08) |<br>+ BL_FIA_SATA_LANE_CONFIG(BL_ME_FIA_SATA_CONTROLLER_LANE_NOT_ASSIGNED,<br>+ BL_FIA_SATA_LANE09) |<br>+ BL_FIA_SATA_LANE_CONFIG(BL_ME_FIA_SATA_CONTROLLER_LANE_NOT_ASSIGNED,<br>+ BL_FIA_SATA_LANE10) |<br>+ BL_FIA_SATA_LANE_CONFIG(BL_ME_FIA_SATA_CONTROLLER_LANE_NOT_ASSIGNED,<br>+ BL_FIA_SATA_LANE11) |<br>+ BL_FIA_SATA_LANE_CONFIG(BL_ME_FIA_SATA_CONTROLLER_LANE_NOT_ASSIGNED,<br>+ BL_FIA_SATA_LANE12) |<br>+ BL_FIA_SATA_LANE_CONFIG(BL_ME_FIA_SATA_CONTROLLER_LANE_NOT_ASSIGNED,<br>+ BL_FIA_SATA_LANE13) |<br>+ BL_FIA_SATA_LANE_CONFIG(BL_ME_FIA_SATA_CONTROLLER_LANE_NOT_ASSIGNED,<br>+ BL_FIA_SATA_LANE14) |<br>+ BL_FIA_SATA_LANE_CONFIG(BL_ME_FIA_SATA_CONTROLLER_LANE_NOT_ASSIGNED,<br>+ BL_FIA_SATA_LANE15) |<br>+ BL_FIA_SATA_LANE_CONFIG(BL_ME_FIA_SATA_CONTROLLER_LANE_ASSIGNED,<br>+ BL_FIA_SATA_LANE16) |<br>+ BL_FIA_SATA_LANE_CONFIG(BL_ME_FIA_SATA_CONTROLLER_LANE_NOT_ASSIGNED,<br>+ BL_FIA_SATA_LANE17) |<br>+ BL_FIA_SATA_LANE_CONFIG(BL_ME_FIA_SATA_CONTROLLER_LANE_NOT_ASSIGNED,<br>+ BL_FIA_SATA_LANE18) |<br>+ BL_FIA_SATA_LANE_CONFIG(BL_ME_FIA_SATA_CONTROLLER_LANE_NOT_ASSIGNED,<br>+ BL_FIA_SATA_LANE19)},<br>+<br>+ /* ME_FIA_PCIE_ROOT_PORTS_CONFIG */<br>+ {BL_FIA_PCIE_ROOT_PORT_CONFIG(BL_ME_FIA_PCIE_ROOT_PORT_STATE,<br>+ BL_ME_FIA_PCIE_ROOT_PORT_ENABLED,<br>+ BL_FIA_PCIE_ROOT_PORT_0) |<br>+ BL_FIA_PCIE_ROOT_PORT_CONFIG(BL_ME_FIA_PCIE_ROOT_PORT_STATE,<br>+ BL_ME_FIA_PCIE_ROOT_PORT_DISABLED,<br>+ BL_FIA_PCIE_ROOT_PORT_1) |<br>+ BL_FIA_PCIE_ROOT_PORT_CONFIG(BL_ME_FIA_PCIE_ROOT_PORT_STATE,<br>+ BL_ME_FIA_PCIE_ROOT_PORT_DISABLED,<br>+ BL_FIA_PCIE_ROOT_PORT_2) |<br>+ BL_FIA_PCIE_ROOT_PORT_CONFIG(BL_ME_FIA_PCIE_ROOT_PORT_STATE,<br>+ BL_ME_FIA_PCIE_ROOT_PORT_DISABLED,<br>+ BL_FIA_PCIE_ROOT_PORT_3) |<br>+ BL_FIA_PCIE_ROOT_PORT_CONFIG(BL_ME_FIA_PCIE_ROOT_PORT_STATE,<br>+ BL_ME_FIA_PCIE_ROOT_PORT_ENABLED,<br>+ BL_FIA_PCIE_ROOT_PORT_4) |<br>+ BL_FIA_PCIE_ROOT_PORT_CONFIG(BL_ME_FIA_PCIE_ROOT_PORT_STATE,<br>+ BL_ME_FIA_PCIE_ROOT_PORT_DISABLED,<br>+ BL_FIA_PCIE_ROOT_PORT_5) |<br>+ BL_FIA_PCIE_ROOT_PORT_CONFIG(BL_ME_FIA_PCIE_ROOT_PORT_STATE,<br>+ BL_ME_FIA_PCIE_ROOT_PORT_ENABLED,<br>+ BL_FIA_PCIE_ROOT_PORT_6) |<br>+ BL_FIA_PCIE_ROOT_PORT_CONFIG(BL_ME_FIA_PCIE_ROOT_PORT_STATE,<br>+ BL_ME_FIA_PCIE_ROOT_PORT_DISABLED,<br>+ BL_FIA_PCIE_ROOT_PORT_7) |<br>+ BL_FIA_PCIE_ROOT_PORT_CONFIG(<br>+ BL_ME_FIA_PCIE_ROOT_PORT_LINK_WIDTH,<br>+ BL_ME_FIA_PCIE_ROOT_PORT_LINK_WIDTH_BICTRL,<br>+ BL_FIA_PCIE_ROOT_PORT_0) |<br>+ BL_FIA_PCIE_ROOT_PORT_CONFIG(<br>+ BL_ME_FIA_PCIE_ROOT_PORT_LINK_WIDTH,<br>+ BL_ME_FIA_PCIE_ROOT_PORT_LINK_WIDTH_BICTRL,<br>+ BL_FIA_PCIE_ROOT_PORT_1) |<br>+ BL_FIA_PCIE_ROOT_PORT_CONFIG(<br>+ BL_ME_FIA_PCIE_ROOT_PORT_LINK_WIDTH,<br>+ BL_ME_FIA_PCIE_ROOT_PORT_LINK_WIDTH_BICTRL,<br>+ BL_FIA_PCIE_ROOT_PORT_2) |<br>+ BL_FIA_PCIE_ROOT_PORT_CONFIG(<br>+ BL_ME_FIA_PCIE_ROOT_PORT_LINK_WIDTH,<br>+ BL_ME_FIA_PCIE_ROOT_PORT_LINK_WIDTH_BICTRL,<br>+ BL_FIA_PCIE_ROOT_PORT_3) |<br>+ BL_FIA_PCIE_ROOT_PORT_CONFIG(BL_ME_FIA_PCIE_ROOT_PORT_LINK_WIDTH,<br>+ BL_ME_FIA_PCIE_ROOT_PORT_LINK_X1,<br>+ BL_FIA_PCIE_ROOT_PORT_4) |<br>+ BL_FIA_PCIE_ROOT_PORT_CONFIG(<br>+ BL_ME_FIA_PCIE_ROOT_PORT_LINK_WIDTH,<br>+ BL_ME_FIA_PCIE_ROOT_PORT_LINK_WIDTH_BICTRL,<br>+ BL_FIA_PCIE_ROOT_PORT_5) |<br>+ BL_FIA_PCIE_ROOT_PORT_CONFIG(BL_ME_FIA_PCIE_ROOT_PORT_LINK_WIDTH,<br>+ BL_ME_FIA_PCIE_ROOT_PORT_LINK_X1,<br>+ BL_FIA_PCIE_ROOT_PORT_6) |<br>+ BL_FIA_PCIE_ROOT_PORT_CONFIG(<br>+ BL_ME_FIA_PCIE_ROOT_PORT_LINK_WIDTH,<br>+ BL_ME_FIA_PCIE_ROOT_PORT_LINK_WIDTH_BICTRL,<br>+ BL_FIA_PCIE_ROOT_PORT_7)} } }<br>+};<br>+#endif<br>+#endif<br>+/* _MAINBOARD_HSIO_H */<br>diff --git a/src/mainboard/intel/harcuvar/ramstage.c b/src/mainboard/intel/harcuvar/ramstage.c<br>new file mode 100644<br>index 0000000..4d90858<br>--- /dev/null<br>+++ b/src/mainboard/intel/harcuvar/ramstage.c<br>@@ -0,0 +1,56 @@<br>+/*<br>+ * This file is part of the coreboot project.<br>+ *<br>+ * Copyright (C) 2014 - 2017 Intel Corporation<br>+ *<br>+ * This program is free software; you can redistribute it and/or modify<br>+ * it under the terms of the GNU General Public License as published by<br>+ * the Free Software Foundation; version 2 of the License.<br>+ *<br>+ * This program is distributed in the hope that it will be useful,<br>+ * but WITHOUT ANY WARRANTY; without even the implied warranty of<br>+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the<br>+ * GNU General Public License for more details.<br>+ *<br>+ */<br>+<br>+#include <console/console.h><br>+#include <fsp/api.h><br>+#include <soc/ramstage.h><br>+#include "emmc.h"<br>+<br>+static int get_emmc_dll_info(uint16_t signature, size_t num_of_entry,<br>+ BL_EMMC_INFORMATION **config)<br>+{<br>+ uint8_t entry;<br>+<br>+ if ((signature == 0) || (num_of_entry == 0) || (*config == NULL))<br>+ return 1;<br>+<br>+ for (entry = 0; entry < num_of_entry; entry++) {<br>+ if ((*config)[entry].Signature == signature) {<br>+ *config = &(*config)[entry];<br>+ return 0;<br>+ }<br>+ }<br>+<br>+ return 1;<br>+}<br>+<br>+void mainboard_silicon_init_params(FSPS_UPD *params)<br>+{<br>+ size_t num;<br>+ uint16_t emmc_dll_sign;<br>+ BL_EMMC_INFORMATION *emmc_config;<br>+<br>+ /* Configure eMMC DLL PCD */<br>+ emmc_dll_sign = DEFAULT_EMMC_DLL_SIGN;<br>+ num = ARRAY_SIZE(harcuvar_emmc_config);<br>+ emmc_config = harcuvar_emmc_config;<br>+<br>+ if (get_emmc_dll_info(emmc_dll_sign, num, &emmc_config))<br>+ die("eMMC DLL Configuration is invalid, please correct it!");<br>+<br>+ params->FspsConfig.PcdEMMCDLLConfigPtr =<br>+ (uint32_t)&emmc_config->eMMCDLLConfig;<br>+}<br>diff --git a/src/mainboard/intel/harcuvar/romstage.c b/src/mainboard/intel/harcuvar/romstage.c<br>new file mode 100644<br>index 0000000..b235feb<br>--- /dev/null<br>+++ b/src/mainboard/intel/harcuvar/romstage.c<br>@@ -0,0 +1,119 @@<br>+/*<br>+ * This file is part of the coreboot project.<br>+ *<br>+ * Copyright (C) 2017 Intel Corp.<br>+ *<br>+ * This program is free software; you can redistribute it and/or modify<br>+ * it under the terms of the GNU General Public License as published by<br>+ * the Free Software Foundation; either version 2 of the License, or<br>+ * (at your option) any later version.<br>+ *<br>+ * This program is distributed in the hope that it will be useful,<br>+ * but WITHOUT ANY WARRANTY; without even the implied warranty of<br>+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the<br>+ * GNU General Public License for more details.<br>+ */<br>+<br>+#include "harcuvar_boardid.h"<br>+#include "gpio.h"<br>+#include "spd/spd.h"<br>+#include <console/console.h><br>+#include <fsp/api.h><br>+#include <fsp/soc_binding.h><br>+#include <string.h><br>+<br>+#if IS_ENABLED(CONFIG_ENABLE_FSP_MEMORY_DOWN)<br>+/*<br>+ * Define platform specific Memory Down Configure structure.<br>+ */<br>+const MEMORY_DOWN_CONFIG mMemoryDownConfig = {<br>+ .SlotState = {<br>+#if IS_ENABLED(CONFIG_ENABLE_MEMORY_DOWN_CH0)<br>+ {STATE_MEMORY_DOWN, STATE_MEMORY_SLOT},<br>+#else<br>+ {STATE_MEMORY_SLOT, STATE_MEMORY_SLOT},<br>+#endif<br>+#if IS_ENABLED(CONFIG_ENABLE_MEMORY_DOWN_CH1)<br>+ {STATE_MEMORY_DOWN, STATE_MEMORY_SLOT},<br>+#else<br>+ {STATE_MEMORY_SLOT, STATE_MEMORY_SLOT},<br>+#endif<br>+ },<br>+ .SpdDataLen = MAX_SPD_BYTES,<br>+ .SpdDataPtr = {<br>+#if IS_ENABLED(CONFIG_ENABLE_MEMORY_DOWN_CH0)<br>+ {(void *)CONFIG_SPD_LOC, (void *)CONFIG_SPD_LOC},<br>+#else<br>+ {(void *)NULL, (void *)NULL},<br>+#endif<br>+#if IS_ENABLED(CONFIG_ENABLE_MEMORY_DOWN_CH1)<br>+ {(void *)CONFIG_SPD_LOC, (void *)CONFIG_SPD_LOC},<br>+#else<br>+ {(void *)NULL, (void *)NULL},<br>+#endif<br>+ },<br>+};<br>+#endif /* CONFIG_ENABLE_FSP_MEMORY_DOWN */<br>+<br>+void mainboard_config_gpios(void);<br>+void mainboard_memory_init_params(FSPM_UPD *mupd);<br>+<br>+/*<br>+* Configure GPIO depend on platform<br>+*/<br>+void mainboard_config_gpios(void)<br>+{<br>+ size_t num;<br>+ const struct pad_config *table;<br>+ uint8_t boardid = board_id();<br>+<br>+ /* Configure pads prior to SiliconInit() in case there's any<br>+ * dependencies during hardware initialization.<br>+ */<br>+ switch (boardid) {<br>+ case BoardIdHarcuvar:<br>+ table = harcuvar_gpio_table;<br>+ num = ARRAY_SIZE(harcuvar_gpio_table);<br>+ break;<br>+ default:<br>+ table = NULL;<br>+ num = 0;<br>+ break;<br>+ }<br>+<br>+ if ((!table) || (!num)) {<br>+ printk(BIOS_ERR, "ERROR: No valid GPIO table found!\n");<br>+ return;<br>+ }<br>+<br>+ printk(BIOS_INFO, "GPIO table: 0x%x, entry num: 0x%x!\n",<br>+ (uint32_t)table, (uint32_t)num);<br>+ gpio_configure_pads(table, num);<br>+}<br>+<br>+void mainboard_memory_init_params(FSPM_UPD *mupd)<br>+{<br>+#if IS_ENABLED(CONFIG_ENABLE_FSP_MEMORY_DOWN)<br>+ uint8_t *spd_data_ptr = NULL;<br>+<br>+ /* Get SPD data pointer */<br>+ spd_data_ptr = mainboard_find_spd_data();<br>+<br>+ if (spd_data_ptr != NULL) {<br>+ printk(BIOS_DEBUG, "Memory Down function is enabled!\n");<br>+<br>+ /* Enable Memory Down function, set Memory<br>+ * Down Configure structure pointer.<br>+ */<br>+ mupd->FspmConfig.PcdMemoryDown = 1;<br>+ mupd->FspmConfig.PcdMemoryDownConfigPtr =<br>+ (uint32_t)&mMemoryDownConfig;<br>+ } else {<br>+ printk(BIOS_DEBUG, "Memory Down function is disabled!\n");<br>+<br>+ /* Disable Memory Down function */<br>+ mupd->FspmConfig.PcdMemoryDown = 0;<br>+ mupd->FspmConfig.PcdMemoryDownConfigPtr = 0;<br>+ }<br>+#endif /* CONFIG_ENABLE_FSP_MEMORY_DOWN */<br>+}<br>diff --git a/src/mainboard/intel/harcuvar/spd/Makefile.inc b/src/mainboard/intel/harcuvar/spd/Makefile.inc<br>new file mode 100644<br>index 0000000..9dd926d<br>--- /dev/null<br>+++ b/src/mainboard/intel/harcuvar/spd/Makefile.inc<br>@@ -0,0 +1,39 @@<br>+##<br>+## This file is part of the coreboot project.<br>+##<br>+## Copyright (C) 2013 Google Inc.<br>+## Copyright (C) 2015 - 2017 Intel Corporation.<br>+##<br>+## This program is free software; you can redistribute it and/or modify<br>+## it under the terms of the GNU General Public License as published by<br>+## the Free Software Foundation; version 2 of the License.<br>+##<br>+## This program is distributed in the hope that it will be useful,<br>+## but WITHOUT ANY WARRANTY; without even the implied warranty of<br>+## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the<br>+## GNU General Public License for more details.<br>+##<br>+<br>+romstage-y += spd.c<br>+<br>+SPD_BIN = $(obj)/spd.bin<br>+<br>+# Order matters for SPD sources. The following indicies<br>+# define the SPD data to use.<br>+SPD_SOURCES = micron_4GiB_dimm_MTA9ASF51272PZ-2G1A2<br>+#SPD_SOURCES = micron_4GiB_sodimm_MTA8ATF51264HZ-2G1A2<br>+<br>+SPD_DEPS := $(foreach f, $(SPD_SOURCES), src/mainboard/$(MAINBOARDDIR)/spd/$(f).spd.hex)<br>+<br>+# Include spd rom data<br>+$(SPD_BIN): $(SPD_DEPS)<br>+ for f in $+; \<br>+ do for c in $$(cat $$f | grep -v ^#); \<br>+ do echo -e -n "\\x$$c"; \<br>+ done; \<br>+ done > $@<br>+<br>+cbfs-files-y += spd.bin<br>+spd.bin-file := $(SPD_BIN)<br>+spd.bin-position := $(CONFIG_SPD_LOC)<br>+spd.bin-type := spd<br>diff --git a/src/mainboard/intel/harcuvar/spd/micron_4GiB_dimm_MTA9ASF51272PZ-2G1A2.spd.hex b/src/mainboard/intel/harcuvar/spd/micron_4GiB_dimm_MTA9ASF51272PZ-2G1A2.spd.hex<br>new file mode 100644<br>index 0000000..4abad8d<br>--- /dev/null<br>+++ b/src/mainboard/intel/harcuvar/spd/micron_4GiB_dimm_MTA9ASF51272PZ-2G1A2.spd.hex<br>@@ -0,0 +1,513 @@<br>+#DDR4_4GB_RDIMM_Micron_MTA9ASF51272PZ-2G1A2.txt<br>+23<br>+10<br>+0C<br>+01<br>+84<br>+19<br>+00<br>+05<br>+00<br>+00<br>+00<br>+03<br>+01<br>+0B<br>+80<br>+00<br>+00<br>+00<br>+08<br>+0C<br>+F4<br>+1B<br>+00<br>+00<br>+6C<br>+6C<br>+6C<br>+11<br>+08<br>+74<br>+20<br>+08<br>+00<br>+05<br>+70<br>+03<br>+00<br>+A8<br>+1E<br>+2B<br>+2B<br>+00<br>+00<br>+00<br>+00<br>+00<br>+00<br>+00<br>+00<br>+00<br>+00<br>+00<br>+00<br>+00<br>+00<br>+00<br>+00<br>+00<br>+00<br>+00<br>+0E<br>+2E<br>+16<br>+36<br>+16<br>+36<br>+16<br>+36<br>+0E<br>+2E<br>+23<br>+04<br>+2B<br>+0C<br>+2B<br>+0C<br>+23<br>+04<br>+00<br>+00<br>+00<br>+00<br>+00<br>+00<br>+00<br>+00<br>+00<br>+00<br>+00<br>+00<br>+00<br>+00<br>+00<br>+00<br>+00<br>+00<br>+00<br>+00<br>+00<br>+00<br>+00<br>+00<br>+00<br>+00<br>+00<br>+00<br>+00<br>+00<br>+00<br>+00<br>+00<br>+00<br>+00<br>+00<br>+00<br>+00<br>+00<br>+EC<br>+B5<br>+CE<br>+00<br>+00<br>+00<br>+00<br>+00<br>+C2<br>+64<br>+2B<br>+11<br>+11<br>+03<br>+05<br>+00<br>+86<br>+32<br>+B1<br>+00<br>+00<br>+00<br>+00<br>+00<br>+00<br>+00<br>+00<br>+00<br>+00<br>+00<br>+00<br>+00<br>+00<br>+00<br>+00<br>+00<br>+00<br>+00<br>+00<br>+00<br>+00<br>+00<br>+00<br>+00<br>+00<br>+00<br>+00<br>+00<br>+00<br>+00<br>+00<br>+00<br>+00<br>+00<br>+00<br>+00<br>+00<br>+00<br>+00<br>+00<br>+00<br>+00<br>+00<br>+00<br>+00<br>+00<br>+00<br>+00<br>+00<br>+00<br>+00<br>+00<br>+00<br>+00<br>+00<br>+00<br>+00<br>+00<br>+00<br>+00<br>+00<br>+00<br>+00<br>+00<br>+00<br>+00<br>+00<br>+00<br>+00<br>+00<br>+00<br>+00<br>+00<br>+00<br>+00<br>+00<br>+00<br>+00<br>+00<br>+00<br>+00<br>+00<br>+00<br>+00<br>+00<br>+00<br>+00<br>+00<br>+00<br>+00<br>+00<br>+00<br>+00<br>+00<br>+00<br>+00<br>+00<br>+00<br>+00<br>+00<br>+00<br>+00<br>+00<br>+00<br>+00<br>+00<br>+00<br>+00<br>+00<br>+00<br>+00<br>+00<br>+00<br>+00<br>+00<br>+00<br>+00<br>+EF<br>+9E<br>+00<br>+00<br>+00<br>+00<br>+00<br>+00<br>+00<br>+00<br>+00<br>+00<br>+00<br>+00<br>+00<br>+00<br>+00<br>+00<br>+00<br>+00<br>+00<br>+00<br>+00<br>+00<br>+00<br>+00<br>+00<br>+00<br>+00<br>+00<br>+00<br>+00<br>+00<br>+00<br>+00<br>+00<br>+00<br>+00<br>+00<br>+00<br>+00<br>+00<br>+00<br>+00<br>+00<br>+00<br>+00<br>+00<br>+00<br>+00<br>+00<br>+00<br>+00<br>+00<br>+00<br>+00<br>+00<br>+00<br>+00<br>+00<br>+00<br>+00<br>+00<br>+00<br>+00<br>+00<br>+80<br>+2C<br>+00<br>+00<br>+00<br>+00<br>+00<br>+00<br>+00<br>+39<br>+41<br>+53<br>+46<br>+35<br>+31<br>+32<br>+37<br>+32<br>+50<br>+5a<br>+2d<br>+32<br>+47<br>+31<br>+41<br>+32<br>+00<br>+00<br>+00<br>+32<br>+80<br>+2C<br>+41<br>+00<br>+00<br>+00<br>+00<br>+00<br>+00<br>+00<br>+00<br>+00<br>+00<br>+00<br>+00<br>+00<br>+00<br>+00<br>+00<br>+00<br>+00<br>+00<br>+00<br>+00<br>+00<br>+00<br>+00<br>+00<br>+00<br>+00<br>+00<br>+00<br>+00<br>+00<br>+00<br>+00<br>+00<br>+00<br>+00<br>+00<br>+00<br>+00<br>+00<br>+00<br>+00<br>+00<br>+00<br>+00<br>+00<br>+00<br>+00<br>+00<br>+00<br>+00<br>+00<br>+00<br>+00<br>+00<br>+00<br>+00<br>+00<br>+00<br>+00<br>+00<br>+00<br>+00<br>+00<br>+00<br>+00<br>+00<br>+00<br>+00<br>+00<br>+00<br>+00<br>+00<br>+00<br>+00<br>+00<br>+00<br>+00<br>+00<br>+00<br>+00<br>+00<br>+00<br>+00<br>+00<br>+00<br>+00<br>+00<br>+00<br>+00<br>+00<br>+00<br>+00<br>+00<br>+00<br>+00<br>+00<br>+00<br>+00<br>+00<br>+00<br>+00<br>+00<br>+00<br>+00<br>+00<br>+00<br>+00<br>+00<br>+00<br>+00<br>+00<br>+00<br>+00<br>+00<br>+00<br>+00<br>+00<br>+00<br>+00<br>+00<br>+00<br>+00<br>+00<br>+00<br>+00<br>+00<br>+00<br>+00<br>+00<br>+00<br>+00<br>+00<br>+00<br>+00<br>+00<br>+00<br>+00<br>+00<br>+00<br>+00<br>+00<br>+00<br>+00<br>+00<br>+00<br>+00<br>+00<br>+00<br>+00<br>+00<br>+00<br>+00<br>+00<br>+00<br>+00<br>+00<br>+00<br>+00<br>diff --git a/src/mainboard/intel/harcuvar/spd/micron_4GiB_sodimm_MTA8ATF51264HZ-2G1A2.spd.hex b/src/mainboard/intel/harcuvar/spd/micron_4GiB_sodimm_MTA8ATF51264HZ-2G1A2.spd.hex<br>new file mode 100644<br>index 0000000..cd70a83<br>--- /dev/null<br>+++ b/src/mainboard/intel/harcuvar/spd/micron_4GiB_sodimm_MTA8ATF51264HZ-2G1A2.spd.hex<br>@@ -0,0 +1,513 @@<br>+#DDR4_4GB_SODIMM_Micron_MTA8ATF51264HZ-2G1A2.txt<br>+23<br>+10<br>+0C<br>+03<br>+84<br>+19<br>+00<br>+08<br>+00<br>+00<br>+00<br>+03<br>+01<br>+03<br>+00<br>+00<br>+00<br>+00<br>+08<br>+0C<br>+F4<br>+1B<br>+00<br>+00<br>+6C<br>+6C<br>+6C<br>+11<br>+08<br>+74<br>+20<br>+08<br>+00<br>+05<br>+70<br>+03<br>+00<br>+A8<br>+1E<br>+2B<br>+2B<br>+00<br>+00<br>+00<br>+00<br>+00<br>+00<br>+00<br>+00<br>+00<br>+00<br>+00<br>+00<br>+00<br>+00<br>+00<br>+00<br>+00<br>+00<br>+00<br>+0C<br>+2B<br>+2D<br>+04<br>+16<br>+35<br>+23<br>+0D<br>+00<br>+00<br>+2C<br>+0B<br>+03<br>+24<br>+35<br>+0C<br>+03<br>+2D<br>+00<br>+00<br>+00<br>+00<br>+00<br>+00<br>+00<br>+00<br>+00<br>+00<br>+00<br>+00<br>+00<br>+00<br>+00<br>+00<br>+00<br>+00<br>+00<br>+00<br>+00<br>+00<br>+00<br>+00<br>+00<br>+00<br>+00<br>+00<br>+00<br>+00<br>+00<br>+00<br>+00<br>+00<br>+00<br>+00<br>+00<br>+00<br>+00<br>+EC<br>+B5<br>+CE<br>+00<br>+00<br>+00<br>+00<br>+00<br>+C2<br>+D4<br>+84<br>+0F<br>+11<br>+00<br>+00<br>+00<br>+00<br>+00<br>+00<br>+00<br>+00<br>+00<br>+00<br>+00<br>+00<br>+00<br>+00<br>+00<br>+00<br>+00<br>+00<br>+00<br>+00<br>+00<br>+00<br>+00<br>+00<br>+00<br>+00<br>+00<br>+00<br>+00<br>+00<br>+00<br>+00<br>+00<br>+00<br>+00<br>+00<br>+00<br>+00<br>+00<br>+00<br>+00<br>+00<br>+00<br>+00<br>+00<br>+00<br>+00<br>+00<br>+00<br>+00<br>+00<br>+00<br>+00<br>+00<br>+00<br>+00<br>+00<br>+00<br>+00<br>+00<br>+00<br>+00<br>+00<br>+00<br>+00<br>+00<br>+00<br>+00<br>+00<br>+00<br>+00<br>+00<br>+00<br>+00<br>+00<br>+00<br>+00<br>+00<br>+00<br>+00<br>+00<br>+00<br>+00<br>+00<br>+00<br>+00<br>+00<br>+00<br>+00<br>+00<br>+00<br>+00<br>+00<br>+00<br>+00<br>+00<br>+00<br>+00<br>+00<br>+00<br>+00<br>+00<br>+00<br>+00<br>+00<br>+00<br>+00<br>+00<br>+00<br>+00<br>+00<br>+00<br>+00<br>+00<br>+00<br>+00<br>+00<br>+00<br>+00<br>+00<br>+00<br>+00<br>+00<br>+00<br>+45<br>+AD<br>+00<br>+00<br>+00<br>+00<br>+00<br>+00<br>+00<br>+00<br>+00<br>+00<br>+00<br>+00<br>+00<br>+00<br>+00<br>+00<br>+00<br>+00<br>+00<br>+00<br>+00<br>+00<br>+00<br>+00<br>+00<br>+00<br>+00<br>+00<br>+00<br>+00<br>+00<br>+00<br>+00<br>+00<br>+00<br>+00<br>+00<br>+00<br>+00<br>+00<br>+00<br>+00<br>+00<br>+00<br>+00<br>+00<br>+00<br>+00<br>+00<br>+00<br>+00<br>+00<br>+00<br>+00<br>+00<br>+00<br>+00<br>+00<br>+00<br>+00<br>+00<br>+00<br>+00<br>+00<br>+80<br>+2C<br>+00<br>+00<br>+00<br>+00<br>+00<br>+00<br>+00<br>+38<br>+41<br>+54<br>+46<br>+35<br>+31<br>+32<br>+36<br>+34<br>+48<br>+5A<br>+2D<br>+32<br>+47<br>+31<br>+41<br>+32<br>+00<br>+00<br>+00<br>+32<br>+80<br>+2C<br>+41<br>+00<br>+00<br>+00<br>+00<br>+00<br>+00<br>+00<br>+00<br>+00<br>+00<br>+00<br>+00<br>+00<br>+00<br>+00<br>+00<br>+00<br>+00<br>+00<br>+00<br>+00<br>+00<br>+00<br>+00<br>+00<br>+00<br>+00<br>+00<br>+00<br>+00<br>+00<br>+00<br>+00<br>+00<br>+00<br>+00<br>+00<br>+00<br>+00<br>+00<br>+00<br>+00<br>+00<br>+00<br>+00<br>+00<br>+00<br>+00<br>+00<br>+00<br>+00<br>+00<br>+00<br>+00<br>+00<br>+00<br>+00<br>+00<br>+00<br>+00<br>+00<br>+00<br>+00<br>+00<br>+00<br>+00<br>+00<br>+00<br>+00<br>+00<br>+00<br>+00<br>+00<br>+00<br>+00<br>+00<br>+00<br>+00<br>+00<br>+00<br>+00<br>+00<br>+00<br>+00<br>+00<br>+00<br>+00<br>+00<br>+00<br>+00<br>+00<br>+00<br>+00<br>+00<br>+00<br>+00<br>+00<br>+00<br>+00<br>+00<br>+00<br>+00<br>+00<br>+00<br>+00<br>+00<br>+00<br>+00<br>+00<br>+00<br>+00<br>+00<br>+00<br>+00<br>+00<br>+00<br>+00<br>+00<br>+00<br>+00<br>+00<br>+00<br>+00<br>+00<br>+00<br>+00<br>+00<br>+00<br>+00<br>+00<br>+00<br>+00<br>+00<br>+00<br>+00<br>+00<br>+00<br>+00<br>+00<br>+00<br>+00<br>+00<br>+00<br>+00<br>+00<br>+00<br>+00<br>+00<br>+00<br>+00<br>+00<br>+00<br>+00<br>+00<br>+00<br>+00<br>+00<br>+00<br>+00<br>diff --git a/src/mainboard/intel/harcuvar/spd/spd.c b/src/mainboard/intel/harcuvar/spd/spd.c<br>new file mode 100644<br>index 0000000..37f4424<br>--- /dev/null<br>+++ b/src/mainboard/intel/harcuvar/spd/spd.c<br>@@ -0,0 +1,58 @@<br>+/*<br>+ * This file is part of the coreboot project.<br>+ *<br>+ * Copyright (C) 2014 Google Inc.<br>+ * Copyright (C) 2015 - 2017 Intel Corporation.<br>+ *<br>+ * This program is free software; you can redistribute it and/or modify<br>+ * it under the terms of the GNU General Public License as published by<br>+ * the Free Software Foundation; version 2 of the License.<br>+ *<br>+ * This program is distributed in the hope that it will be useful,<br>+ * but WITHOUT ANY WARRANTY; without even the implied warranty of<br>+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the<br>+ * GNU General Public License for more details.<br>+ *<br>+ */<br>+<br>+#include <arch/byteorder.h><br>+#include <cbfs.h><br>+#include <console/console.h><br>+#include <string.h><br>+<br>+#include "spd.h"<br>+<br>+/* Get SPD data for on-board memory */<br>+uint8_t *mainboard_find_spd_data()<br>+{<br>+ uint8_t *spd_data;<br>+ int spd_index;<br>+ size_t spd_file_len;<br>+ char *spd_file;<br>+<br>+ spd_index = 0;<br>+<br>+ spd_file = cbfs_boot_map_with_leak("spd.bin", CBFS_TYPE_SPD,<br>+ &spd_file_len);<br>+ if (!spd_file)<br>+ die("SPD data not found.");<br>+<br>+ if (spd_file_len < ((spd_index + 1) * SPD_LEN)) {<br>+ printk(BIOS_ERR,<br>+ "SPD index override to 0 due to incorrect SPD index.\n");<br>+ spd_index = 0;<br>+ }<br>+<br>+ if (spd_file_len < SPD_LEN)<br>+ die("Missing SPD data.");<br>+<br>+ /* Assume same memory in both channels */<br>+ spd_index *= SPD_LEN;<br>+ spd_data = (uint8_t *)(spd_file + spd_index);<br>+<br>+ /* Make sure a valid SPD was found */<br>+ if (spd_data[0] == 0)<br>+ die("Invalid SPD data.");<br>+<br>+ return spd_data;<br>+}<br>diff --git a/src/mainboard/intel/harcuvar/spd/spd.h b/src/mainboard/intel/harcuvar/spd/spd.h<br>new file mode 100644<br>index 0000000..13692d7<br>--- /dev/null<br>+++ b/src/mainboard/intel/harcuvar/spd/spd.h<br>@@ -0,0 +1,35 @@<br>+/*<br>+ * This file is part of the coreboot project.<br>+ *<br>+ * Copyright (C) 2014 Google Inc.<br>+ * Copyright (C) 2015 - 2017 Intel Corporation.<br>+ *<br>+ * This program is free software; you can redistribute it and/or modify<br>+ * it under the terms of the GNU General Public License as published by<br>+ * the Free Software Foundation; version 2 of the License.<br>+ *<br>+ * This program is distributed in the hope that it will be useful,<br>+ * but WITHOUT ANY WARRANTY; without even the implied warranty of<br>+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the<br>+ * GNU General Public License for more details.<br>+ *<br>+ */<br>+<br>+#ifndef MAINBOARD_SPD_H<br>+#define MAINBOARD_SPD_H<br>+<br>+#define SPD_LEN 512<br>+<br>+#define SPD_DRAM_TYPE 2<br>+#define SPD_DRAM_DDR3 0x0b<br>+#define SPD_DRAM_LPDDR3 0xf1<br>+#define SPD_DENSITY_BANKS 4<br>+#define SPD_ADDRESSING 5<br>+#define SPD_ORGANIZATION 7<br>+#define SPD_BUS_DEV_WIDTH 8<br>+#define SPD_PART_OFF 128<br>+#define SPD_PART_LEN 18<br>+<br>+uint8_t *mainboard_find_spd_data(void);<br>+<br>+#endif<br></pre><p>To view, visit <a href="https://review.coreboot.org/20862">change 20862</a>. To unsubscribe, visit <a href="https://review.coreboot.org/settings">settings</a>.</p><div itemscope itemtype="http://schema.org/EmailMessage"><div itemscope itemprop="action" itemtype="http://schema.org/ViewAction"><link itemprop="url" href="https://review.coreboot.org/20862"/><meta itemprop="name" content="View Change"/></div></div>
<div style="display:none"> Gerrit-Project: coreboot </div>
<div style="display:none"> Gerrit-Branch: master </div>
<div style="display:none"> Gerrit-MessageType: newchange </div>
<div style="display:none"> Gerrit-Change-Id: I088833e36e2d22d1fe1610b8dca1454092da511a </div>
<div style="display:none"> Gerrit-Change-Number: 20862 </div>
<div style="display:none"> Gerrit-PatchSet: 1 </div>
<div style="display:none"> Gerrit-Owner: Mariusz Szafranski </div>