<p>Mariusz Szafranski has uploaded this change for <strong>review</strong>.</p><p><a href="https://review.coreboot.org/20805">View Change</a></p><pre style="font-family: monospace,monospace; white-space: pre-wrap;">vendorcode/intel/fsp/fsp2_0/denverton_ns: Add FSP header files for Denverton_NS SoC<br><br>Change-Id: I9672610df09089c549e74072345781bea0b4d06f<br>Signed-off-by: Mariusz Szafranski <mariuszx.szafranski@intel.com><br>---<br>A src/vendorcode/intel/fsp/fsp2_0/denverton_ns/FspUpd.h<br>A src/vendorcode/intel/fsp/fsp2_0/denverton_ns/FspmUpd.h<br>A src/vendorcode/intel/fsp/fsp2_0/denverton_ns/FspsUpd.h<br>A src/vendorcode/intel/fsp/fsp2_0/denverton_ns/FsptUpd.h<br>4 files changed, 1,156 insertions(+), 0 deletions(-)<br><br></pre><pre style="font-family: monospace,monospace; white-space: pre-wrap;">git pull ssh://review.coreboot.org:29418/coreboot refs/changes/05/20805/1</pre><pre style="font-family: monospace,monospace; white-space: pre-wrap;">diff --git a/src/vendorcode/intel/fsp/fsp2_0/denverton_ns/FspUpd.h b/src/vendorcode/intel/fsp/fsp2_0/denverton_ns/FspUpd.h<br>new file mode 100644<br>index 0000000..ec523a4<br>--- /dev/null<br>+++ b/src/vendorcode/intel/fsp/fsp2_0/denverton_ns/FspUpd.h<br>@@ -0,0 +1,48 @@<br>+/** @file<br>+<br>+Copyright (c) 2017, Intel Corporation. All rights reserved.<BR><br>+<br>+Redistribution and use in source and binary forms, with or without modification,<br>+are permitted provided that the following conditions are met:<br>+<br>+* Redistributions of source code must retain the above copyright notice, this<br>+ list of conditions and the following disclaimer.<br>+* Redistributions in binary form must reproduce the above copyright notice, this<br>+ list of conditions and the following disclaimer in the documentation and/or<br>+ other materials provided with the distribution.<br>+* Neither the name of Intel Corporation nor the names of its contributors may<br>+ be used to endorse or promote products derived from this software without<br>+ specific prior written permission.<br>+<br>+ THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"<br>+ AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE<br>+ IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE<br>+ ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE<br>+ LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR<br>+ CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF<br>+ SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS<br>+ INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN<br>+ CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)<br>+ ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF<br>+ THE POSSIBILITY OF SUCH DAMAGE.<br>+<br>+ This file is automatically generated. Please do NOT modify !!!<br>+<br>+**/<br>+<br>+#ifndef __FSPUPD_H__<br>+#define __FSPUPD_H__<br>+<br>+#include <FspEas.h><br>+<br>+#pragma pack(push, 1)<br>+<br>+#define FSPT_UPD_SIGNATURE 0x545F445055564E44 /* 'DNVUPD_T' */<br>+<br>+#define FSPM_UPD_SIGNATURE 0x4D5F445055564E44 /* 'DNVUPD_M' */<br>+<br>+#define FSPS_UPD_SIGNATURE 0x535F445055564E44 /* 'DNVUPD_S' */<br>+<br>+#pragma pack(pop)<br>+<br>+#endif<br>diff --git a/src/vendorcode/intel/fsp/fsp2_0/denverton_ns/FspmUpd.h b/src/vendorcode/intel/fsp/fsp2_0/denverton_ns/FspmUpd.h<br>new file mode 100644<br>index 0000000..cf0e36d<br>--- /dev/null<br>+++ b/src/vendorcode/intel/fsp/fsp2_0/denverton_ns/FspmUpd.h<br>@@ -0,0 +1,710 @@<br>+/** @file<br>+<br>+Copyright (c) 2017, Intel Corporation. All rights reserved.<BR><br>+<br>+Redistribution and use in source and binary forms, with or without modification,<br>+are permitted provided that the following conditions are met:<br>+<br>+* Redistributions of source code must retain the above copyright notice, this<br>+ list of conditions and the following disclaimer.<br>+* Redistributions in binary form must reproduce the above copyright notice, this<br>+ list of conditions and the following disclaimer in the documentation and/or<br>+ other materials provided with the distribution.<br>+* Neither the name of Intel Corporation nor the names of its contributors may<br>+ be used to endorse or promote products derived from this software without<br>+ specific prior written permission.<br>+<br>+ THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"<br>+ AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE<br>+ IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE<br>+ ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE<br>+ LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR<br>+ CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF<br>+ SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS<br>+ INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN<br>+ CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)<br>+ ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF<br>+ THE POSSIBILITY OF SUCH DAMAGE.<br>+<br>+ This file is automatically generated. Please do NOT modify !!!<br>+<br>+**/<br>+<br>+#ifndef __FSPMUPD_H__<br>+#define __FSPMUPD_H__<br>+<br>+#include <FspUpd.h><br>+<br>+#pragma pack(push, 1)<br>+<br>+#define MAX_CH 2 /* Maximum Number of Memory Channels */<br>+#define MAX_DIMM 2 /* Maximum Number of DIMMs PER Memory Channel */<br>+#define MAX_SPD_BYTES 512 /* Maximum Number of SPD bytes */<br>+<br>+/*<br>+ * Memory Down structures.<br>+ */<br>+typedef enum {<br>+ STATE_MEMORY_SLOT = 0, /* No memory down and a physical memory slot. */<br>+ STATE_MEMORY_DOWN = 1, /* Memory down and not a physical memory slot. */<br>+} MemorySlotState;<br>+<br>+typedef struct {<br>+ MemorySlotState SlotState[MAX_CH][MAX_DIMM]; /* Memory Down state of<br>+ each DIMM in each<br>+ Channel */<br>+ UINT16 SpdDataLen; /* Length in Bytes of a single DIMM's SPD Data */<br>+ UINT8 *SpdDataPtr[MAX_CH][MAX_DIMM]; /* Pointer to SPD Data for each<br>+ DIMM in each Channel */<br>+} MEMORY_DOWN_CONFIG;<br>+<br>+/*<br>+* SMBIOS Memory Info structures.<br>+*/<br>+typedef struct {<br>+ UINT8 DimmId;<br>+ UINT32 SizeInMb;<br>+ UINT16 MfgId;<br>+ UINT8<br>+ ModulePartNum[20]; /* Module part number for DDR3 is 18 bytes<br>+ however for DRR4 20 bytes as per JEDEC Spec,<br>+ so reserving 20 bytes */<br>+} DIMM_INFO;<br>+<br>+typedef struct {<br>+ UINT8 ChannelId;<br>+ UINT8 DimmCount;<br>+ DIMM_INFO DimmInfo[MAX_DIMM];<br>+} CHANNEL_INFO;<br>+<br>+typedef struct {<br>+ UINT8 Revision;<br>+ UINT16 DataWidth;<br>+ /** As defined in SMBIOS 3.0 spec<br>+ Section 7.18.2 and Table 75<br>+ **/<br>+ UINT8 MemoryType;<br>+ UINT16 MemoryFrequencyInMHz;<br>+ /** As defined in SMBIOS 3.0 spec<br>+ Section 7.17.3 and Table 72<br>+ **/<br>+ UINT8 ErrorCorrectionType;<br>+ UINT8 ChannelCount;<br>+ CHANNEL_INFO ChannelInfo[MAX_CH];<br>+} FSP_SMBIOS_MEMORY_INFO;<br>+<br>+/*<br>+* GBE PCD supported states.<br>+*/<br>+typedef enum {<br>+ BL_GBE0_GBE1_DISABLED,<br>+ BL_GBE0_GBE1_ENABLED,<br>+ BL_GBE1_DISABLED,<br>+} BL_GBE_PCD_STATE;<br>+<br>+/*<br>+* FIA MUX configuration structures.<br>+*/<br>+<br>+#define BL_ME_FIA_MUX_LANE_NUM_MAX 20<br>+#define BL_ME_FIA_MUX_LANE_NUM_MIN 1<br>+#define BL_ME_FIA_MUX_LANE_MUX_SEL_WIDTH 2<br>+#define BL_ME_FIA_MUX_LANE_MUX_SEL_MASK 0x3<br>+#define BL_ME_FIA_MUX_LANE_XHCI_ONLY 0xFF00000000<br>+<br>+typedef enum {<br>+ BL_FIA_LANE00 = 0,<br>+ BL_FIA_LANE01,<br>+ BL_FIA_LANE02,<br>+ BL_FIA_LANE03,<br>+ BL_FIA_LANE04,<br>+ BL_FIA_LANE05,<br>+ BL_FIA_LANE06,<br>+ BL_FIA_LANE07,<br>+ BL_FIA_LANE08,<br>+ BL_FIA_LANE09,<br>+ BL_FIA_LANE10,<br>+ BL_FIA_LANE11,<br>+ BL_FIA_LANE12,<br>+ BL_FIA_LANE13,<br>+ BL_FIA_LANE14,<br>+ BL_FIA_LANE15,<br>+ BL_FIA_LANE16,<br>+ BL_FIA_LANE17,<br>+ BL_FIA_LANE18,<br>+ BL_FIA_LANE19,<br>+} BL_ME_FIA_MUX_LANE_ORDER;<br>+<br>+#define BL_ME_FIA_MUX_LANE_SATA0_BEGING BL_FIA_LANE04<br>+#define BL_ME_FIA_MUX_LANE_SATA1_BEGING BL_FIA_LANE12<br>+<br>+#define BL_FIA_LANE_CONFIG(Config, Lane) \<br>+ ((UINT64)((UINT64)(Config) \<br>+ << ((UINT64)(Lane) * (BL_ME_FIA_MUX_LANE_MUX_SEL_WIDTH))))<br>+<br>+typedef union _BL_ME_FIA_MUX_CONFIG {<br>+ UINT64 MeFiaMuxLaneConfig;<br>+ struct {<br>+ UINT64 Lane00MuxSel : 2; // ME_FIA_MUX_LANE_DISABLED or PCIE<br>+ UINT64 Lane01MuxSel : 2; // ME_FIA_MUX_LANE_DISABLED or PCIE<br>+ UINT64 Lane02MuxSel : 2; // ME_FIA_MUX_LANE_DISABLED or PCIE<br>+ UINT64 Lane03MuxSel : 2; // ME_FIA_MUX_LANE_DISABLED or PCIE<br>+ UINT64 Lane04MuxSel : 2; // ME_FIA_MUX_LANE_DISABLED or PCIE or<br>+ // SATA<br>+ UINT64 Lane05MuxSel : 2; // ME_FIA_MUX_LANE_DISABLED or PCIE or<br>+ // SATA<br>+ UINT64 Lane06MuxSel : 2; // ME_FIA_MUX_LANE_DISABLED or PCIE or<br>+ // SATA<br>+ UINT64 Lane07MuxSel : 2; // ME_FIA_MUX_LANE_DISABLED or PCIE or<br>+ // SATA<br>+ UINT64 Lane08MuxSel : 2; // ME_FIA_MUX_LANE_DISABLED or PCIE or<br>+ // SATA<br>+ UINT64 Lane09MuxSel : 2; // ME_FIA_MUX_LANE_DISABLED or PCIE or<br>+ // SATA<br>+ UINT64 Lane10MuxSel : 2; // ME_FIA_MUX_LANE_DISABLED or PCIE or<br>+ // SATA<br>+ UINT64 Lane11MuxSel : 2; // ME_FIA_MUX_LANE_DISABLED or PCIE or<br>+ // SATA<br>+ UINT64 Lane12MuxSel : 2; // ME_FIA_MUX_LANE_DISABLED or PCIE or<br>+ // SATA<br>+ UINT64 Lane13MuxSel : 2; // ME_FIA_MUX_LANE_DISABLED or PCIE or<br>+ // SATA<br>+ UINT64 Lane14MuxSel : 2; // ME_FIA_MUX_LANE_DISABLED or PCIE or<br>+ // SATA<br>+ UINT64 Lane15MuxSel : 2; // ME_FIA_MUX_LANE_DISABLED or PCIE or<br>+ // SATA<br>+ UINT64 Lane16MuxSel : 2; // ME_FIA_MUX_LANE_DISABLED or XHCI or<br>+ // SATA<br>+ UINT64 Lane17MuxSel : 2; // ME_FIA_MUX_LANE_DISABLED or XHCI or<br>+ // SATA<br>+ UINT64 Lane18MuxSel : 2; // ME_FIA_MUX_LANE_DISABLED or XHCI or<br>+ // SATA<br>+ UINT64 Lane19MuxSel : 2; // ME_FIA_MUX_LANE_DISABLED or XHCI or<br>+ // SATA<br>+ UINT64 Reserved : 24;<br>+ } BL_MeFiaMuxLaneMuxSel;<br>+} BL_ME_FIA_MUX_CONFIG;<br>+<br>+typedef enum {<br>+ BL_ME_FIA_MUX_LANE_DISCONNECTED,<br>+ BL_ME_FIA_MUX_LANE_PCIE,<br>+ BL_ME_FIA_MUX_LANE_SATA,<br>+ BL_ME_FIA_MUX_LANE_XHCI,<br>+} BL_ME_FIA_MUX_LANE_CONFIG;<br>+<br>+#define BL_ME_FIA_SATA_LANE_SEL_WIDTH 2<br>+#define BL_ME_FIA_SATA_LANE_XHCI_ONLY 0x55000000<br>+<br>+typedef enum {<br>+ BL_FIA_SATA_LANE04 = 0,<br>+ BL_FIA_SATA_LANE05,<br>+ BL_FIA_SATA_LANE06,<br>+ BL_FIA_SATA_LANE07,<br>+ BL_FIA_SATA_LANE08,<br>+ BL_FIA_SATA_LANE09,<br>+ BL_FIA_SATA_LANE10,<br>+ BL_FIA_SATA_LANE11,<br>+ BL_FIA_SATA_LANE12,<br>+ BL_FIA_SATA_LANE13,<br>+ BL_FIA_SATA_LANE14,<br>+ BL_FIA_SATA_LANE15,<br>+ BL_FIA_SATA_LANE16,<br>+ BL_FIA_SATA_LANE17,<br>+ BL_FIA_SATA_LANE18,<br>+ BL_FIA_SATA_LANE19<br>+} BL_ME_FIA_SATA_LANE_ORDER;<br>+<br>+#define BL_FIA_SATA_LANE_CONFIG(Config, Lane) \<br>+ ((UINT32)((UINT32)(Config) \<br>+ << ((UINT32)(Lane) * (BL_ME_FIA_SATA_LANE_SEL_WIDTH))))<br>+<br>+typedef union _BL_ME_FIA_SATA_CONFIG {<br>+ UINT64 MeFiaSataLaneConfig;<br>+ struct {<br>+ UINT64 Lane04SataSel : 2;<br>+ UINT64 Lane05SataSel : 2;<br>+ UINT64 Lane06SataSel : 2;<br>+ UINT64 Lane07SataSel : 2;<br>+ UINT64 Lane08SataSel : 2;<br>+ UINT64 Lane09SataSel : 2;<br>+ UINT64 Lane10SataSel : 2;<br>+ UINT64 Lane11SataSel : 2;<br>+ UINT64 Lane12SataSel : 2;<br>+ UINT64 Lane13SataSel : 2;<br>+ UINT64 Lane14SataSel : 2;<br>+ UINT64 Lane15SataSel : 2;<br>+ UINT64 Lane16SataSel : 2;<br>+ UINT64 Lane17SataSel : 2;<br>+ UINT64 Lane18SataSel : 2;<br>+ UINT64 Lane19SataSel : 2;<br>+ UINT64 Reserved : 32;<br>+ } BL_MeFiaSataLaneSataSel;<br>+} BL_ME_FIA_SATA_CONFIG;<br>+<br>+typedef enum {<br>+ BL_ME_FIA_SATA_CONTROLLER_LANE_ASSIGNED = 0,<br>+ BL_ME_FIA_SATA_CONTROLLER_LANE_NOT_ASSIGNED = 1,<br>+ BL_ME_FIA_SATA_CONTROLLER_LANE_SS_AND_GPIO_ASSIGNED = 3<br>+} BL_ME_FIA_SATA_LANE_CONFIG;<br>+<br>+#define BL_ME_FIA_PCIE_ROOT_PORT_LINK_WIDTH_SEL_WIDTH 4<br>+#define BL_ME_FIA_PCIE_ROOT_PORTS_STATE_WIDTH 8<br>+#define BL_ME_FIA_PCIE_ROOT_CONFIG_XHCI_ONLY 0x0<br>+<br>+typedef enum {<br>+ BL_FIA_PCIE_ROOT_PORT_0 = 0,<br>+ BL_FIA_PCIE_ROOT_PORT_1,<br>+ BL_FIA_PCIE_ROOT_PORT_2,<br>+ BL_FIA_PCIE_ROOT_PORT_3,<br>+ BL_FIA_PCIE_ROOT_PORT_4,<br>+ BL_FIA_PCIE_ROOT_PORT_5,<br>+ BL_FIA_PCIE_ROOT_PORT_6,<br>+ BL_FIA_PCIE_ROOT_PORT_7<br>+} BL_ME_FIA_PCIE_ROOT_PORT_ORDER;<br>+<br>+#define BL_FIA_PCIE_ROOT_PORT_CONFIG(Type, Config, PcieRootPort) \<br>+ (((Type) == BL_ME_FIA_PCIE_ROOT_PORT_STATE) \<br>+ ? ((UINT64)((UINT64)(Config) << (UINT64)(PcieRootPort))) \<br>+ : ((UINT64)( \<br>+ (UINT64)(Config) << (UINT64)( \<br>+ ((UINT64)(PcieRootPort) * \<br>+ (BL_ME_FIA_PCIE_ROOT_PORT_LINK_WIDTH_SEL_WIDTH)) + \<br>+ BL_ME_FIA_PCIE_ROOT_PORTS_STATE_WIDTH))))<br>+<br>+typedef union _BL_ME_FIA_PCIE_ROOT_PORTS_CONFIG {<br>+ UINT64 MeFiaPcieRootPortsConfig;<br>+ struct {<br>+ UINT64 PcieRp0En : 1;<br>+ UINT64 PcieRp1En : 1;<br>+ UINT64 PcieRp2En : 1;<br>+ UINT64 PcieRp3En : 1;<br>+ UINT64 PcieRp4En : 1;<br>+ UINT64 PcieRp5En : 1;<br>+ UINT64 PcieRp6En : 1;<br>+ UINT64 PcieRp7En : 1;<br>+ UINT64 PcieRp0LinkWidth : 4;<br>+ UINT64 PcieRp1LinkWidth : 4;<br>+ UINT64 PcieRp2LinkWidth : 4;<br>+ UINT64 PcieRp3LinkWidth : 4;<br>+ UINT64 PcieRp4LinkWidth : 4;<br>+ UINT64 PcieRp5LinkWidth : 4;<br>+ UINT64 PcieRp6LinkWidth : 4;<br>+ UINT64 PcieRp7LinkWidth : 4;<br>+ UINT64 Reserved : 24;<br>+ } BL_MeFiaPcieRpConfig;<br>+} BL_ME_FIA_PCIE_ROOT_PORTS_CONFIG;<br>+<br>+typedef enum {<br>+ BL_ME_FIA_PCIE_ROOT_PORT_STATE,<br>+ BL_ME_FIA_PCIE_ROOT_PORT_LINK_WIDTH<br>+} BL_ME_FIA_PCIE_ROOT_PORT_CONFIG_TYPE;<br>+<br>+typedef enum {<br>+ BL_ME_FIA_PCIE_ROOT_PORT_DISABLED,<br>+ BL_ME_FIA_PCIE_ROOT_PORT_ENABLED<br>+} BL_ME_FIA_PCIE_ROOT_PORT_STATE_CONFIG;<br>+<br>+typedef enum {<br>+ BL_ME_FIA_PCIE_ROOT_PORT_LINK_WIDTH_BICTRL = 0,<br>+ BL_ME_FIA_PCIE_ROOT_PORT_LINK_X1 = 0xF<br>+} BL_ME_FIA_PCIE_ROOT_PORT_LINK_CONFIG;<br>+<br>+typedef struct _BL_ME_FIA_CONFIG {<br>+ BL_ME_FIA_MUX_CONFIG MuxConfiguration;<br>+ BL_ME_FIA_SATA_CONFIG SataLaneConfiguration;<br>+ BL_ME_FIA_PCIE_ROOT_PORTS_CONFIG PcieRootPortsConfiguration;<br>+} BL_ME_FIA_CONFIG;<br>+<br>+/*<br>+ * The FIA_MUX_CONFIG block describes the expected configuration of<br>+ * FIA MUX configuration.<br>+ */<br>+typedef struct {<br>+ UINT32 SkuNumLanesAllowed; // Platform view of Num Lanes allowed<br>+ BL_ME_FIA_CONFIG FiaMuxConfig; // Current Platform FIA MUX Configuration<br>+ BL_ME_FIA_CONFIG FiaMuxConfigRequest; // FIA MUX Configuration Requested<br>+} BL_FIA_MUX_CONFIG;<br>+<br>+/*<br>+ * The FIA_MUX_CONFIG_STATUS describes the status of configuring<br>+ * FIA MUX configuration.<br>+*/<br>+typedef struct {<br>+ UINT64 FiaMuxConfigGetStatus; // Status returned from FiaMuxConfigGet,<br>+ // if not EFI_SUCCESS, then error occurred<br>+ // and user can decide on next steps<br>+ UINT64 FiaMuxConfigSetStatus; // Status returned from FiaMuxConfigSet,<br>+ // if not EFI_SUCCESS, then error occurred<br>+ // and user can decide on next steps<br>+ BOOLEAN FiaMuxConfigSetRequired; // Boolean: true - a FiaMuxConfigSet<br>+ // was required, false otherwise<br>+} BL_FIA_MUX_CONFIG_STATUS;<br>+<br>+/*<br>+* FIA MUX Config HOB structure<br>+*/<br>+typedef struct {<br>+ BL_FIA_MUX_CONFIG FiaMuxConfig;<br>+ BL_FIA_MUX_CONFIG_STATUS FiaMuxConfigStatus;<br>+} BL_FIA_MUX_CONFIG_HOB;<br>+<br>+/* PCIe port bifurcation codes - matches setup option values */<br>+#define PCIE_BIF_CTRL_x2x2x2x2 0<br>+#define PCIE_BIF_CTRL_x2x2x4 1<br>+#define PCIE_BIF_CTRL_x4x2x2 2<br>+#define PCIE_BIF_CTRL_x4x4 3<br>+#define PCIE_BIF_CTRL_x8 4<br>+<br>+#define BL_MAX_PCIE_CTRL 2<br>+<br>+/*<br>+ * HSIO INFORMATION structure<br>+ */<br>+typedef enum {<br>+ BL_SKU_HSIO_06 = 6,<br>+ BL_SKU_HSIO_08 = 8,<br>+ BL_SKU_HSIO_10 = 10,<br>+ BL_SKU_HSIO_12 = 12,<br>+ BL_SKU_HSIO_20 = 20,<br>+} BL_SKU_HSIO_LANE_NUMBER;<br>+<br>+typedef struct {<br>+ UINT16 NumLanesSupported;<br>+ UINT8 PcieBifCtr[BL_MAX_PCIE_CTRL];<br>+ BL_ME_FIA_CONFIG FiaConfig;<br>+} BL_HSIO_INFORMATION;<br>+<br>+/*<br>+ * eMMC DLL structure for EMMC DLL registers settings<br>+ */<br>+typedef struct {<br>+ UINT32 TxCmdCntl;<br>+ UINT32 TxDataCntl1;<br>+ UINT32 TxDataCntl2;<br>+ UINT32 RxCmdDataCntl1;<br>+ UINT32 RxStrobeCntl;<br>+ UINT32 RxCmdDataCntl2;<br>+ UINT32 MasterSwCntl;<br>+} BL_EMMC_DLL_CONFIG;<br>+<br>+typedef struct {<br>+ UINT16 Signature;<br>+ BL_EMMC_DLL_CONFIG eMMCDLLConfig;<br>+} BL_EMMC_INFORMATION;<br>+<br>+typedef enum {<br>+ BL_FAST_BOOT_CHECKER_NORMAL = 0,<br>+ BL_FAST_BOOT_CHECKER_WARNING,<br>+ BL_FAST_BOOT_CHECKER_CRITICAL<br>+} BL_FAST_BOOT_CHECKER;<br>+<br>+#define BL_MAX_SCRUB_SEGMENTS 5<br>+<br>+typedef struct {<br>+ UINT16 Start; // Determines the low range for a memory segment (in MB)<br>+ UINT16 End; // Determines the high range for a memory segment (in MB)<br>+} BL_SCRUB_SEGMENT;<br>+<br>+typedef struct {<br>+ UINT8 NumberOfSegments;<br>+ UINT8 Reserved;<br>+ BL_SCRUB_SEGMENT ScrubSegment[BL_MAX_SCRUB_SEGMENTS];<br>+} BL_MEMORY_SCRUB_SEGMENTS;<br>+<br>+/** Fsp M Configuration<br>+**/<br>+typedef struct {<br>+<br>+ /** Offset 0x0040 - Tseg Size<br>+ Size of SMRAM memory reserved.<br>+ 2:2 MB, 4:4 MB, 8:8 MB, 16:16 MB<br>+ **/<br>+ UINT8 PcdSmmTsegSize;<br>+<br>+ /** Offset 0x0041 - FSP Debug Print Level<br>+ Select the FSP debug message print level.<br>+ 0:NO DEBUG, 1:MIN DEBUG, 2:MED DEBUG, 3:VERBOSE DEBUG<br>+ **/<br>+ UINT8 PcdFspDebugPrintErrorLevel;<br>+<br>+ /** Offset 0x0042 - Channel 0 DIMM 0 SPD SMBus Address<br>+ SPD SMBus Address of each DIMM slot.<br>+ **/<br>+ UINT8 PcdSpdSmbusAddress_0_0;<br>+<br>+ /** Offset 0x0043 - Channel 0 DIMM 1 SPD SMBus Address<br>+ SPD SMBus Address of each DIMM slot.<br>+ **/<br>+ UINT8 PcdSpdSmbusAddress_0_1;<br>+<br>+ /** Offset 0x0044 - Channel 1 DIMM 0 SPD SMBus Address<br>+ SPD SMBus Address of each DIMM slot.<br>+ **/<br>+ UINT8 PcdSpdSmbusAddress_1_0;<br>+<br>+ /** Offset 0x0045 - Channel 1 DIMM 1 SPD SMBus Address<br>+ SPD SMBus Address of each DIMM slot.<br>+ **/<br>+ UINT8 PcdSpdSmbusAddress_1_1;<br>+<br>+ /** Offset 0x0046 - Enable Rank Margin Tool<br>+ Enable/disable Rank Margin Tool.<br>+ $EN_DIS<br>+ **/<br>+ UINT8 PcdMrcRmtSupport;<br>+<br>+ /** Offset 0x0047 - RMT CPGC exp_loop_cnt<br>+ Set the CPGC exp_loop_cnt field for RMT execution 2^(exp_loop_cnt -1).<br>+ 1:1, 2:2, 3:3, 4:4, 5:5, 6:6, 7:7, 8:8, 9:9, 10:10, 11:11, 12:12,<br>+ 13:13, 14:14, 15:15<br>+ **/<br>+ UINT8 PcdMrcRmtCpgcExpLoopCntValue;<br>+<br>+ /** Offset 0x0048 - RMT CPGC num_bursts<br>+ Set the CPGC num_bursts field for RMT execution 2^(num_bursts -1).<br>+ 1:1, 2:2, 3:3, 4:4, 5:5, 6:6, 7:7, 8:8, 9:9, 10:10, 11:11, 12:12,<br>+ 13:13, 14:14, 15:15<br>+ **/<br>+ UINT8 PcdMrcRmtCpgcNumBursts;<br>+<br>+ /** Offset 0x0049 - Preserve Memory Across Reset<br>+ Enable/disable memory preservation across reset.<br>+ $EN_DIS<br>+ **/<br>+ UINT8 PcdMemoryPreservation;<br>+<br>+ /** Offset 0x004A - Fast Boot<br>+ Enable/disable Fast Boot function. Once enabled, all following boots<br>+ will use the<br>+ presaved MRC data to improve the boot performance.<br>+ $EN_DIS<br>+ **/<br>+ UINT8 PcdFastBoot;<br>+<br>+ /** Offset 0x004B - ECC Support<br>+ Enable/disable ECC Support.<br>+ $EN_DIS<br>+ **/<br>+ UINT8 PcdEccSupport;<br>+<br>+ /** Offset 0x004C - HSUART Device<br>+ Select the PCI High Speed UART Device for Serial Port.<br>+ 0:HSUART0, 1:HSUART1, 2:HSUART2<br>+ **/<br>+ UINT8 PcdHsuartDevice;<br>+<br>+ /** Offset 0x004D - Memory Down<br>+ Enable/disable Memory Down function.<br>+ $EN_DIS<br>+ **/<br>+ UINT8 PcdMemoryDown;<br>+<br>+ /** Offset 0x004E<br>+ **/<br>+ UINT32 PcdMemoryDownConfigPtr;<br>+<br>+ /** Offset 0x0052 - SATA Controller 0<br>+ Enable/disable SATA Controller 0.<br>+ $EN_DIS<br>+ **/<br>+ UINT8 PcdEnableSATA0;<br>+<br>+ /** Offset 0x0053 - SATA Controller 1<br>+ Enable/disable SATA Controller 1.<br>+ $EN_DIS<br>+ **/<br>+ UINT8 PcdEnableSATA1;<br>+<br>+ /** Offset 0x0054 - Intel Quick Assist Technology<br>+ Enable/disable Intel Quick Assist Technology.<br>+ $EN_DIS<br>+ **/<br>+ UINT8 PcdEnableIQAT;<br>+<br>+ /** Offset 0x0055 - SPD Write Disable<br>+ Select SMBus SPD Write Enable State (Default: 0 = [FORCE_ENABLE], 1 =<br>+ [FORCE_DISABLE])<br>+ 0:Force Enable, 1:Force Disable<br>+ **/<br>+ UINT8 PcdSmbusSpdWriteDisable;<br>+<br>+ /** Offset 0x0056 - ME_SHUTDOWN Message<br>+ Enable/Disable sending ME_SHUTDOWN message to ME, refer to FSP<br>+ Integration Guide<br>+ for details.<br>+ $EN_DIS<br>+ **/<br>+ UINT8 PcdEnableMeShutdown;<br>+<br>+ /** Offset 0x0057 - XHCI Controller<br>+ Enable / Disable XHCI controller<br>+ $EN_DIS<br>+ **/<br>+ UINT8 PcdEnableXhci;<br>+<br>+ /** Offset 0x0058 - Memory Frequency<br>+ Set DDR Memory Frequency, refer to FSP Integration Guide for details.<br>+ 15:Auto, 3:1600, 4:1866, 5:2133, 6:2400<br>+ **/<br>+ UINT8 PcdDdrFreq;<br>+<br>+ /** Offset 0x0059 - MMIO Size<br>+ Set memory mapped IO space size<br>+ 0:2048M, 1:1024M, 2:3072M<br>+ **/<br>+ UINT8 PcdMmioSize;<br>+<br>+ /** Offset 0x005A - ME HECI Communication<br>+ Enable/Disable ME HECI communication<br>+ $EN_DIS<br>+ **/<br>+ UINT8 PcdMeHeciCommunication;<br>+<br>+ /** Offset 0x005B - HSIO Lanes Number<br>+ HSIO lanes number of SKU<br>+ 6:6, 8:8, 10:10, 12:12, 20:20<br>+ **/<br>+ UINT8 PcdHsioLanesNumber;<br>+<br>+ /** Offset 0x005C<br>+ **/<br>+ UINT32 PcdFiaMuxConfigPtr;<br>+<br>+ /** Offset 0x0060 - Customer Revision<br>+ The Customer can set this revision string for their own purpose.<br>+ **/<br>+ UINT8 PcdCustomerRevision[32];<br>+<br>+ /** Offset 0x0080 - 32-Bit bus mode<br>+ Enable/Disable 32-Bit bus memory mode.<br>+ $EN_DIS<br>+ **/<br>+ UINT8 PcdHalfWidthEnable;<br>+<br>+ /** Offset 0x0081 - TCL Performance<br>+ Enable/Disable Tcl timing for performance.<br>+ $EN_DIS<br>+ **/<br>+ UINT8 PcdTclIdle;<br>+<br>+ /** Offset 0x0082 - Interleave Mode<br>+ Select Interleave Mode<br>+ 0:DISABLED, 1:MODE0, 2:MODE1, 3:MODE2<br>+ **/<br>+ UINT8 PcdInterleaveMode;<br>+<br>+ /** Offset 0x0083 - Memory Thermal Throttling<br>+ Enable/disable Memory Thermal Throttling management mode<br>+ $EN_DIS<br>+ **/<br>+ UINT8 PcdMemoryThermalThrottling;<br>+<br>+ /** Offset 0x0084 - Memory Test<br>+ Enable / Disable Memory Test, refer to FSP Integration Guide for<br>+ details.<br>+ $EN_DIS<br>+ **/<br>+ UINT8 PcdSkipMemoryTest;<br>+<br>+ /** Offset 0x0085<br>+ **/<br>+ BL_MEMORY_SCRUB_SEGMENTS *PcdScrubSegmentPtr;<br>+<br>+ /** Offset 0x0089 - USB2 Port 1 OC Pin<br>+ Map selected OC pin to the port<br>+ 0:OC Pin 0, 8:No pin mapped<br>+ **/<br>+ UINT8 PcdUsb2Port1Pin;<br>+<br>+ /** Offset 0x008A - USB2 Port 2 OC Pin<br>+ Map selected OC pin to the port<br>+ 0:OC Pin 0, 8:No pin mapped<br>+ **/<br>+ UINT8 PcdUsb2Port2Pin;<br>+<br>+ /** Offset 0x008B - USB2 Port 3 OC Pin<br>+ Map selected OC pin to the port<br>+ 0:OC Pin 0, 8:No pin mapped<br>+ **/<br>+ UINT8 PcdUsb2Port3Pin;<br>+<br>+ /** Offset 0x008C - USB2 Port 4 OC Pin<br>+ Map selected OC pin to the port<br>+ 0:OC Pin 0, 8:No pin mapped<br>+ **/<br>+ UINT8 PcdUsb2Port4Pin;<br>+<br>+ /** Offset 0x008D - USB3 Port 1 OC Pin<br>+ Map selected OC pin to the port<br>+ 0:OC Pin 0, 8:No pin mapped<br>+ **/<br>+ UINT8 PcdUsb3Port1Pin;<br>+<br>+ /** Offset 0x008E - USB3 Port 2 OC Pin<br>+ Map selected OC pin to the port<br>+ 0:OC Pin 0, 8:No pin mapped<br>+ **/<br>+ UINT8 PcdUsb3Port2Pin;<br>+<br>+ /** Offset 0x008F - USB3 Port 3 OC Pin<br>+ Map selected OC pin to the port<br>+ 0:OC Pin 0, 8:No pin mapped<br>+ **/<br>+ UINT8 PcdUsb3Port3Pin;<br>+<br>+ /** Offset 0x0090 - USB3 Port 4 OC Pin<br>+ Map selected OC pin to the port<br>+ 0:OC Pin 0, 8:No pin mapped<br>+ **/<br>+ UINT8 PcdUsb3Port4Pin;<br>+<br>+ /** Offset 0x0091 - IOxAPIC 0-199<br>+ Enable/disable IOxAPIC 24-119 entries<br>+ $EN_DIS<br>+ **/<br>+ UINT8 PcdIOxAPIC0_199;<br>+<br>+ /** Offset 0x0092 - DMAP_X16<br>+ Enable/Disable DMAP_X16 dynamic MRC field indicating memory device<br>+ width is x16 or not<br>+ $EN_DIS<br>+ **/<br>+ UINT8 PcdDmapX16;<br>+<br>+ /** Offset 0x0093<br>+ **/<br>+ UINT8 UnusedUpdSpace0[333];<br>+<br>+ /** Offset 0x01E0<br>+ **/<br>+ UINT8 ReservedMemoryInitUpd[16];<br>+} FSP_M_CONFIG;<br>+<br>+/** Fsp M UPD Configuration<br>+**/<br>+typedef struct {<br>+<br>+ /** Offset 0x0000<br>+ **/<br>+ FSP_UPD_HEADER FspUpdHeader;<br>+<br>+ /** Offset 0x0020<br>+ **/<br>+ FSPM_ARCH_UPD FspmArchUpd;<br>+<br>+ /** Offset 0x0040<br>+ **/<br>+ FSP_M_CONFIG FspmConfig;<br>+<br>+ /** Offset 0x01F0<br>+ **/<br>+ UINT8 UnusedUpdSpace1[14];<br>+<br>+ /** Offset 0x01FE<br>+ **/<br>+ UINT16 UpdTerminator;<br>+} FSPM_UPD;<br>+<br>+#pragma pack(pop)<br>+<br>+#endif<br>diff --git a/src/vendorcode/intel/fsp/fsp2_0/denverton_ns/FspsUpd.h b/src/vendorcode/intel/fsp/fsp2_0/denverton_ns/FspsUpd.h<br>new file mode 100644<br>index 0000000..d861800<br>--- /dev/null<br>+++ b/src/vendorcode/intel/fsp/fsp2_0/denverton_ns/FspsUpd.h<br>@@ -0,0 +1,289 @@<br>+/** @file<br>+<br>+Copyright (c) 2017, Intel Corporation. All rights reserved.<BR><br>+<br>+Redistribution and use in source and binary forms, with or without modification,<br>+are permitted provided that the following conditions are met:<br>+<br>+* Redistributions of source code must retain the above copyright notice, this<br>+ list of conditions and the following disclaimer.<br>+* Redistributions in binary form must reproduce the above copyright notice, this<br>+ list of conditions and the following disclaimer in the documentation and/or<br>+ other materials provided with the distribution.<br>+* Neither the name of Intel Corporation nor the names of its contributors may<br>+ be used to endorse or promote products derived from this software without<br>+ specific prior written permission.<br>+<br>+ THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"<br>+ AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE<br>+ IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE<br>+ ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE<br>+ LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR<br>+ CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF<br>+ SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS<br>+ INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN<br>+ CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)<br>+ ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF<br>+ THE POSSIBILITY OF SUCH DAMAGE.<br>+<br>+ This file is automatically generated. Please do NOT modify !!!<br>+<br>+**/<br>+<br>+#ifndef __FSPSUPD_H__<br>+#define __FSPSUPD_H__<br>+<br>+#include <FspUpd.h><br>+<br>+#pragma pack(push, 1)<br>+<br>+/** Fsp S Configuration<br>+**/<br>+typedef struct {<br>+<br>+ /** Offset 0x0020 - PCIe Controller 0 Bifurcation<br>+ Configure PCI Express controller 0 bifurcation.<br>+ 0:X2X2X2X2, 1:X2X2X4, 2:X4X2X2, 3:X4X4, 4:X8<br>+ **/<br>+ UINT8 PcdBifurcationPcie0;<br>+<br>+ /** Offset 0x0021 - PCIe Controller 1 Bifurcation<br>+ Configure PCI Express controller 1 bifurcation.<br>+ 0:X2X2X2X2, 1:X2X2X4, 2:X4X2X2, 3:X4X4, 4:X8<br>+ **/<br>+ UINT8 PcdBifurcationPcie1;<br>+<br>+ /** Offset 0x0022 - Active Core Count<br>+ Select # of Active Cores (Default: 0, 0:ALL, 1..15 = 1..15 Cores)<br>+ 0:ALL, 1:1, 2:2, 3:3, 4:4, 5:5, 6:6, 7:7, 8:8, 9:9, 10:10, 11:11,<br>+ 12:12, 13:13,<br>+ 14:14, 15:15<br>+ **/<br>+ UINT8 PcdActiveCoreCount;<br>+<br>+ /** Offset 0x0023<br>+ **/<br>+ UINT32 PcdCpuMicrocodePatchBase;<br>+<br>+ /** Offset 0x0027<br>+ **/<br>+ UINT32 PcdCpuMicrocodePatchSize;<br>+<br>+ /** Offset 0x002B - PCIe Controller 0<br>+ Enable / Disable PCI Express controller 0<br>+ $EN_DIS<br>+ **/<br>+ UINT8 PcdEnablePcie0;<br>+<br>+ /** Offset 0x002C - PCIe Controller 1<br>+ Enable / Disable PCI Express controller 1<br>+ $EN_DIS<br>+ **/<br>+ UINT8 PcdEnablePcie1;<br>+<br>+ /** Offset 0x002D - Embedded Multi-Media Controller (eMMC)<br>+ Enable / Disable Embedded Multi-Media controller<br>+ $EN_DIS<br>+ **/<br>+ UINT8 PcdEnableEmmc;<br>+<br>+ /** Offset 0x002E - LAN Controllers<br>+ Enable / Disable LAN controllers, refer to FSP Integration Guide for<br>+ details.<br>+ 0:Disable LAN 0 & LAN 1, 1:Enable LAN 0 & LAN 1, 2:Disable LAN 1 only<br>+ **/<br>+ UINT8 PcdEnableGbE;<br>+<br>+ /** Offset 0x002F<br>+ **/<br>+ UINT32 PcdFiaMuxConfigRequestPtr;<br>+<br>+ /** Offset 0x0033<br>+ **/<br>+ UINT32 UnusedUpdSpace0;<br>+<br>+ /** Offset 0x0037 - PCIe Root Port 0 DeEmphasis<br>+ Desired DeEmphasis level for PCIE root port<br>+ 0:6dB, 1:3.5dB<br>+ **/<br>+ UINT8 PcdPcieRootPort0DeEmphasis;<br>+<br>+ /** Offset 0x0038 - PCIe Root Port 1 DeEmphasis<br>+ Desired DeEmphasis level for PCIE root port<br>+ 0:6dB, 1:3.5dB<br>+ **/<br>+ UINT8 PcdPcieRootPort1DeEmphasis;<br>+<br>+ /** Offset 0x0039 - PCIe Root Port 2 DeEmphasis<br>+ Desired DeEmphasis level for PCIE root port<br>+ 0:6dB, 1:3.5dB<br>+ **/<br>+ UINT8 PcdPcieRootPort2DeEmphasis;<br>+<br>+ /** Offset 0x003A - PCIe Root Port 3 DeEmphasis<br>+ Desired DeEmphasis level for PCIE root port<br>+ 0:6dB, 1:3.5dB<br>+ **/<br>+ UINT8 PcdPcieRootPort3DeEmphasis;<br>+<br>+ /** Offset 0x003B - PCIe Root Port 4 DeEmphasis<br>+ Desired DeEmphasis level for PCIE root port<br>+ 0:6dB, 1:3.5dB<br>+ **/<br>+ UINT8 PcdPcieRootPort4DeEmphasis;<br>+<br>+ /** Offset 0x003C - PCIe Root Port 5 DeEmphasis<br>+ Desired DeEmphasis level for PCIE root port<br>+ 0:6dB, 1:3.5dB<br>+ **/<br>+ UINT8 PcdPcieRootPort5DeEmphasis;<br>+<br>+ /** Offset 0x003D - PCIe Root Port 6 DeEmphasis<br>+ Desired DeEmphasis level for PCIE root port<br>+ 0:6dB, 1:3.5dB<br>+ **/<br>+ UINT8 PcdPcieRootPort6DeEmphasis;<br>+<br>+ /** Offset 0x003E - PCIe Root Port 7 DeEmphasis<br>+ Desired DeEmphasis level for PCIE root port<br>+ 0:6dB, 1:3.5dB<br>+ **/<br>+ UINT8 PcdPcieRootPort7DeEmphasis;<br>+<br>+ /** Offset 0x003F<br>+ **/<br>+ UINT8 UnusedUpdSpace1;<br>+<br>+ /** Offset 0x0040<br>+ **/<br>+ UINT32 PcdEMMCDLLConfigPtr;<br>+<br>+ /** Offset 0x0044 - PCIe Root Port 0 Link Speed<br>+ Upper limit on link operational speed for PCI Express RootPort<br>+ 1:GEN1, 2:GEN2, 3:GEN3<br>+ **/<br>+ UINT8 PcdPcieRootPort0LinkSpeed;<br>+<br>+ /** Offset 0x0045 - PCIe Root Port 1 Link Speed<br>+ Upper limit on link operational speed for PCI Express RootPort<br>+ 1:GEN1, 2:GEN2, 3:GEN3<br>+ **/<br>+ UINT8 PcdPcieRootPort1LinkSpeed;<br>+<br>+ /** Offset 0x0046 - PCIe Root Port 2 Link Speed<br>+ Upper limit on link operational speed for PCI Express RootPort<br>+ 1:GEN1, 2:GEN2, 3:GEN3<br>+ **/<br>+ UINT8 PcdPcieRootPort2LinkSpeed;<br>+<br>+ /** Offset 0x0047 - PCIe Root Port 3 Link Speed<br>+ Upper limit on link operational speed for PCI Express RootPort<br>+ 1:GEN1, 2:GEN2, 3:GEN3<br>+ **/<br>+ UINT8 PcdPcieRootPort3LinkSpeed;<br>+<br>+ /** Offset 0x0048 - PCIe Root Port 4 Link Speed<br>+ Upper limit on link operational speed for PCI Express RootPort<br>+ 1:GEN1, 2:GEN2, 3:GEN3<br>+ **/<br>+ UINT8 PcdPcieRootPort4LinkSpeed;<br>+<br>+ /** Offset 0x0049 - PCIe Root Port 5 Link Speed<br>+ Upper limit on link operational speed for PCI Express RootPort<br>+ 1:GEN1, 2:GEN2, 3:GEN3<br>+ **/<br>+ UINT8 PcdPcieRootPort5LinkSpeed;<br>+<br>+ /** Offset 0x004A - PCIe Root Port 6 Link Speed<br>+ Upper limit on link operational speed for PCI Express RootPort<br>+ 1:GEN1, 2:GEN2, 3:GEN3<br>+ **/<br>+ UINT8 PcdPcieRootPort6LinkSpeed;<br>+<br>+ /** Offset 0x004B - PCIe Root Port 7 Link Speed<br>+ Upper limit on link operational speed for PCI Express RootPort<br>+ 1:GEN1, 2:GEN2, 3:GEN3<br>+ **/<br>+ UINT8 PcdPcieRootPort7LinkSpeed;<br>+<br>+ /** Offset 0x004C - PCIe Root Port 0 ASPM<br>+ Enable PCI Express Active State Power Management settings<br>+ 0:Disabled, 2:L1<br>+ **/<br>+ UINT8 PcdPcieRootPort0Aspm;<br>+<br>+ /** Offset 0x004D - PCIe Root Port 1 ASPM<br>+ Enable PCI Express Active State Power Management settings<br>+ 0:Disabled, 2:L1<br>+ **/<br>+ UINT8 PcdPcieRootPort1Aspm;<br>+<br>+ /** Offset 0x004E - PCIe Root Port 2 ASPM<br>+ Enable PCI Express Active State Power Management settings<br>+ 0:Disabled, 2:L1<br>+ **/<br>+ UINT8 PcdPcieRootPort2Aspm;<br>+<br>+ /** Offset 0x004F - PCIe Root Port 3 ASPM<br>+ Enable PCI Express Active State Power Management settings<br>+ 0:Disabled, 2:L1<br>+ **/<br>+ UINT8 PcdPcieRootPort3Aspm;<br>+<br>+ /** Offset 0x0050 - PCIe Root Port 4 ASPM<br>+ Enable PCI Express Active State Power Management settings<br>+ 0:Disabled, 2:L1<br>+ **/<br>+ UINT8 PcdPcieRootPort4Aspm;<br>+<br>+ /** Offset 0x0051 - PCIe Root Port 5 ASPM<br>+ Enable PCI Express Active State Power Management settings<br>+ 0:Disabled, 2:L1<br>+ **/<br>+ UINT8 PcdPcieRootPort5Aspm;<br>+<br>+ /** Offset 0x0052 - PCIe Root Port 6 ASPM<br>+ Enable PCI Express Active State Power Management settings<br>+ 0:Disabled, 2:L1<br>+ **/<br>+ UINT8 PcdPcieRootPort6Aspm;<br>+<br>+ /** Offset 0x0053 - PCIe Root Port 7 ASPM<br>+ Enable PCI Express Active State Power Management settings<br>+ 0:Disabled, 2:L1<br>+ **/<br>+ UINT8 PcdPcieRootPort7Aspm;<br>+<br>+ /** Offset 0x0054<br>+ **/<br>+ UINT8 UnusedUpdSpace2[140];<br>+<br>+ /** Offset 0x00E0<br>+ **/<br>+ UINT8 ReservedSiliconInitUpd[16];<br>+} FSP_S_CONFIG;<br>+<br>+/** Fsp S UPD Configuration<br>+**/<br>+typedef struct {<br>+<br>+ /** Offset 0x0000<br>+ **/<br>+ FSP_UPD_HEADER FspUpdHeader;<br>+<br>+ /** Offset 0x0020<br>+ **/<br>+ FSP_S_CONFIG FspsConfig;<br>+<br>+ /** Offset 0x00F0<br>+ **/<br>+ UINT8 UnusedUpdSpace3[14];<br>+<br>+ /** Offset 0x00FE<br>+ **/<br>+ UINT16 UpdTerminator;<br>+} FSPS_UPD;<br>+<br>+#pragma pack(pop)<br>+<br>+#endif<br>diff --git a/src/vendorcode/intel/fsp/fsp2_0/denverton_ns/FsptUpd.h b/src/vendorcode/intel/fsp/fsp2_0/denverton_ns/FsptUpd.h<br>new file mode 100644<br>index 0000000..cca90f0<br>--- /dev/null<br>+++ b/src/vendorcode/intel/fsp/fsp2_0/denverton_ns/FsptUpd.h<br>@@ -0,0 +1,109 @@<br>+/** @file<br>+<br>+Copyright (c) 2017, Intel Corporation. All rights reserved.<BR><br>+<br>+Redistribution and use in source and binary forms, with or without modification,<br>+are permitted provided that the following conditions are met:<br>+<br>+* Redistributions of source code must retain the above copyright notice, this<br>+ list of conditions and the following disclaimer.<br>+* Redistributions in binary form must reproduce the above copyright notice, this<br>+ list of conditions and the following disclaimer in the documentation and/or<br>+ other materials provided with the distribution.<br>+* Neither the name of Intel Corporation nor the names of its contributors may<br>+ be used to endorse or promote products derived from this software without<br>+ specific prior written permission.<br>+<br>+ THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"<br>+ AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE<br>+ IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE<br>+ ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE<br>+ LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR<br>+ CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF<br>+ SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS<br>+ INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN<br>+ CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)<br>+ ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF<br>+ THE POSSIBILITY OF SUCH DAMAGE.<br>+<br>+ This file is automatically generated. Please do NOT modify !!!<br>+<br>+**/<br>+<br>+#ifndef __FSPTUPD_H__<br>+#define __FSPTUPD_H__<br>+<br>+#include <FspUpd.h><br>+<br>+#pragma pack(push, 1)<br>+<br>+/** Fsp T Core UPD<br>+**/<br>+typedef struct {<br>+<br>+ /** Offset 0x0020<br>+ **/<br>+ UINT32 MicrocodeRegionBase;<br>+<br>+ /** Offset 0x0024<br>+ **/<br>+ UINT32 MicrocodeRegionLength;<br>+<br>+ /** Offset 0x0028<br>+ **/<br>+ UINT32 CodeRegionBase;<br>+<br>+ /** Offset 0x002C<br>+ **/<br>+ UINT32 CodeRegionLength;<br>+<br>+ /** Offset 0x0030<br>+ **/<br>+ UINT8 Reserved1[16];<br>+} FSPT_CORE_UPD;<br>+<br>+/** Fsp T Configuration<br>+**/<br>+typedef struct {<br>+<br>+ /** Offset 0x0040 - Disable Port80 output in FSP-T<br>+ Select Port80 Control in FSP-T (0:VPD-Style, 1:Enable Port80 Output,<br>+ 2:Disable Port80<br>+ Output, refer to FSP Integration Guide for details<br>+ 0:VPD-Style, 1:Enable Port80 Output[Default], 2:Disable Port80 Output<br>+ **/<br>+ UINT8 PcdFsptPort80RouteDisable;<br>+<br>+ /** Offset 0x0041<br>+ **/<br>+ UINT8 ReservedTempRamInitUpd[31];<br>+} FSPT_CONFIG;<br>+<br>+/** Fsp T UPD Configuration<br>+**/<br>+typedef struct {<br>+<br>+ /** Offset 0x0000<br>+ **/<br>+ FSP_UPD_HEADER FspUpdHeader;<br>+<br>+ /** Offset 0x0020<br>+ **/<br>+ FSPT_CORE_UPD FsptCoreUpd;<br>+<br>+ /** Offset 0x0040<br>+ **/<br>+ FSPT_CONFIG FsptConfig;<br>+<br>+ /** Offset 0x0060<br>+ **/<br>+ UINT8 UnusedUpdSpace0[30];<br>+<br>+ /** Offset 0x007E<br>+ **/<br>+ UINT16 UpdTerminator;<br>+} FSPT_UPD;<br>+<br>+#pragma pack(pop)<br>+<br>+#endif<br></pre><p>To view, visit <a href="https://review.coreboot.org/20805">change 20805</a>. To unsubscribe, visit <a href="https://review.coreboot.org/settings">settings</a>.</p><div itemscope itemtype="http://schema.org/EmailMessage"><div itemscope itemprop="action" itemtype="http://schema.org/ViewAction"><link itemprop="url" href="https://review.coreboot.org/20805"/><meta itemprop="name" content="View Change"/></div></div>
<div style="display:none"> Gerrit-Project: coreboot </div>
<div style="display:none"> Gerrit-Branch: master </div>
<div style="display:none"> Gerrit-MessageType: newchange </div>
<div style="display:none"> Gerrit-Change-Id: I9672610df09089c549e74072345781bea0b4d06f </div>
<div style="display:none"> Gerrit-Change-Number: 20805 </div>
<div style="display:none"> Gerrit-PatchSet: 1 </div>
<div style="display:none"> Gerrit-Owner: Mariusz Szafranski </div>