<p>Iru Cai has uploaded this change for <strong>review</strong>.</p><p><a href="https://review.coreboot.org/20779">View Change</a></p><pre style="font-family: monospace,monospace; white-space: pre-wrap;">mainboard/hp: Add HP Elitebook 2760p<br><br>The code is generated by autoport.<br><br>The flash chip is socketed beside the WLAN slot. The EHCI debug port<br>is on right side of the laptop beside the RJ11 connector.<br><br>Things that work:<br>- memory: 0+8G, 4G+8G<br>- Linux (Linux Mint 18.1 with Linux 4.4)<br>- native graphics init + SeaBIOS payload with SeaVGABIOS<br>- all 3 USB ports<br>- WLAN<br>- WWAN<br>- expresscard<br>- S3 suspend and resume<br>- internal flashing after IFD is unlocked and coreboot is flashed<br>- keyboard, trackpoint and touchpad<br>- fan control<br>- AC and battery status<br><br>Issues:<br>- Wacom digitizer does not work (even after I add it in DSDT)<br>- GRUB payload will freeze (including chainloading GRUB from SeaBIOS)<br><br>Things that are not tested:<br>- SD card reader<br>- smart card reader<br>- cable modem<br><br>(EC) blobs:<br><br>This laptop uses SMSC KBC1126-NU as EC. It needs two blobs in the<br>flash chip. You can use the tools in util/kbc1126 to extract them<br>from OEM firmware, and use the following configuration to insert<br>them to coreboot image:<br><br> -> Chipset<br> -> Add firmware images for KBC1126 firmware<br><br>Change-Id: I2d0fb1c3f8214aecea17e3a111932d7df8bc4af1<br>Signed-off-by: Iru Cai <mytbk920423@gmail.com><br>---<br>A src/mainboard/hp/2760p/Kconfig<br>A src/mainboard/hp/2760p/Kconfig.name<br>A src/mainboard/hp/2760p/Makefile.inc<br>A src/mainboard/hp/2760p/board_info.txt<br>A src/mainboard/hp/2760p/devicetree.cb<br>A src/mainboard/hp/2760p/gpio.c<br>A src/mainboard/hp/2760p/hda_verb.c<br>A src/mainboard/hp/2760p/romstage.c<br>8 files changed, 551 insertions(+), 0 deletions(-)<br><br></pre><pre style="font-family: monospace,monospace; white-space: pre-wrap;">git pull ssh://review.coreboot.org:29418/coreboot refs/changes/79/20779/1</pre><pre style="font-family: monospace,monospace; white-space: pre-wrap;">diff --git a/src/mainboard/hp/2760p/Kconfig b/src/mainboard/hp/2760p/Kconfig<br>new file mode 100644<br>index 0000000..c3dd5f9<br>--- /dev/null<br>+++ b/src/mainboard/hp/2760p/Kconfig<br>@@ -0,0 +1,39 @@<br>+if BOARD_HP_2760P<br>+<br>+config BOARD_SPECIFIC_OPTIONS # dummy<br>+ def_bool y<br>+ select HP_ELITEBOOK_SNB_IVB<br>+ select BOARD_ROMSIZE_KB_8192<br>+ select CPU_INTEL_SOCKET_RPGA989<br>+ select NORTHBRIDGE_INTEL_SANDYBRIDGE<br>+ select SOUTHBRIDGE_INTEL_BD82X6X<br>+<br>+config DEVICETREE<br>+ string<br>+ default ../2760p/devicetree.cb<br>+<br>+config MAINBOARD_PART_NUMBER<br>+ string<br>+ default "EliteBook 2760p"<br>+<br>+config VGA_BIOS_FILE<br>+ string<br>+ default "pci8086,0116.rom"<br>+<br>+config VGA_BIOS_ID<br>+ string<br>+ default "8086,0116"<br>+<br>+config MAINBOARD_PCI_SUBSYSTEM_DEVICE_ID<br>+ hex<br>+ default 0x162a<br>+<br>+config MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID<br>+ hex<br>+ default 0x103c<br>+<br>+config USBDEBUG_HCD_INDEX<br>+ int<br>+ default 1<br>+<br>+endif<br>diff --git a/src/mainboard/hp/2760p/Kconfig.name b/src/mainboard/hp/2760p/Kconfig.name<br>new file mode 100644<br>index 0000000..a0dfe41<br>--- /dev/null<br>+++ b/src/mainboard/hp/2760p/Kconfig.name<br>@@ -0,0 +1,2 @@<br>+config BOARD_HP_2760P<br>+ bool "EliteBook 2760p"<br>diff --git a/src/mainboard/hp/2760p/Makefile.inc b/src/mainboard/hp/2760p/Makefile.inc<br>new file mode 100644<br>index 0000000..8bb3cd6<br>--- /dev/null<br>+++ b/src/mainboard/hp/2760p/Makefile.inc<br>@@ -0,0 +1,4 @@<br>+romstage-y += romstage.c<br>+romstage-y += gpio.c<br>+<br>+ramstage-y += hda_verb.c<br>diff --git a/src/mainboard/hp/2760p/board_info.txt b/src/mainboard/hp/2760p/board_info.txt<br>new file mode 100644<br>index 0000000..312086b<br>--- /dev/null<br>+++ b/src/mainboard/hp/2760p/board_info.txt<br>@@ -0,0 +1,7 @@<br>+Category: laptop<br>+Board URL: https://support.hp.com/us-en/product/hp-elitebook-2760p-tablet-pc/5071191<br>+ROM protocol: SPI<br>+ROM package: SOIC-8<br>+ROM socketed: y<br>+Flashrom support: n<br>+Release year: 2011<br>diff --git a/src/mainboard/hp/2760p/devicetree.cb b/src/mainboard/hp/2760p/devicetree.cb<br>new file mode 100644<br>index 0000000..2f9e363<br>--- /dev/null<br>+++ b/src/mainboard/hp/2760p/devicetree.cb<br>@@ -0,0 +1,139 @@<br>+#<br>+# This file is part of the coreboot project.<br>+#<br>+# Copyright (C) 2017 Iru Cai <mytbk920423@gmail.com><br>+#<br>+# This program is free software; you can redistribute it and/or modify<br>+# it under the terms of the GNU General Public License as published by<br>+# the Free Software Foundation; either version 2 of the License, or<br>+# (at your option) any later version.<br>+#<br>+# This program is distributed in the hope that it will be useful,<br>+# but WITHOUT ANY WARRANTY; without even the implied warranty of<br>+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the<br>+# GNU General Public License for more details.<br>+#<br>+<br>+chip northbridge/intel/sandybridge # FIXME: check gfx.ndid and gfx.did<br>+ register "gfx.did" = "{ 0x80000100, 0x80000240, 0x80000410, 0x80000410, 0x00000005 }"<br>+ register "gfx.link_frequency_270_mhz" = "1"<br>+ register "gfx.ndid" = "3"<br>+ register "gfx.use_spread_spectrum_clock" = "1"<br>+ register "gpu_cpu_backlight" = "0x00000129"<br>+ register "gpu_dp_b_hotplug" = "4"<br>+ register "gpu_dp_c_hotplug" = "4"<br>+ register "gpu_dp_d_hotplug" = "4"<br>+ register "gpu_panel_port_select" = "0"<br>+ register "gpu_panel_power_backlight_off_delay" = "2000"<br>+ register "gpu_panel_power_backlight_on_delay" = "2000"<br>+ register "gpu_panel_power_cycle_delay" = "5"<br>+ register "gpu_panel_power_down_delay" = "230"<br>+ register "gpu_panel_power_up_delay" = "300"<br>+ register "gpu_pch_backlight" = "0x02880288"<br>+ device cpu_cluster 0x0 on<br>+ chip cpu/intel/socket_rPGA989<br>+ device lapic 0x0 on<br>+ end<br>+ end<br>+ chip cpu/intel/model_206ax # FIXME: check all registers<br>+ register "c1_acpower" = "1"<br>+ register "c1_battery" = "1"<br>+ register "c2_acpower" = "3"<br>+ register "c2_battery" = "3"<br>+ register "c3_acpower" = "5"<br>+ register "c3_battery" = "5"<br>+ device lapic 0xacac off<br>+ end<br>+ end<br>+ end<br>+ device domain 0x0 on<br>+ device pci 00.0 on # Host bridge Host bridge<br>+ subsystemid 0x103c 0x162a<br>+ end<br>+ device pci 01.0 off # PCIe Bridge for discrete graphics<br>+ end<br>+ device pci 02.0 on # Internal graphics VGA controller<br>+ subsystemid 0x103c 0x162a<br>+ end<br>+<br>+ chip southbridge/intel/bd82x6x # Intel Series 6 Cougar Point PCH<br>+ register "c2_latency" = "0x0065"<br>+ register "docking_supported" = "0"<br>+ register "gen1_dec" = "0x007c0201"<br>+ register "gen2_dec" = "0x000c0101"<br>+ register "gen3_dec" = "0x00fcfe01"<br>+ register "gen4_dec" = "0x007c0281"<br>+ register "gpi6_routing" = "2"<br>+ register "p_cnt_throttling_supported" = "1"<br>+ register "pcie_hotplug_map" = "{ 0, 0, 1, 0, 0, 0, 0, 0 }"<br>+ register "pcie_port_coalesce" = "1"<br>+ register "sata_interface_speed_support" = "0x3"<br>+ register "sata_port_map" = "0x21"<br>+<br>+ register "spi_uvscc" = "0x2005"<br>+ register "spi_lvscc" = "0"<br>+<br>+ device pci 16.0 on # Management Engine Interface 1<br>+ subsystemid 0x103c 0x162a<br>+ end<br>+ device pci 16.1 off # Management Engine Interface 2<br>+ end<br>+ device pci 16.2 off # Management Engine IDE-R<br>+ end<br>+ device pci 16.3 off # Management Engine KT<br>+ end<br>+ device pci 19.0 on # Intel Gigabit Ethernet<br>+ subsystemid 0x103c 0x162a<br>+ end<br>+ device pci 1a.0 on # USB2 EHCI #2<br>+ subsystemid 0x103c 0x162a<br>+ end<br>+ device pci 1b.0 on # High Definition Audio Audio controller<br>+ subsystemid 0x103c 0x162a<br>+ end<br>+ device pci 1c.0 on # PCIe Port #1<br>+ subsystemid 0x103c 0x162a<br>+ end<br>+ device pci 1c.1 on # PCIe Port #2<br>+ subsystemid 0x103c 0x162a<br>+ end<br>+ device pci 1c.2 on # PCIe Port #3<br>+ subsystemid 0x103c 0x162a<br>+ end<br>+ device pci 1c.3 on # WLAN<br>+ end<br>+ device pci 1c.4 off # PCIe Port #5<br>+ end<br>+ device pci 1c.5 off # PCIe Port #6<br>+ end<br>+ device pci 1c.6 off # PCIe Port #7<br>+ end<br>+ device pci 1c.7 off # PCIe Port #8<br>+ end<br>+ device pci 1d.0 on # USB2 EHCI #1<br>+ subsystemid 0x103c 0x162a<br>+ end<br>+ device pci 1e.0 off # PCI bridge<br>+ end<br>+ device pci 1f.0 on # LPC bridge PCI-LPC bridge<br>+ subsystemid 0x103c 0x162a<br>+ chip ec/hp/kbc1126<br>+ register "ec_data_port" = "0x60"<br>+ register "ec_cmd_port" = "0x64"<br>+ register "ec_ctrl_reg" = "0xca"<br>+ register "ec_fan_ctrl_value" = "0x4d"<br>+ device pnp ff.1 off end<br>+ end # kbc1126<br>+ end<br>+ device pci 1f.2 on # SATA Controller 1<br>+ subsystemid 0x103c 0x162a<br>+ end<br>+ device pci 1f.3 off # SMBus<br>+ end<br>+ device pci 1f.5 off # SATA Controller 2<br>+ end<br>+ device pci 1f.6 off # Thermal<br>+ end<br>+ end<br>+ end<br>+end<br>diff --git a/src/mainboard/hp/2760p/gpio.c b/src/mainboard/hp/2760p/gpio.c<br>new file mode 100644<br>index 0000000..6ad2c9c<br>--- /dev/null<br>+++ b/src/mainboard/hp/2760p/gpio.c<br>@@ -0,0 +1,245 @@<br>+/*<br>+ * This file is part of the coreboot project.<br>+ *<br>+ * Copyright (C) 2017 Iru Cai <mytbk920423@gmail.com><br>+ *<br>+ * This program is free software; you can redistribute it and/or<br>+ * modify it under the terms of the GNU General Public License as<br>+ * published by the Free Software Foundation; version 2 of the License.<br>+ *<br>+ * This program is distributed in the hope that it will be useful,<br>+ * but WITHOUT ANY WARRANTY; without even the implied warranty of<br>+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the<br>+ * GNU General Public License for more details.<br>+ */<br>+<br>+#include <southbridge/intel/common/gpio.h><br>+<br>+const struct pch_gpio_set1 pch_gpio_set1_mode = {<br>+ .gpio0 = GPIO_MODE_GPIO,<br>+ .gpio1 = GPIO_MODE_GPIO,<br>+ .gpio2 = GPIO_MODE_GPIO,<br>+ .gpio3 = GPIO_MODE_GPIO,<br>+ .gpio4 = GPIO_MODE_GPIO,<br>+ .gpio5 = GPIO_MODE_NATIVE,<br>+ .gpio6 = GPIO_MODE_GPIO,<br>+ .gpio7 = GPIO_MODE_GPIO,<br>+ .gpio8 = GPIO_MODE_GPIO,<br>+ .gpio9 = GPIO_MODE_NATIVE,<br>+ .gpio10 = GPIO_MODE_GPIO,<br>+ .gpio11 = GPIO_MODE_GPIO,<br>+ .gpio12 = GPIO_MODE_NATIVE,<br>+ .gpio13 = GPIO_MODE_GPIO,<br>+ .gpio14 = GPIO_MODE_GPIO,<br>+ .gpio15 = GPIO_MODE_GPIO,<br>+ .gpio16 = GPIO_MODE_GPIO,<br>+ .gpio17 = GPIO_MODE_GPIO,<br>+ .gpio18 = GPIO_MODE_NATIVE,<br>+ .gpio19 = GPIO_MODE_NATIVE,<br>+ .gpio20 = GPIO_MODE_NATIVE,<br>+ .gpio21 = GPIO_MODE_GPIO,<br>+ .gpio22 = GPIO_MODE_GPIO,<br>+ .gpio23 = GPIO_MODE_GPIO,<br>+ .gpio24 = GPIO_MODE_GPIO,<br>+ .gpio25 = GPIO_MODE_NATIVE,<br>+ .gpio26 = GPIO_MODE_NATIVE,<br>+ .gpio27 = GPIO_MODE_GPIO,<br>+ .gpio28 = GPIO_MODE_GPIO,<br>+ .gpio29 = GPIO_MODE_GPIO,<br>+ .gpio30 = GPIO_MODE_NATIVE,<br>+ .gpio31 = GPIO_MODE_NATIVE,<br>+};<br>+<br>+const struct pch_gpio_set1 pch_gpio_set1_direction = {<br>+ .gpio0 = GPIO_DIR_OUTPUT,<br>+ .gpio1 = GPIO_DIR_INPUT,<br>+ .gpio2 = GPIO_DIR_INPUT,<br>+ .gpio3 = GPIO_DIR_INPUT,<br>+ .gpio4 = GPIO_DIR_INPUT,<br>+ .gpio6 = GPIO_DIR_INPUT,<br>+ .gpio7 = GPIO_DIR_INPUT,<br>+ .gpio8 = GPIO_DIR_INPUT,<br>+ .gpio10 = GPIO_DIR_INPUT,<br>+ .gpio11 = GPIO_DIR_OUTPUT,<br>+ .gpio13 = GPIO_DIR_INPUT,<br>+ .gpio14 = GPIO_DIR_INPUT,<br>+ .gpio15 = GPIO_DIR_INPUT,<br>+ .gpio16 = GPIO_DIR_INPUT,<br>+ .gpio17 = GPIO_DIR_OUTPUT,<br>+ .gpio21 = GPIO_DIR_INPUT,<br>+ .gpio22 = GPIO_DIR_OUTPUT,<br>+ .gpio23 = GPIO_DIR_INPUT,<br>+ .gpio24 = GPIO_DIR_OUTPUT,<br>+ .gpio27 = GPIO_DIR_OUTPUT,<br>+ .gpio28 = GPIO_DIR_OUTPUT,<br>+ .gpio29 = GPIO_DIR_OUTPUT,<br>+};<br>+<br>+const struct pch_gpio_set1 pch_gpio_set1_level = {<br>+ .gpio0 = GPIO_LEVEL_LOW,<br>+ .gpio11 = GPIO_LEVEL_LOW,<br>+ .gpio17 = GPIO_LEVEL_HIGH,<br>+ .gpio22 = GPIO_LEVEL_HIGH,<br>+ .gpio24 = GPIO_LEVEL_HIGH,<br>+ .gpio27 = GPIO_LEVEL_LOW,<br>+ .gpio28 = GPIO_LEVEL_LOW,<br>+ .gpio29 = GPIO_LEVEL_HIGH,<br>+};<br>+<br>+const struct pch_gpio_set1 pch_gpio_set1_reset = {<br>+ .gpio24 = GPIO_RESET_RSMRST,<br>+ .gpio30 = GPIO_RESET_RSMRST,<br>+};<br>+<br>+const struct pch_gpio_set1 pch_gpio_set1_invert = {<br>+ .gpio1 = GPIO_INVERT,<br>+ .gpio2 = GPIO_NO_INVERT,<br>+ .gpio3 = GPIO_INVERT,<br>+ .gpio4 = GPIO_NO_INVERT,<br>+ .gpio6 = GPIO_INVERT,<br>+ .gpio7 = GPIO_INVERT,<br>+ .gpio8 = GPIO_NO_INVERT,<br>+ .gpio10 = GPIO_INVERT,<br>+ .gpio13 = GPIO_INVERT,<br>+ .gpio14 = GPIO_INVERT,<br>+ .gpio15 = GPIO_NO_INVERT,<br>+ .gpio16 = GPIO_NO_INVERT,<br>+ .gpio21 = GPIO_NO_INVERT,<br>+ .gpio23 = GPIO_NO_INVERT,<br>+};<br>+<br>+const struct pch_gpio_set1 pch_gpio_set1_blink = {<br>+};<br>+<br>+const struct pch_gpio_set2 pch_gpio_set2_mode = {<br>+ .gpio32 = GPIO_MODE_NATIVE,<br>+ .gpio33 = GPIO_MODE_GPIO,<br>+ .gpio34 = GPIO_MODE_GPIO,<br>+ .gpio35 = GPIO_MODE_GPIO,<br>+ .gpio36 = GPIO_MODE_GPIO,<br>+ .gpio37 = GPIO_MODE_GPIO,<br>+ .gpio38 = GPIO_MODE_GPIO,<br>+ .gpio39 = GPIO_MODE_GPIO,<br>+ .gpio40 = GPIO_MODE_NATIVE,<br>+ .gpio41 = GPIO_MODE_NATIVE,<br>+ .gpio42 = GPIO_MODE_NATIVE,<br>+ .gpio43 = GPIO_MODE_NATIVE,<br>+ .gpio44 = GPIO_MODE_GPIO,<br>+ .gpio45 = GPIO_MODE_NATIVE,<br>+ .gpio46 = GPIO_MODE_GPIO,<br>+ .gpio47 = GPIO_MODE_NATIVE,<br>+ .gpio48 = GPIO_MODE_GPIO,<br>+ .gpio49 = GPIO_MODE_GPIO,<br>+ .gpio50 = GPIO_MODE_GPIO,<br>+ .gpio51 = GPIO_MODE_GPIO,<br>+ .gpio52 = GPIO_MODE_GPIO,<br>+ .gpio53 = GPIO_MODE_GPIO,<br>+ .gpio54 = GPIO_MODE_GPIO,<br>+ .gpio55 = GPIO_MODE_GPIO,<br>+ .gpio56 = GPIO_MODE_NATIVE,<br>+ .gpio57 = GPIO_MODE_GPIO,<br>+ .gpio58 = GPIO_MODE_NATIVE,<br>+ .gpio59 = GPIO_MODE_NATIVE,<br>+ .gpio60 = GPIO_MODE_GPIO,<br>+ .gpio61 = GPIO_MODE_GPIO,<br>+ .gpio62 = GPIO_MODE_NATIVE,<br>+ .gpio63 = GPIO_MODE_NATIVE,<br>+};<br>+<br>+const struct pch_gpio_set2 pch_gpio_set2_direction = {<br>+ .gpio33 = GPIO_DIR_OUTPUT,<br>+ .gpio34 = GPIO_DIR_INPUT,<br>+ .gpio35 = GPIO_DIR_OUTPUT,<br>+ .gpio36 = GPIO_DIR_OUTPUT,<br>+ .gpio37 = GPIO_DIR_OUTPUT,<br>+ .gpio38 = GPIO_DIR_INPUT,<br>+ .gpio39 = GPIO_DIR_INPUT,<br>+ .gpio44 = GPIO_DIR_INPUT,<br>+ .gpio46 = GPIO_DIR_INPUT,<br>+ .gpio48 = GPIO_DIR_INPUT,<br>+ .gpio49 = GPIO_DIR_OUTPUT,<br>+ .gpio50 = GPIO_DIR_INPUT,<br>+ .gpio51 = GPIO_DIR_INPUT,<br>+ .gpio52 = GPIO_DIR_INPUT,<br>+ .gpio53 = GPIO_DIR_OUTPUT,<br>+ .gpio54 = GPIO_DIR_OUTPUT,<br>+ .gpio55 = GPIO_DIR_OUTPUT,<br>+ .gpio57 = GPIO_DIR_OUTPUT,<br>+ .gpio60 = GPIO_DIR_OUTPUT,<br>+ .gpio61 = GPIO_DIR_OUTPUT,<br>+};<br>+<br>+const struct pch_gpio_set2 pch_gpio_set2_level = {<br>+ .gpio33 = GPIO_LEVEL_LOW,<br>+ .gpio35 = GPIO_LEVEL_LOW,<br>+ .gpio36 = GPIO_LEVEL_LOW,<br>+ .gpio37 = GPIO_LEVEL_LOW,<br>+ .gpio49 = GPIO_LEVEL_LOW,<br>+ .gpio53 = GPIO_LEVEL_HIGH,<br>+ .gpio54 = GPIO_LEVEL_HIGH,<br>+ .gpio55 = GPIO_LEVEL_LOW,<br>+ .gpio57 = GPIO_LEVEL_HIGH,<br>+ .gpio60 = GPIO_LEVEL_HIGH,<br>+ .gpio61 = GPIO_LEVEL_HIGH,<br>+};<br>+<br>+const struct pch_gpio_set2 pch_gpio_set2_reset = {<br>+};<br>+<br>+const struct pch_gpio_set3 pch_gpio_set3_mode = {<br>+ .gpio64 = GPIO_MODE_NATIVE,<br>+ .gpio65 = GPIO_MODE_NATIVE,<br>+ .gpio66 = GPIO_MODE_NATIVE,<br>+ .gpio67 = GPIO_MODE_NATIVE,<br>+ .gpio68 = GPIO_MODE_GPIO,<br>+ .gpio69 = GPIO_MODE_GPIO,<br>+ .gpio70 = GPIO_MODE_GPIO,<br>+ .gpio71 = GPIO_MODE_NATIVE,<br>+ .gpio72 = GPIO_MODE_GPIO,<br>+ .gpio73 = GPIO_MODE_GPIO,<br>+ .gpio74 = GPIO_MODE_GPIO,<br>+ .gpio75 = GPIO_MODE_NATIVE,<br>+};<br>+<br>+const struct pch_gpio_set3 pch_gpio_set3_direction = {<br>+ .gpio68 = GPIO_DIR_OUTPUT,<br>+ .gpio69 = GPIO_DIR_INPUT,<br>+ .gpio70 = GPIO_DIR_OUTPUT,<br>+ .gpio72 = GPIO_DIR_OUTPUT,<br>+ .gpio73 = GPIO_DIR_OUTPUT,<br>+ .gpio74 = GPIO_DIR_OUTPUT,<br>+};<br>+<br>+const struct pch_gpio_set3 pch_gpio_set3_level = {<br>+ .gpio68 = GPIO_LEVEL_HIGH,<br>+ .gpio70 = GPIO_LEVEL_HIGH,<br>+ .gpio72 = GPIO_LEVEL_HIGH,<br>+ .gpio73 = GPIO_LEVEL_HIGH,<br>+ .gpio74 = GPIO_LEVEL_HIGH,<br>+};<br>+<br>+const struct pch_gpio_set3 pch_gpio_set3_reset = {<br>+};<br>+<br>+const struct pch_gpio_map mainboard_gpio_map = {<br>+ .set1 = {<br>+ .mode = &pch_gpio_set1_mode,<br>+ .direction = &pch_gpio_set1_direction,<br>+ .level = &pch_gpio_set1_level,<br>+ .blink = &pch_gpio_set1_blink,<br>+ .invert = &pch_gpio_set1_invert,<br>+ .reset = &pch_gpio_set1_reset,<br>+ },<br>+ .set2 = {<br>+ .mode = &pch_gpio_set2_mode,<br>+ .direction = &pch_gpio_set2_direction,<br>+ .level = &pch_gpio_set2_level,<br>+ .reset = &pch_gpio_set2_reset,<br>+ },<br>+ .set3 = {<br>+ .mode = &pch_gpio_set3_mode,<br>+ .direction = &pch_gpio_set3_direction,<br>+ .level = &pch_gpio_set3_level,<br>+ .reset = &pch_gpio_set3_reset,<br>+ },<br>+};<br>diff --git a/src/mainboard/hp/2760p/hda_verb.c b/src/mainboard/hp/2760p/hda_verb.c<br>new file mode 100644<br>index 0000000..6a62cf1<br>--- /dev/null<br>+++ b/src/mainboard/hp/2760p/hda_verb.c<br>@@ -0,0 +1,82 @@<br>+/*<br>+ * This file is part of the coreboot project.<br>+ *<br>+ * Copyright (C) 2011 The ChromiumOS Authors. All rights reserved.<br>+ * Copyright (C) 2014 Vladimir Serbinenko<br>+ * Copyright (C) 2017 Iru Cai <mytbk920423@gmail.com><br>+ *<br>+ * This program is free software; you can redistribute it and/or<br>+ * modify it under the terms of the GNU General Public License as<br>+ * published by the Free Software Foundation; version 2 of the License.<br>+ *<br>+ * This program is distributed in the hope that it will be useful,<br>+ * but WITHOUT ANY WARRANTY; without even the implied warranty of<br>+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the<br>+ * GNU General Public License for more details.<br>+ */<br>+<br>+#include <device/azalia_device.h><br>+<br>+const u32 cim_verb_data[] = {<br>+ 0x111d7605, /* Codec Vendor / Device ID: IDT */<br>+ 0x103c162a, /* Subsystem ID */<br>+<br>+ 0x0000000b, /* Number of 4 dword sets */<br>+ /* NID 0x01: Subsystem ID. */<br>+ AZALIA_SUBVENDOR(0x0, 0x103c162a),<br>+<br>+ /* NID 0x0a. */<br>+ AZALIA_PIN_CFG(0x0, 0x0a, 0x40f000f0),<br>+<br>+ /* NID 0x0b. */<br>+ AZALIA_PIN_CFG(0x0, 0x0b, 0x0421401f),<br>+<br>+ /* NID 0x0c. */<br>+ AZALIA_PIN_CFG(0x0, 0x0c, 0x04a11020),<br>+<br>+ /* NID 0x0d. */<br>+ AZALIA_PIN_CFG(0x0, 0x0d, 0x90170110),<br>+<br>+ /* NID 0x0e. */<br>+ AZALIA_PIN_CFG(0x0, 0x0e, 0x90a70130),<br>+<br>+ /* NID 0x0f. */<br>+ AZALIA_PIN_CFG(0x0, 0x0f, 0x40f000f0),<br>+<br>+ /* NID 0x10. */<br>+ AZALIA_PIN_CFG(0x0, 0x10, 0x40f000f0),<br>+<br>+ /* NID 0x11. */<br>+ AZALIA_PIN_CFG(0x0, 0x11, 0x40f000f0),<br>+<br>+ /* NID 0x1f. */<br>+ AZALIA_PIN_CFG(0x0, 0x1f, 0x40f000f0),<br>+<br>+ /* NID 0x20. */<br>+ AZALIA_PIN_CFG(0x0, 0x20, 0x40f000f0),<br>+ 0x11c11040, /* Codec Vendor / Device ID: LSI */<br>+ 0x103c3066, /* Subsystem ID */<br>+<br>+ 0x00000001, /* Number of 4 dword sets */<br>+ /* NID 0x01: Subsystem ID. */<br>+ AZALIA_SUBVENDOR(0x1, 0x103c3066),<br>+ 0x80862805, /* Codec Vendor / Device ID: Intel */<br>+ 0x80860101, /* Subsystem ID */<br>+<br>+ 0x00000004, /* Number of 4 dword sets */<br>+ /* NID 0x01: Subsystem ID. */<br>+ AZALIA_SUBVENDOR(0x3, 0x80860101),<br>+<br>+ /* NID 0x05. */<br>+ AZALIA_PIN_CFG(0x3, 0x05, 0x18560010),<br>+<br>+ /* NID 0x06. */<br>+ AZALIA_PIN_CFG(0x3, 0x06, 0x58560020),<br>+<br>+ /* NID 0x07. */<br>+ AZALIA_PIN_CFG(0x3, 0x07, 0x58560030),<br>+};<br>+<br>+const u32 pc_beep_verbs[0] = {};<br>+<br>+AZALIA_ARRAY_SIZES;<br>diff --git a/src/mainboard/hp/2760p/romstage.c b/src/mainboard/hp/2760p/romstage.c<br>new file mode 100644<br>index 0000000..6ac4efe<br>--- /dev/null<br>+++ b/src/mainboard/hp/2760p/romstage.c<br>@@ -0,0 +1,33 @@<br>+/*<br>+ * This file is part of the coreboot project.<br>+ *<br>+ * Copyright (C) 2017 Iru Cai <mytbk920423@gmail.com><br>+ *<br>+ * This program is free software; you can redistribute it and/or modify<br>+ * it under the terms of the GNU General Public License as published by<br>+ * the Free Software Foundation; version 2 of the License.<br>+ *<br>+ * This program is distributed in the hope that it will be useful,<br>+ * but WITHOUT ANY WARRANTY; without even the implied warranty of<br>+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the<br>+ * GNU General Public License for more details.<br>+ */<br>+<br>+#include <southbridge/intel/bd82x6x/pch.h><br>+<br>+const struct southbridge_usb_port mainboard_usb_ports[] = {<br>+ { 1, 1, 0 },<br>+ { 1, 1, 0 },<br>+ { 1, 1, 1 },<br>+ { 1, 1, 1 },<br>+ { 1, 0, 2 },<br>+ { 1, 1, 2 },<br>+ { 0, 0, 3 },<br>+ { 1, 0, 3 },<br>+ { 1, 1, 4 },<br>+ { 1, 0, 4 },<br>+ { 0, 0, 5 },<br>+ { 1, 1, 5 },<br>+ { 0, 0, 6 },<br>+ { 1, 1, 6 },<br>+};<br></pre><p>To view, visit <a href="https://review.coreboot.org/20779">change 20779</a>. To unsubscribe, visit <a href="https://review.coreboot.org/settings">settings</a>.</p><div itemscope itemtype="http://schema.org/EmailMessage"><div itemscope itemprop="action" itemtype="http://schema.org/ViewAction"><link itemprop="url" href="https://review.coreboot.org/20779"/><meta itemprop="name" content="View Change"/></div></div>
<div style="display:none"> Gerrit-Project: coreboot </div>
<div style="display:none"> Gerrit-Branch: master </div>
<div style="display:none"> Gerrit-MessageType: newchange </div>
<div style="display:none"> Gerrit-Change-Id: I2d0fb1c3f8214aecea17e3a111932d7df8bc4af1 </div>
<div style="display:none"> Gerrit-Change-Number: 20779 </div>
<div style="display:none"> Gerrit-PatchSet: 1 </div>
<div style="display:none"> Gerrit-Owner: Iru Cai <mytbk920423@gmail.com> </div>