<p>Hannah Williams has uploaded this change for <strong>review</strong>.</p><p><a href="https://review.coreboot.org/20755">View Change</a></p><pre style="font-family: monospace,monospace; white-space: pre-wrap;">soc/intel/apollolake: Add CNVI and PCIE IRQs for GLK<br><br>Change-Id: I0387ccf6970e6169cbebd232ae210731338d0900<br>Signed-off-by: Hannah Williams <hannah.williams@intel.com><br>---<br>M src/soc/intel/apollolake/acpi/pci_irqs.asl<br>M src/soc/intel/apollolake/acpi/soc_int.asl<br>2 files changed, 13 insertions(+), 0 deletions(-)<br><br></pre><pre style="font-family: monospace,monospace; white-space: pre-wrap;">git pull ssh://review.coreboot.org:29418/coreboot refs/changes/55/20755/1</pre><pre style="font-family: monospace,monospace; white-space: pre-wrap;">diff --git a/src/soc/intel/apollolake/acpi/pci_irqs.asl b/src/soc/intel/apollolake/acpi/pci_irqs.asl<br>index 22878c6..2475db3 100644<br>--- a/src/soc/intel/apollolake/acpi/pci_irqs.asl<br>+++ b/src/soc/intel/apollolake/acpi/pci_irqs.asl<br>@@ -30,6 +30,15 @@<br>           Package(){0x000FFFFF, 0, 0, CSE_INT},<br>                 Package(){0x0011FFFF, 0, 0, ISH_INT},<br>                 Package(){0x0012FFFF, 0, 0, SATA_INT},<br>+#if IS_ENABLED(CONFIG_SOC_INTEL_GLK)<br>+                Package(){0x000CFFFF, 0, 0, CNVI_INT},<br>+               Package(){0x0013FFFF, 0, 0, PIRQF_INT},<br>+              Package(){0x0013FFFF, 1, 0, PIRQF_INT},<br>+              Package(){0x0013FFFF, 2, 0, PIRQF_INT},<br>+              Package(){0x0013FFFF, 3, 0, PIRQF_INT},<br>+              Package(){0x0014FFFF, 0, 0, PIRQG_INT},<br>+              Package(){0x0014FFFF, 1, 0, PIRQG_INT},<br>+#else<br>               Package(){0x0013FFFF, 0, 0, PIRQA_INT},<br>               Package(){0x0013FFFF, 1, 0, PIRQB_INT},<br>               Package(){0x0013FFFF, 2, 0, PIRQC_INT},<br>@@ -38,6 +47,7 @@<br>            Package(){0x0014FFFF, 1, 0, PIRQC_INT},<br>               Package(){0x0014FFFF, 2, 0, PIRQD_INT},<br>               Package(){0x0014FFFF, 3, 0, PIRQA_INT},<br>+#endif<br>              Package(){0x0015FFFF, 0, 0, XHCI_INT},<br>                Package(){0x0015FFFF, 1, 0, XDCI_INT},<br>                Package(){0x0016FFFF, 0, 0, I2C0_INT},<br>diff --git a/src/soc/intel/apollolake/acpi/soc_int.asl b/src/soc/intel/apollolake/acpi/soc_int.asl<br>index c643244..11b5460 100644<br>--- a/src/soc/intel/apollolake/acpi/soc_int.asl<br>+++ b/src/soc/intel/apollolake/acpi/soc_int.asl<br>@@ -36,6 +36,8 @@<br> #define SMBUS_INT      20      /* PIRQE */<br> #define CSE_INT           20      /* PIRQE */<br> #define IUNIT_INT 21      /* PIRQF */<br>+#define PIRQF_INT 21<br>+#define PIRQG_INT  22<br> #define PUNIT_INT  24<br> #define AUDIO_INT  25<br> #define ISH_INT            26<br>@@ -54,5 +56,6 @@<br> #define EMMC_INT        39<br> #define PMC_INT            40<br> #define SDIO_INT   42<br>+#define CNVI_INT   44<br> <br> #endif  /* _SOC_INT_DEFINE_ASL_ */<br></pre><p>To view, visit <a href="https://review.coreboot.org/20755">change 20755</a>. To unsubscribe, visit <a href="https://review.coreboot.org/settings">settings</a>.</p><div itemscope itemtype="http://schema.org/EmailMessage"><div itemscope itemprop="action" itemtype="http://schema.org/ViewAction"><link itemprop="url" href="https://review.coreboot.org/20755"/><meta itemprop="name" content="View Change"/></div></div>

<div style="display:none"> Gerrit-Project: coreboot </div>
<div style="display:none"> Gerrit-Branch: master </div>
<div style="display:none"> Gerrit-MessageType: newchange </div>
<div style="display:none"> Gerrit-Change-Id: I0387ccf6970e6169cbebd232ae210731338d0900 </div>
<div style="display:none"> Gerrit-Change-Number: 20755 </div>
<div style="display:none"> Gerrit-PatchSet: 1 </div>
<div style="display:none"> Gerrit-Owner: Hannah Williams <hannah.williams@intel.com> </div>
<div style="display:none"> Gerrit-Reviewer: Ravishankar Sarawadi <ravishankar.sarawadi@intel.com> </div>