<p>Marshall Dawson has uploaded this change for <strong>review</strong>.</p><p><a href="https://review.coreboot.org/20744">View Change</a></p><pre style="font-family: monospace,monospace; white-space: pre-wrap;">amd/gardenia: Correct PCIe port settings<br><br>Fix the OEM settings for two ports and remove an extraneous comment.<br><br>Change-Id: I2812ea5945f67229872e78041c771606047bbbec<br>Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com><br>---<br>M src/mainboard/amd/gardenia/OemCustomize.c<br>1 file changed, 3 insertions(+), 4 deletions(-)<br><br></pre><pre style="font-family: monospace,monospace; white-space: pre-wrap;">git pull ssh://review.coreboot.org:29418/coreboot refs/changes/44/20744/1</pre><pre style="font-family: monospace,monospace; white-space: pre-wrap;">diff --git a/src/mainboard/amd/gardenia/OemCustomize.c b/src/mainboard/amd/gardenia/OemCustomize.c<br>index 47e332e..692bdb2 100644<br>--- a/src/mainboard/amd/gardenia/OemCustomize.c<br>+++ b/src/mainboard/amd/gardenia/OemCustomize.c<br>@@ -21,7 +21,7 @@<br>  /* Init port descriptor (PCIe port, Lanes 7:4, D2F1) for x4 slot */<br>   {<br>             0,<br>-           PCIE_ENGINE_DATA_INITIALIZER(PcieUnusedEngine, 4, 7),<br>+                PCIE_ENGINE_DATA_INITIALIZER(PciePortEngine, 4, 7),<br>           PCIE_PORT_DATA_INITIALIZER_V2(PortEnabled, ChannelTypeExt6db,<br>                                 2, 1,<br>                                 HotplugDisabled,<br>@@ -32,8 +32,8 @@<br>   /* Initialize Port descriptor (PCIe port, Lanes 1:0, D2F2) for M.2 */<br>         {<br>             0,<br>-           PCIE_ENGINE_DATA_INITIALIZER(PcieUnusedEngine, 0, 1),<br>-                PCIE_PORT_DATA_INITIALIZER_V2(PortDisabled, ChannelTypeExt6db,<br>+               PCIE_ENGINE_DATA_INITIALIZER(PciePortEngine, 0, 1),<br>+          PCIE_PORT_DATA_INITIALIZER_V2(PortEnabled, ChannelTypeExt6db,<br>                                 2, 2,<br>                                 HotplugDisabled,<br>                              PcieGenMaxSupported,<br>@@ -72,7 +72,6 @@<br>                               PcieGenMaxSupported,<br>                          AspmL0sL1, 0x16, 0)<br>   },<br>-   /* Initialize Port descriptor (PCIe port, Lane 1, D2F3) for M.2 */<br> };<br> <br> static const PCIe_DDI_DESCRIPTOR DdiList[] = {<br></pre><p>To view, visit <a href="https://review.coreboot.org/20744">change 20744</a>. To unsubscribe, visit <a href="https://review.coreboot.org/settings">settings</a>.</p><div itemscope itemtype="http://schema.org/EmailMessage"><div itemscope itemprop="action" itemtype="http://schema.org/ViewAction"><link itemprop="url" href="https://review.coreboot.org/20744"/><meta itemprop="name" content="View Change"/></div></div>

<div style="display:none"> Gerrit-Project: coreboot </div>
<div style="display:none"> Gerrit-Branch: master </div>
<div style="display:none"> Gerrit-MessageType: newchange </div>
<div style="display:none"> Gerrit-Change-Id: I2812ea5945f67229872e78041c771606047bbbec </div>
<div style="display:none"> Gerrit-Change-Number: 20744 </div>
<div style="display:none"> Gerrit-PatchSet: 1 </div>
<div style="display:none"> Gerrit-Owner: Marshall Dawson <marshalldawson3rd@gmail.com> </div>