<p>Martin Roth has uploaded this change for <strong>review</strong>.</p><p><a href="https://review.coreboot.org/20729">View Change</a></p><pre style="font-family: monospace,monospace; white-space: pre-wrap;">src/cpu: Fix checkpatch warning: no spaces at the start of a line<br><br>Change-Id: Iabdaaaee49e8c5cead304cda66412aa36a2ffd19<br>Signed-off-by: Martin Roth <martinroth@google.com><br>---<br>M src/cpu/amd/agesa/family15/fixme.c<br>M src/cpu/amd/family_10h-family_15h/fidvid.c<br>M src/cpu/amd/family_10h-family_15h/model_10xxx_init.c<br>3 files changed, 34 insertions(+), 34 deletions(-)<br><br></pre><pre style="font-family: monospace,monospace; white-space: pre-wrap;">git pull ssh://review.coreboot.org:29418/coreboot refs/changes/29/20729/1</pre><pre style="font-family: monospace,monospace; white-space: pre-wrap;">diff --git a/src/cpu/amd/agesa/family15/fixme.c b/src/cpu/amd/agesa/family15/fixme.c<br>index 03f4dff..9134d5a 100644<br>--- a/src/cpu/amd/agesa/family15/fixme.c<br>+++ b/src/cpu/amd/agesa/family15/fixme.c<br>@@ -20,31 +20,31 @@<br> <br> UINT64<br> MsrRead (<br>- IN UINT32 MsrAddress<br>- );<br>+ IN UINT32 MsrAddress<br>+ );<br> <br> VOID<br> MsrWrite (<br>- IN UINT32 MsrAddress,<br>- IN UINT64 Value<br>- );<br>+ IN UINT32 MsrAddress,<br>+ IN UINT64 Value<br>+ );<br> <br> <br> UINT64<br> MsrRead (<br>- IN UINT32 MsrAddress<br>- )<br>+ IN UINT32 MsrAddress<br>+ )<br> {<br>- return __readmsr (MsrAddress);<br>+ return __readmsr (MsrAddress);<br> }<br> <br> VOID<br> MsrWrite (<br>- IN UINT32 MsrAddress,<br>- IN UINT64 Value<br>- )<br>+ IN UINT32 MsrAddress,<br>+ IN UINT64 Value<br>+ )<br> {<br>- __writemsr (MsrAddress, Value);<br>+ __writemsr (MsrAddress, Value);<br> }<br> <br> #if !IS_ENABLED(CONFIG_BOARD_AMD_DINAR)<br>diff --git a/src/cpu/amd/family_10h-family_15h/fidvid.c b/src/cpu/amd/family_10h-family_15h/fidvid.c<br>index 12fc2c7..e4bb9a3 100644<br>--- a/src/cpu/amd/family_10h-family_15h/fidvid.c<br>+++ b/src/cpu/amd/family_10h-family_15h/fidvid.c<br>@@ -310,7 +310,7 @@<br> msr = rdmsr(0xC0010064);<br> highVoltageVid = (u8) ((msr.lo >> PS_CPU_VID_SHFT) & 0x7F);<br> if (!(msr.hi & 0x80000000)) {<br>- printk(BIOS_ERR,"P-state info in MSRC001_0064 is invalid !!!\n");<br>+ printk(BIOS_ERR,"P-state info in MSRC001_0064 is invalid !!!\n");<br> highVoltageVid = (u8) ((pci_read_config32(dev, 0x1E0)<br> >> PS_CPU_VID_SHFT) & 0x7F);<br> }<br>@@ -340,7 +340,7 @@<br> /* If SVI, we only care about CPU VID.<br> * If PVI, determine the higher voltage b/t NB and CPU<br> * BKDG 2.4.1.7 (a)<br>- */<br>+ */<br> if (pviModeFlag) {<br> bValue = (u8) ((msr.lo >> PS_NB_VID_SHFT) & 0x7F);<br> if (lowVoltageVid > bValue)<br>@@ -685,8 +685,8 @@<br> }<br> <br> static void set_pstate(u32 nonBoostedPState) {<br>- msr_t msr;<br>- uint8_t skip_wait;<br>+ msr_t msr;<br>+ uint8_t skip_wait;<br> <br> // Transition P0 for calling core.<br> msr = rdmsr(0xC0010062);<br>@@ -735,23 +735,23 @@<br> }<br> <br> static void fixPsNbVidBeforeWR(u32 newNbVid, u32 coreid, u32 dev, u8 pviMode)<br>- {<br>- msr_t msr;<br>- u8 startup_pstate;<br>+{<br>+ msr_t msr;<br>+ u8 startup_pstate;<br> <br>- /* This function sets NbVid before the warm reset.<br>- * Get StartupPstate from MSRC001_0071.<br>+ /* This function sets NbVid before the warm reset.<br>+ * Get StartupPstate from MSRC001_0071.<br> * Read Pstate register pointed by [StartupPstate].<br>- * and copy its content to P0 and P1 registers.<br>- * Copy newNbVid to P0[NbVid].<br>- * transition to P1 on all cores,<br>- * then transition to P0 on core 0.<br>- * Wait for MSRC001_0063[CurPstate] = 000b on core 0.<br>+ * and copy its content to P0 and P1 registers.<br>+ * Copy newNbVid to P0[NbVid].<br>+ * transition to P1 on all cores,<br>+ * then transition to P0 on core 0.<br>+ * Wait for MSRC001_0063[CurPstate] = 000b on core 0.<br> * see BKDG rev 3.48 2.4.2.9.1 BIOS NB COF and VID Configuration<br> * for SVI and Single-Plane PVI Systems<br>- */<br>+ */<br> <br>- msr = rdmsr(0xc0010071);<br>+ msr = rdmsr(0xc0010071);<br> startup_pstate = (msr.hi >> (32 - 32)) & 0x07;<br> <br> /* Copy startup pstate to P1 and P0 MSRs. Set the maxvid for<br>@@ -768,7 +768,7 @@<br> * PstatMaxVal is going to be 0 on cold reset anyway ?<br> */<br> if (!(pci_read_config32(dev, 0xdc) & (~PS_MAX_VAL_MASK))) {<br>- printk(BIOS_ERR,"F3xDC[PstateMaxVal] is zero. Northbridge voltage setting will fail. fixPsNbVidBeforeWR in fidvid.c needs fixing. See AMD # 31116 rev 3.48 BKDG 2.4.2.9.1\n");<br>+ printk(BIOS_ERR,"F3xDC[PstateMaxVal] is zero. Northbridge voltage setting will fail. fixPsNbVidBeforeWR in fidvid.c needs fixing. See AMD # 31116 rev 3.48 BKDG 2.4.2.9.1\n");<br> };<br> <br> msr.lo &= ~0xFE000000; // clear nbvid<br>@@ -784,7 +784,7 @@<br> <br> if (coreid == 0) {<br> set_pstate(0);<br>- }<br>+ }<br> <br> /* missing step 7 (restore PstateMax to 0 if needed) because<br> * we skipped step 2<br>@@ -1010,7 +1010,7 @@<br> }<br> /* write newNbVid to P-state Reg's NbVid if its NbDid=0 */<br> fixPsNbVidAfterWR(nbvid, NbVidUpdateAll,pvimode);<br>- } else { /* !nb_cof_vid_update */<br>+ } else { /* !nb_cof_vid_update */<br> if (pvimode)<br> UpdateSinglePlaneNbVid();<br> }<br>diff --git a/src/cpu/amd/family_10h-family_15h/model_10xxx_init.c b/src/cpu/amd/family_10h-family_15h/model_10xxx_init.c<br>index 361a866..1e2a467 100644<br>--- a/src/cpu/amd/family_10h-family_15h/model_10xxx_init.c<br>+++ b/src/cpu/amd/family_10h-family_15h/model_10xxx_init.c<br>@@ -92,10 +92,10 @@<br> disable_cache();<br> <br> for (i = 0x2; i < 0x10; i++) {<br>- wrmsr(0x00000200 | i, msr);<br>- }<br>+ wrmsr(0x00000200 | i, msr);<br>+ }<br> <br>- enable_cache();<br>+ enable_cache();<br> <br> /* Set up other MTRRs */<br> amd_setup_mtrrs();<br></pre><p>To view, visit <a href="https://review.coreboot.org/20729">change 20729</a>. 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<div style="display:none"> Gerrit-Project: coreboot </div>
<div style="display:none"> Gerrit-Branch: master </div>
<div style="display:none"> Gerrit-MessageType: newchange </div>
<div style="display:none"> Gerrit-Change-Id: Iabdaaaee49e8c5cead304cda66412aa36a2ffd19 </div>
<div style="display:none"> Gerrit-Change-Number: 20729 </div>
<div style="display:none"> Gerrit-PatchSet: 1 </div>
<div style="display:none"> Gerrit-Owner: Martin Roth <martinroth@google.com> </div>