<p>Martin Roth has uploaded this change for <strong>review</strong>.</p><p><a href="https://review.coreboot.org/20704">View Change</a></p><pre style="font-family: monospace,monospace; white-space: pre-wrap;">Fix files with multiple newlines at the end.<br><br>Change-Id: Iaab26033e947cb9cf299faf1ce6d40a90a9facbe<br>Signed-off-by: Martin Roth <martinroth@google.com><br>---<br>M .checkpatch.conf<br>M src/arch/x86/include/arch/pirq_routing.h<br>M src/cpu/amd/agesa/family14/romstage.c<br>M src/lib/gnat/COPYING.RUNTIME<br>M src/mainboard/asus/p5gc-mx/Makefile.inc<br>M src/mainboard/elmex/pcm205400/buildOpts.c<br>M src/mainboard/google/reef/variants/coral/mainboard.c<br>M src/mainboard/intel/kblrvp/variants/rvp7/include/variant/gpio.h<br>M src/mainboard/intel/leafhill/Kconfig.name<br>M src/mainboard/intel/minnow3/gpio.c<br>M src/mainboard/lenovo/x1_carbon_gen1/mainboard.c<br>M src/mainboard/pcengines/apu2/mainboard.c<br>M src/mainboard/purism/librem13v2/Makefile.inc<br>M src/soc/intel/apollolake/xdci.c<br>M src/soc/intel/cannonlake/bootblock/cpu.c<br>M src/soc/intel/cannonlake/include/soc/gpio_soc_defs.h<br>M src/soc/intel/cannonlake/romstage/power_state.c<br>M src/soc/intel/common/block/cse/Kconfig<br>M src/soc/intel/common/block/include/intelblocks/msr.h<br>M src/soc/intel/common/block/include/intelblocks/xhci.h<br>M src/soc/intel/common/block/sata/Kconfig<br>M src/soc/intel/common/block/smbus/Makefile.inc<br>22 files changed, 0 insertions(+), 22 deletions(-)<br><br></pre><pre style="font-family: monospace,monospace; white-space: pre-wrap;">git pull ssh://review.coreboot.org:29418/coreboot refs/changes/04/20704/1</pre><pre style="font-family: monospace,monospace; white-space: pre-wrap;">diff --git a/.checkpatch.conf b/.checkpatch.conf<br>index ad04d39..62cc5d5 100644<br>--- a/.checkpatch.conf<br>+++ b/.checkpatch.conf<br>@@ -28,4 +28,3 @@<br> <br> # Exclude the vendorcode directory<br> --exclude src/vendorcode<br>-<br>diff --git a/src/arch/x86/include/arch/pirq_routing.h b/src/arch/x86/include/arch/pirq_routing.h<br>index 1ca7618..0117912 100644<br>--- a/src/arch/x86/include/arch/pirq_routing.h<br>+++ b/src/arch/x86/include/arch/pirq_routing.h<br>@@ -63,4 +63,3 @@<br> void pirq_assign_irqs(const unsigned char pirq[CONFIG_MAX_PIRQ_LINKS]);<br> <br> #endif /* ARCH_PIRQ_ROUTING_H */<br>-<br>diff --git a/src/cpu/amd/agesa/family14/romstage.c b/src/cpu/amd/agesa/family14/romstage.c<br>index e89b2fc..23fa008 100644<br>--- a/src/cpu/amd/agesa/family14/romstage.c<br>+++ b/src/cpu/amd/agesa/family14/romstage.c<br>@@ -75,4 +75,3 @@<br> post_code(0x62);<br> }<br> }<br>-<br>diff --git a/src/lib/gnat/COPYING.RUNTIME b/src/lib/gnat/COPYING.RUNTIME<br>index e1b3c69..e86f7fb 100644<br>--- a/src/lib/gnat/COPYING.RUNTIME<br>+++ b/src/lib/gnat/COPYING.RUNTIME<br>@@ -70,4 +70,3 @@<br> The availability of this Exception does not imply any general<br> presumption that third-party software is unaffected by the copyleft<br> requirements of the license of GCC.<br>-<br>diff --git a/src/mainboard/asus/p5gc-mx/Makefile.inc b/src/mainboard/asus/p5gc-mx/Makefile.inc<br>index 9aac7e2..f3d7e76 100644<br>--- a/src/mainboard/asus/p5gc-mx/Makefile.inc<br>+++ b/src/mainboard/asus/p5gc-mx/Makefile.inc<br>@@ -1,3 +1,2 @@<br> ramstage-y += cstates.c<br> romstage-y += gpio.c<br>-<br>diff --git a/src/mainboard/elmex/pcm205400/buildOpts.c b/src/mainboard/elmex/pcm205400/buildOpts.c<br>index fe4e779..eb6cf33 100644<br>--- a/src/mainboard/elmex/pcm205400/buildOpts.c<br>+++ b/src/mainboard/elmex/pcm205400/buildOpts.c<br>@@ -294,4 +294,3 @@<br> <br> // Instantiate all solution relevant data.<br> #include "PlatformInstall.h"<br>-<br>diff --git a/src/mainboard/google/reef/variants/coral/mainboard.c b/src/mainboard/google/reef/variants/coral/mainboard.c<br>index 41a8056..54c24f8 100644<br>--- a/src/mainboard/google/reef/variants/coral/mainboard.c<br>+++ b/src/mainboard/google/reef/variants/coral/mainboard.c<br>@@ -29,4 +29,3 @@<br> *oem_table_id = CONFIG_VARIANT_DIR;<br> *oem_revision = variant_board_sku();<br> }<br>-<br>diff --git a/src/mainboard/intel/kblrvp/variants/rvp7/include/variant/gpio.h b/src/mainboard/intel/kblrvp/variants/rvp7/include/variant/gpio.h<br>index 7a8314e..2233339 100644<br>--- a/src/mainboard/intel/kblrvp/variants/rvp7/include/variant/gpio.h<br>+++ b/src/mainboard/intel/kblrvp/variants/rvp7/include/variant/gpio.h<br>@@ -218,4 +218,3 @@<br> #endif<br> <br> #endif<br>-<br>diff --git a/src/mainboard/intel/leafhill/Kconfig.name b/src/mainboard/intel/leafhill/Kconfig.name<br>index 391203c..bff60da 100644<br>--- a/src/mainboard/intel/leafhill/Kconfig.name<br>+++ b/src/mainboard/intel/leafhill/Kconfig.name<br>@@ -1,3 +1,2 @@<br> config BOARD_INTEL_LEAFHILL<br> bool "Leafhill"<br>-<br>diff --git a/src/mainboard/intel/minnow3/gpio.c b/src/mainboard/intel/minnow3/gpio.c<br>index 4e8f926..330a242 100644<br>--- a/src/mainboard/intel/minnow3/gpio.c<br>+++ b/src/mainboard/intel/minnow3/gpio.c<br>@@ -348,4 +348,3 @@<br> *num = ARRAY_SIZE(sleep_gpio_table_config);<br> return sleep_gpio_table_config;<br> }<br>-<br>diff --git a/src/mainboard/lenovo/x1_carbon_gen1/mainboard.c b/src/mainboard/lenovo/x1_carbon_gen1/mainboard.c<br>index a61f12c..a4f2b38 100644<br>--- a/src/mainboard/lenovo/x1_carbon_gen1/mainboard.c<br>+++ b/src/mainboard/lenovo/x1_carbon_gen1/mainboard.c<br>@@ -34,4 +34,3 @@<br> void h8_mainboard_init_dock (void)<br> {<br> }<br>-<br>diff --git a/src/mainboard/pcengines/apu2/mainboard.c b/src/mainboard/pcengines/apu2/mainboard.c<br>index f82ed50..f337147 100644<br>--- a/src/mainboard/pcengines/apu2/mainboard.c<br>+++ b/src/mainboard/pcengines/apu2/mainboard.c<br>@@ -232,4 +232,3 @@<br> .enable_dev = mainboard_enable,<br> };<br> <br>-<br>diff --git a/src/mainboard/purism/librem13v2/Makefile.inc b/src/mainboard/purism/librem13v2/Makefile.inc<br>index eb01360..5a7131f 100644<br>--- a/src/mainboard/purism/librem13v2/Makefile.inc<br>+++ b/src/mainboard/purism/librem13v2/Makefile.inc<br>@@ -18,4 +18,3 @@<br> ramstage-y += pei_data.c<br> ramstage-y += ramstage.c<br> ramstage-y += hda_verb.c<br>-<br>diff --git a/src/soc/intel/apollolake/xdci.c b/src/soc/intel/apollolake/xdci.c<br>index 2578fa0..4c3047c 100644<br>--- a/src/soc/intel/apollolake/xdci.c<br>+++ b/src/soc/intel/apollolake/xdci.c<br>@@ -89,4 +89,3 @@<br> {<br> configure_host_mode_port0(dev);<br> }<br>-<br>diff --git a/src/soc/intel/cannonlake/bootblock/cpu.c b/src/soc/intel/cannonlake/bootblock/cpu.c<br>index 5b336da..3ebe1e4 100644<br>--- a/src/soc/intel/cannonlake/bootblock/cpu.c<br>+++ b/src/soc/intel/cannonlake/bootblock/cpu.c<br>@@ -25,4 +25,3 @@<br> IS_ENABLED(CONFIG_BOOT_DEVICE_SPI_FLASH))<br> fast_spi_cache_bios_region();<br> }<br>-<br>diff --git a/src/soc/intel/cannonlake/include/soc/gpio_soc_defs.h b/src/soc/intel/cannonlake/include/soc/gpio_soc_defs.h<br>index cdc40d4..e9a5b89 100644<br>--- a/src/soc/intel/cannonlake/include/soc/gpio_soc_defs.h<br>+++ b/src/soc/intel/cannonlake/include/soc/gpio_soc_defs.h<br>@@ -249,4 +249,3 @@<br> #define NUM_GPIO_COM2_PADS (GPD11 - GPD0 + 1)<br> <br> #endif<br>-<br>diff --git a/src/soc/intel/cannonlake/romstage/power_state.c b/src/soc/intel/cannonlake/romstage/power_state.c<br>index 2c98a9e..2c45ad9 100644<br>--- a/src/soc/intel/cannonlake/romstage/power_state.c<br>+++ b/src/soc/intel/cannonlake/romstage/power_state.c<br>@@ -29,4 +29,3 @@<br> <br> return ps;<br> }<br>-<br>diff --git a/src/soc/intel/common/block/cse/Kconfig b/src/soc/intel/common/block/cse/Kconfig<br>index 441ff93..321d34c 100644<br>--- a/src/soc/intel/common/block/cse/Kconfig<br>+++ b/src/soc/intel/common/block/cse/Kconfig<br>@@ -4,4 +4,3 @@<br> help<br> Driver for communication with Converged Security Engine (CSE)<br> over Host Embedded Controller Interface (HECI)<br>-<br>diff --git a/src/soc/intel/common/block/include/intelblocks/msr.h b/src/soc/intel/common/block/include/intelblocks/msr.h<br>index 1025c28..55d0bfd 100644<br>--- a/src/soc/intel/common/block/include/intelblocks/msr.h<br>+++ b/src/soc/intel/common/block/include/intelblocks/msr.h<br>@@ -133,4 +133,3 @@<br> <br> #define SGX_SUPPORTED (1<<2)<br> #endif /* SOC_INTEL_COMMON_MSR_H */<br>-<br>diff --git a/src/soc/intel/common/block/include/intelblocks/xhci.h b/src/soc/intel/common/block/include/intelblocks/xhci.h<br>index ea1f682..32ae9a2 100644<br>--- a/src/soc/intel/common/block/include/intelblocks/xhci.h<br>+++ b/src/soc/intel/common/block/include/intelblocks/xhci.h<br>@@ -19,4 +19,3 @@<br> void soc_xhci_init(struct device *dev);<br> <br> #endif /* SOC_INTEL_COMMON_BLOCK_XHCI_H */<br>-<br>diff --git a/src/soc/intel/common/block/sata/Kconfig b/src/soc/intel/common/block/sata/Kconfig<br>index 89ca12e..6b24f59 100644<br>--- a/src/soc/intel/common/block/sata/Kconfig<br>+++ b/src/soc/intel/common/block/sata/Kconfig<br>@@ -2,4 +2,3 @@<br> bool<br> help<br> Intel Processor common SATA support<br>-<br>diff --git a/src/soc/intel/common/block/smbus/Makefile.inc b/src/soc/intel/common/block/smbus/Makefile.inc<br>index e33f37f..1a10fd9 100644<br>--- a/src/soc/intel/common/block/smbus/Makefile.inc<br>+++ b/src/soc/intel/common/block/smbus/Makefile.inc<br>@@ -6,4 +6,3 @@<br> <br> ramstage-$(CONFIG_SOC_INTEL_COMMON_BLOCK_SMBUS) += smbuslib.c<br> ramstage-$(CONFIG_SOC_INTEL_COMMON_BLOCK_SMBUS) += smbus.c<br>-<br></pre><p>To view, visit <a href="https://review.coreboot.org/20704">change 20704</a>. To unsubscribe, visit <a href="https://review.coreboot.org/settings">settings</a>.</p><div itemscope itemtype="http://schema.org/EmailMessage"><div itemscope itemprop="action" itemtype="http://schema.org/ViewAction"><link itemprop="url" href="https://review.coreboot.org/20704"/><meta itemprop="name" content="View Change"/></div></div>
<div style="display:none"> Gerrit-Project: coreboot </div>
<div style="display:none"> Gerrit-Branch: master </div>
<div style="display:none"> Gerrit-MessageType: newchange </div>
<div style="display:none"> Gerrit-Change-Id: Iaab26033e947cb9cf299faf1ce6d40a90a9facbe </div>
<div style="display:none"> Gerrit-Change-Number: 20704 </div>
<div style="display:none"> Gerrit-PatchSet: 1 </div>
<div style="display:none"> Gerrit-Owner: Martin Roth <martinroth@google.com> </div>