<p>James has uploaded this change for <strong>review</strong>.</p><p><a href="https://review.coreboot.org/20694">View Change</a></p><pre style="font-family: monospace,monospace; white-space: pre-wrap;">mainboard/lenovo: add new port ThinkPad X131e (Intel)<br><br>Add support for Lenovo ThinkPad X131e (Intel).<br><br>The Intel version of ThinkPad X131e can ship with SandyBridge or<br>IvyBridge processors. The mainboard uses 8MiB+4MiB flash chips, with<br>the 8MiB chip containing the IFD and ME, and the 4MiB chip containing<br>the BIOS. The flash chips can be accessed with an external programmer.<br><br>Tested and working:<br> - Machine type 3367AH5 / Intel Celeron 887 (SandyBridge)<br> - Boots Debian GNU/Linux 9.0 (Linux 4.9.30-2+deb9u2) via SeaBIOS<br> - Boot from internal SATA<br> - Native RAM init<br> - Native VGA init<br> - libgfxinit<br> - VGA display output<br> - Keyboard, trackpoint, touchpad<br> - Audio (speaker, headphones)<br> - Ethernet (Realtek)<br> - Backlight<br> - USB ports<br> - SD card reader<br> - Webcam<br> - Fan and temperature sensors<br><br>Not tested:<br> - HDMI display out<br> - Wifi (Broadcom)<br> - WWAN/mSATA (no card)<br> - Other operating systems<br><br>Not working or not implemented:<br> - Fn keys<br> - TPM<br> - ACPI S3 (Sleep)<br> - ACPI S4 (Hibernation)<br> - CMOS<br><br>Change-Id: If8de3a9308997e2d57aee869023ee9a43a2db872<br>Signed-off-by: James Ye <jye836@gmail.com><br>---<br>A src/mainboard/lenovo/x131e/Kconfig<br>A src/mainboard/lenovo/x131e/Kconfig.name<br>A src/mainboard/lenovo/x131e/Makefile.inc<br>A src/mainboard/lenovo/x131e/acpi/ec.asl<br>A src/mainboard/lenovo/x131e/acpi/platform.asl<br>A src/mainboard/lenovo/x131e/acpi/superio.asl<br>A src/mainboard/lenovo/x131e/acpi_tables.c<br>A src/mainboard/lenovo/x131e/board_info.txt<br>A src/mainboard/lenovo/x131e/devicetree.cb<br>A src/mainboard/lenovo/x131e/dsdt.asl<br>A src/mainboard/lenovo/x131e/gma-mainboard.ads<br>A src/mainboard/lenovo/x131e/gpio.c<br>A src/mainboard/lenovo/x131e/hda_verb.c<br>A src/mainboard/lenovo/x131e/mainboard.c<br>A src/mainboard/lenovo/x131e/romstage.c<br>A src/mainboard/lenovo/x131e/smihandler.c<br>A src/mainboard/lenovo/x131e/thermal.h<br>17 files changed, 1,012 insertions(+), 0 deletions(-)<br><br></pre><pre style="font-family: monospace,monospace; white-space: pre-wrap;">git pull ssh://review.coreboot.org:29418/coreboot refs/changes/94/20694/1</pre><pre style="font-family: monospace,monospace; white-space: pre-wrap;">diff --git a/src/mainboard/lenovo/x131e/Kconfig b/src/mainboard/lenovo/x131e/Kconfig<br>new file mode 100644<br>index 0000000..969e943<br>--- /dev/null<br>+++ b/src/mainboard/lenovo/x131e/Kconfig<br>@@ -0,0 +1,67 @@<br>+if BOARD_LENOVO_X131E<br>+<br>+config BOARD_SPECIFIC_OPTIONS # dummy<br>+ def_bool y<br>+ select SYSTEM_TYPE_LAPTOP<br>+ select CPU_INTEL_SOCKET_RPGA989<br>+ select NORTHBRIDGE_INTEL_SANDYBRIDGE<br>+ select USE_NATIVE_RAMINIT<br>+ select SOUTHBRIDGE_INTEL_C216<br>+ select EC_LENOVO_PMH7<br>+ select EC_LENOVO_H8<br>+ select NO_UART_ON_SUPERIO<br>+ select BOARD_ROMSIZE_KB_12288<br>+ select HAVE_ACPI_TABLES<br>+ select HAVE_ACPI_RESUME<br>+ select INTEL_INT15<br>+ select SANDYBRIDGE_IVYBRIDGE_LVDS<br>+ select MAINBOARD_HAS_LPC_TPM<br>+ select MAINBOARD_HAS_LIBGFXINIT<br>+ select GFX_GMA_INTERNAL_IS_LVDS<br>+ select SERIRQ_CONTINUOUS_MODE<br>+<br>+config HAVE_IFD_BIN<br>+ bool<br>+ default n<br>+<br>+config HAVE_ME_BIN<br>+ bool<br>+ default n<br>+<br>+config MAINBOARD_DIR<br>+ string<br>+ default lenovo/x131e<br>+<br>+config MAINBOARD_PART_NUMBER<br>+ string<br>+ default "ThinkPad X131e"<br>+<br>+config MMCONF_BASE_ADDRESS<br>+ hex<br>+ default 0xf8000000<br>+<br>+config MAX_CPUS<br>+ int<br>+ default 8<br>+<br>+config USBDEBUG_HCD_INDEX<br>+ int<br>+ default 2<br>+<br>+config DRAM_RESET_GATE_GPIO<br>+ int<br>+ default 10<br>+<br>+config VGA_BIOS_ID<br>+ string<br>+ default "8086,0106"<br>+<br>+config MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID<br>+ hex<br>+ default 0x17aa<br>+<br>+config MAINBOARD_PCI_SUBSYSTEM_DEVICE_ID<br>+ hex<br>+ default 0x21fe<br>+<br>+endif # BOARD_LENOVO_X131E<br>diff --git a/src/mainboard/lenovo/x131e/Kconfig.name b/src/mainboard/lenovo/x131e/Kconfig.name<br>new file mode 100644<br>index 0000000..46cd891<br>--- /dev/null<br>+++ b/src/mainboard/lenovo/x131e/Kconfig.name<br>@@ -0,0 +1,2 @@<br>+config BOARD_LENOVO_X131E<br>+ bool "ThinkPad X131e"<br>diff --git a/src/mainboard/lenovo/x131e/Makefile.inc b/src/mainboard/lenovo/x131e/Makefile.inc<br>new file mode 100644<br>index 0000000..2dab950<br>--- /dev/null<br>+++ b/src/mainboard/lenovo/x131e/Makefile.inc<br>@@ -0,0 +1,19 @@<br>+##<br>+## This file is part of the coreboot project.<br>+##<br>+## Copyright (C) 2011 The ChromiumOS Authors. All rights reserved.<br>+##<br>+## This program is free software; you can redistribute it and/or modify<br>+## it under the terms of the GNU General Public License as published by<br>+## the Free Software Foundation; version 2 of the License.<br>+##<br>+## This program is distributed in the hope that it will be useful,<br>+## but WITHOUT ANY WARRANTY; without even the implied warranty of<br>+## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the<br>+## GNU General Public License for more details.<br>+##<br>+<br>+smm-$(CONFIG_HAVE_SMI_HANDLER) += smihandler.c<br>+romstage-y += gpio.c<br>+<br>+ramstage-$(CONFIG_MAINBOARD_USE_LIBGFXINIT) += gma-mainboard.ads<br>diff --git a/src/mainboard/lenovo/x131e/acpi/ec.asl b/src/mainboard/lenovo/x131e/acpi/ec.asl<br>new file mode 100644<br>index 0000000..d963dc9<br>--- /dev/null<br>+++ b/src/mainboard/lenovo/x131e/acpi/ec.asl<br>@@ -0,0 +1,28 @@<br>+/*<br>+ * This file is part of the coreboot project.<br>+ *<br>+ * Copyright (c) 2011 Sven Schnelle <svens@stackframe.org><br>+ * Copyright (c) 2017 James Ye <jye836@gmail.com><br>+ *<br>+ * This program is free software; you can redistribute it and/or<br>+ * modify it under the terms of the GNU General Public License as<br>+ * published by the Free Software Foundation; version 2 of<br>+ * the License.<br>+ *<br>+ * This program is distributed in the hope that it will be useful,<br>+ * but WITHOUT ANY WARRANTY; without even the implied warranty of<br>+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the<br>+ * GNU General Public License for more details.<br>+ */<br>+<br>+#define THINKPAD_EC_GPE 22<br>+#define BRIGHTNESS_UP \_SB.PCI0.GFX0.INCB<br>+#define BRIGHTNESS_DOWN \_SB.PCI0.GFX0.DECB<br>+#define ACPI_VIDEO_DEVICE \_SB.PCI0.GFX0<br>+#define EC_LENOVO_H8_ME_WORKAROUND 1<br>+<br>+#include <ec/lenovo/h8/acpi/ec.asl><br>+<br>+Scope(\_SB.PCI0.LPCB.EC)<br>+{<br>+}<br>diff --git a/src/mainboard/lenovo/x131e/acpi/platform.asl b/src/mainboard/lenovo/x131e/acpi/platform.asl<br>new file mode 100644<br>index 0000000..9cd327a<br>--- /dev/null<br>+++ b/src/mainboard/lenovo/x131e/acpi/platform.asl<br>@@ -0,0 +1,37 @@<br>+/*<br>+ * This file is part of the coreboot project.<br>+ *<br>+ * Copyright (C) 2011-2012 The Chromium OS Authors. All rights reserved.<br>+ *<br>+ * This program is free software; you can redistribute it and/or modify<br>+ * it under the terms of the GNU General Public License as published by<br>+ * the Free Software Foundation; version 2 of the License.<br>+ *<br>+ * This program is distributed in the hope that it will be useful,<br>+ * but WITHOUT ANY WARRANTY; without even the implied warranty of<br>+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the<br>+ * GNU General Public License for more details.<br>+ */<br>+<br>+/* The _PTS method (Prepare To Sleep) is called before the OS is<br>+ * entering a sleep state. The sleep state number is passed in Arg0<br>+ */<br>+<br>+Method(_PTS,1)<br>+{<br>+ \_SB.PCI0.LPCB.EC.MUTE(1)<br>+ \_SB.PCI0.LPCB.EC.USBP(0)<br>+ \_SB.PCI0.LPCB.EC.RADI(0)<br>+}<br>+<br>+/* The _WAK method is called on system wakeup */<br>+<br>+Method(_WAK,1)<br>+{<br>+ /* ME may not be up yet. */<br>+ Store (0, \_TZ.MEB1)<br>+ Store (0, \_TZ.MEB2)<br>+<br>+ /* Not implemented. */<br>+ Return(Package(){0,0})<br>+}<br>diff --git a/src/mainboard/lenovo/x131e/acpi/superio.asl b/src/mainboard/lenovo/x131e/acpi/superio.asl<br>new file mode 100644<br>index 0000000..253a358<br>--- /dev/null<br>+++ b/src/mainboard/lenovo/x131e/acpi/superio.asl<br>@@ -0,0 +1,16 @@<br>+/*<br>+ * This file is part of the coreboot project.<br>+ *<br>+ * Copyright (C) 2017 James Ye <jye836@gmail.com><br>+ *<br>+ * This program is free software; you can redistribute it and/or modify<br>+ * it under the terms of the GNU General Public License as published by<br>+ * the Free Software Foundation; version 2 of the License.<br>+ *<br>+ * This program is distributed in the hope that it will be useful,<br>+ * but WITHOUT ANY WARRANTY; without even the implied warranty of<br>+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the<br>+ * GNU General Public License for more details.<br>+ */<br>+<br>+#include <drivers/pc80/pc/ps2_controller.asl><br>diff --git a/src/mainboard/lenovo/x131e/acpi_tables.c b/src/mainboard/lenovo/x131e/acpi_tables.c<br>new file mode 100644<br>index 0000000..c9e9407<br>--- /dev/null<br>+++ b/src/mainboard/lenovo/x131e/acpi_tables.c<br>@@ -0,0 +1,54 @@<br>+/*<br>+ * This file is part of the coreboot project.<br>+ *<br>+ * Copyright (C) 2007-2009 coresystems GmbH<br>+ *<br>+ * This program is free software; you can redistribute it and/or modify<br>+ * it under the terms of the GNU General Public License as published by<br>+ * the Free Software Foundation; version 2 of the License.<br>+ *<br>+ * This program is distributed in the hope that it will be useful,<br>+ * but WITHOUT ANY WARRANTY; without even the implied warranty of<br>+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the<br>+ * GNU General Public License for more details.<br>+ */<br>+<br>+#include <types.h><br>+#include <string.h><br>+#include <cbmem.h><br>+#include <console/console.h><br>+#include <arch/acpi.h><br>+#include <arch/ioapic.h><br>+#include <arch/acpigen.h><br>+#include <arch/smp/mpspec.h><br>+#include <device/device.h><br>+#include <device/pci.h><br>+#include <device/pci_ids.h><br>+<br>+#include <southbridge/intel/bd82x6x/pch.h><br>+#include <southbridge/intel/bd82x6x/nvs.h><br>+#include "thermal.h"<br>+<br>+static void acpi_update_thermal_table(global_nvs_t *gnvs)<br>+{<br>+ gnvs->tcrt = CRITICAL_TEMPERATURE;<br>+ gnvs->tpsv = PASSIVE_TEMPERATURE;<br>+}<br>+<br>+void acpi_create_gnvs(global_nvs_t *gnvs)<br>+{<br>+ /* Disable USB ports in S3 by default */<br>+ gnvs->s3u0 = 0;<br>+ gnvs->s3u1 = 0;<br>+<br>+ /* Disable USB ports in S5 by default */<br>+ gnvs->s5u0 = 0;<br>+ gnvs->s5u1 = 0;<br>+<br>+ /* IGD Displays */<br>+<br>+ // the lid is open by default.<br>+ gnvs->lids = 1;<br>+<br>+ acpi_update_thermal_table(gnvs);<br>+}<br>diff --git a/src/mainboard/lenovo/x131e/board_info.txt b/src/mainboard/lenovo/x131e/board_info.txt<br>new file mode 100644<br>index 0000000..09ddde1<br>--- /dev/null<br>+++ b/src/mainboard/lenovo/x131e/board_info.txt<br>@@ -0,0 +1,6 @@<br>+Category: laptop<br>+ROM package: SOIC-8<br>+ROM protocol: SPI<br>+ROM socketed: n<br>+Flashrom support: n<br>+Release year: 2012<br>diff --git a/src/mainboard/lenovo/x131e/devicetree.cb b/src/mainboard/lenovo/x131e/devicetree.cb<br>new file mode 100644<br>index 0000000..2f3bbbb<br>--- /dev/null<br>+++ b/src/mainboard/lenovo/x131e/devicetree.cb<br>@@ -0,0 +1,181 @@<br>+chip northbridge/intel/sandybridge<br>+ # IGD Displays<br>+ register "gfx.ndid" = "3"<br>+ register "gfx.did" = "{ 0x80000100, 0x80000240, 0x80000410 }"<br>+<br>+ # DisplayPort<br>+ register "gpu_dp_b_hotplug" = "4"<br>+ register "gpu_dp_c_hotplug" = "4"<br>+ register "gpu_dp_d_hotplug" = "4"<br>+<br>+ # Enable Panel as LVDS and configure power delays<br>+ register "gpu_panel_port_select" = "0" # LVDS<br>+ register "gpu_panel_power_cycle_delay" = "6" # T7: 500ms<br>+ register "gpu_panel_power_up_delay" = "100" # T1+T2: 10ms<br>+ register "gpu_panel_power_down_delay" = "100" # T5+T6: 10ms<br>+ register "gpu_panel_power_backlight_on_delay" = "2100" # T3: 210ms<br>+ register "gpu_panel_power_backlight_off_delay" = "2100" # T4: 210ms<br>+ register "gfx.use_spread_spectrum_clock" = "1"<br>+ register "gfx.link_frequency_270_mhz" = "1"<br>+ register "gpu_cpu_backlight" = "0x1155"<br>+ register "gpu_pch_backlight" = "0x11551155"<br>+<br>+ device cpu_cluster 0x0 on<br>+ chip cpu/intel/socket_rPGA989<br>+ device lapic 0x0 on end<br>+ end<br>+ chip cpu/intel/model_206ax<br>+ device lapic 0xacac off end<br>+<br>+ register "c1_acpower" = "1"<br>+ register "c2_acpower" = "3"<br>+ register "c3_acpower" = "5"<br>+<br>+ register "c1_battery" = "1"<br>+ register "c2_battery" = "3"<br>+ register "c3_battery" = "5"<br>+ end<br>+ end<br>+<br>+ device domain 0x0 on<br>+ device pci 00.0 on # Host bridge<br>+ subsystemid 0x17aa 0x21fe<br>+ end<br>+ device pci 01.0 off end # PCIe Bridge for discrete graphics<br>+ device pci 02.0 on # Internal graphics VGA controller<br>+ subsystemid 0x17aa 0x21fe<br>+ end<br>+<br>+ chip southbridge/intel/bd82x6x<br>+ # GPI routing<br>+ register "alt_gp_smi_en" = "0x0000" # 0x0002?<br>+ register "gpi6_routing" = "2"<br>+ register "gpi13_routing" = "2"<br>+<br>+ # Enable SATA ports<br>+ register "sata_port_map" = "0x1"<br>+ # Set max SATA speed to 6.0 Gb/s<br>+ register "sata_interface_speed_support" = "0x3"<br>+<br>+ register "gen1_dec" = "0x007c1611"<br>+ register "gen2_dec" = "0x00040069"<br>+ register "gen3_dec" = "0x000c0701"<br>+ register "gen4_dec" = "0x000c06a1"<br>+<br>+ register "pcie_hotplug_map" = "{ 0, 0, 1, 0, 0, 0, 0, 0 }"<br>+<br>+ register "xhci_switchable_ports" = "0xf"<br>+ register "superspeed_capable_ports" = "0xf"<br>+ register "xhci_overcurrent_mapping" = "0x00000c03"<br>+<br>+ # Enable zero-based linear PCIe root port functions<br>+ register "pcie_port_coalesce" = "1"<br>+ register "c2_latency" = "0x0065"<br>+ register "p_cnt_throttling_supported" = "1"<br>+<br>+ register "spi_uvscc" = "0x2005"<br>+ register "spi_lvscc" = "0x2005"<br>+<br>+ device pci 14.0 on # USB 3.0 Controller<br>+ subsystemid 0x17aa 0x21fe<br>+ end<br>+ device pci 16.0 on # Management Engine Interface 1<br>+ subsystemid 0x17aa 0x21fe<br>+ end<br>+ device pci 16.1 off end # Management Engine Interface 2<br>+ device pci 16.2 off end # Management Engine IDE-R<br>+ device pci 16.3 off end # Management Engine KT<br>+ device pci 19.0 off end # Intel Gigabit Ethernet<br>+ device pci 1a.0 on # USB2 EHCI #2<br>+ subsystemid 0x17aa 0x21fe<br>+ end<br>+ device pci 1b.0 on # High Definition Audio Audio controller<br>+ subsystemid 0x17aa 0x21fe<br>+ end<br>+ device pci 1c.0 on # PCIe Port #1<br>+ subsystemid 0x17aa 0x21fe<br>+ end<br>+ device pci 1c.1 on # PCIe Port #2<br>+ subsystemid 0x17aa 0x21fe<br>+ end<br>+ device pci 1c.2 on # PCIe Port #3<br>+ subsystemid 0x17aa 0x21fe<br>+ end<br>+ device pci 1c.3 off end # PCIe Port #4<br>+ device pci 1c.4 off end # PCIe Port #5<br>+ device pci 1c.5 on # PCIe Port #6<br>+ subsystemid 0x17aa 0x21fe<br>+ end<br>+ device pci 1c.6 off end # PCIe Port #7<br>+ device pci 1c.7 off end # PCIe Port #8<br>+ device pci 1d.0 on # USB2 EHCI #1<br>+ subsystemid 0x17aa 0x21fe<br>+ end<br>+ device pci 1e.0 off end # PCI bridge<br>+ device pci 1f.0 on # LPC bridge PCI-LPC bridge<br>+ subsystemid 0x17aa 0x21fe<br>+ chip ec/lenovo/pmh7<br>+ register "backlight_enable" = "0x01"<br>+ register "dock_event_enable" = "0x00"<br>+ device pnp ff.1 on # dummy<br>+ end<br>+ end<br>+ chip ec/lenovo/h8<br>+ device pnp ff.2 on # dummy<br>+ io 0x60 = 0x62<br>+ io 0x62 = 0x66<br>+ io 0x64 = 0x1600<br>+ io 0x66 = 0x1604<br>+ end<br>+<br>+ register "config0" = "0xa6"<br>+ register "config1" = "0x0c"<br>+ register "config2" = "0xa0"<br>+ register "config3" = "0x62"<br>+<br>+ register "has_keyboard_backlight" = "0"<br>+<br>+ register "beepmask0" = "0x00" # 0x02?<br>+ register "beepmask1" = "0x86" # 0x87<br>+ register "has_power_management_beeps" = "0"<br>+<br>+ register "event0_enable" = "0xff"<br>+ register "event1_enable" = "0xff"<br>+ register "event2_enable" = "0xff"<br>+ register "event3_enable" = "0xff"<br>+ register "event4_enable" = "0xff"<br>+ register "event5_enable" = "0xff"<br>+ register "event6_enable" = "0xff"<br>+ register "event7_enable" = "0xff"<br>+ register "event8_enable" = "0xff"<br>+ register "event9_enable" = "0xff"<br>+ register "eventa_enable" = "0xff"<br>+ register "eventb_enable" = "0xff"<br>+ register "eventc_enable" = "0xff"<br>+ register "eventd_enable" = "0xff"<br>+ register "evente_enable" = "0xff"<br>+ register "eventf_enable" = "0xff"<br>+ end<br>+ end<br>+ device pci 1f.2 on # SATA Controller 1<br>+ subsystemid 0x17aa 0x21fe<br>+ end<br>+ device pci 1f.3 on # SMBus<br>+ subsystemid 0x17aa 0x21fe<br>+ # eeprom, 8 virtual devices, same chip<br>+ chip drivers/i2c/at24rf08c<br>+ device i2c 54 on end<br>+ device i2c 55 on end<br>+ device i2c 56 on end<br>+ device i2c 57 on end<br>+ device i2c 5c on end<br>+ device i2c 5d on end<br>+ device i2c 5e on end<br>+ device i2c 5f on end<br>+ end<br>+ end<br>+ device pci 1f.5 off end # SATA Controller 2<br>+ device pci 1f.6 off end # Thermal<br>+ end<br>+ end<br>+end<br>diff --git a/src/mainboard/lenovo/x131e/dsdt.asl b/src/mainboard/lenovo/x131e/dsdt.asl<br>new file mode 100644<br>index 0000000..b88a813<br>--- /dev/null<br>+++ b/src/mainboard/lenovo/x131e/dsdt.asl<br>@@ -0,0 +1,48 @@<br>+/*<br>+ * This file is part of the coreboot project.<br>+ *<br>+ * Copyright (C) 2007-2009 coresystems GmbH<br>+ * Copyright (C) 2011 The ChromiumOS Authors. All rights reserved.<br>+ * Copyright (C) 2014 Vladimir Serbinenko<br>+ * Copyright (C) 2017 James Ye <jye836@gmail.com><br>+ *<br>+ * This program is free software; you can redistribute it and/or modify<br>+ * it under the terms of the GNU General Public License as published by<br>+ * the Free Software Foundation; version 2 of the License.<br>+ *<br>+ * This program is distributed in the hope that it will be useful,<br>+ * but WITHOUT ANY WARRANTY; without even the implied warranty of<br>+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the<br>+ * GNU General Public License for more details.<br>+ */<br>+<br>+DefinitionBlock(<br>+ "dsdt.aml",<br>+ "DSDT",<br>+ 0x03, // DSDT revision: ACPI v3.0<br>+ "COREv4", // OEM id<br>+ "COREBOOT", // OEM table id<br>+ 0x20141018 // OEM revision<br>+)<br>+{<br>+ // Some generic macros<br>+ #include "acpi/platform.asl"<br>+ #include <cpu/intel/model_206ax/acpi/cpu.asl><br>+ #include <southbridge/intel/bd82x6x/acpi/platform.asl><br>+<br>+ // global NVS and variables<br>+ #include <southbridge/intel/bd82x6x/acpi/globalnvs.asl><br>+<br>+ // Chipset specific sleep states<br>+ #include <southbridge/intel/bd82x6x/acpi/sleepstates.asl><br>+<br>+ Scope (\_SB) {<br>+ Device (PCI0)<br>+ {<br>+ #include <northbridge/intel/sandybridge/acpi/sandybridge.asl><br>+ #include <drivers/intel/gma/acpi/default_brightness_levels.asl><br>+ #include <southbridge/intel/bd82x6x/acpi/pch.asl><br>+ #include <southbridge/intel/bd82x6x/acpi/default_irq_route.asl><br>+ }<br>+ }<br>+}<br>diff --git a/src/mainboard/lenovo/x131e/gma-mainboard.ads b/src/mainboard/lenovo/x131e/gma-mainboard.ads<br>new file mode 100644<br>index 0000000..736dce7<br>--- /dev/null<br>+++ b/src/mainboard/lenovo/x131e/gma-mainboard.ads<br>@@ -0,0 +1,20 @@<br>+with HW.GFX.GMA;<br>+with HW.GFX.GMA.Display_Probing;<br>+<br>+use HW.GFX.GMA;<br>+use HW.GFX.GMA.Display_Probing;<br>+<br>+private package GMA.Mainboard is<br>+<br>+ ports : constant Port_List :=<br>+ (DP1,<br>+ DP2,<br>+ DP3,<br>+ HDMI1,<br>+ HDMI2,<br>+ HDMI3,<br>+ Analog,<br>+ Internal,<br>+ others => Disabled);<br>+<br>+end GMA.Mainboard;<br>diff --git a/src/mainboard/lenovo/x131e/gpio.c b/src/mainboard/lenovo/x131e/gpio.c<br>new file mode 100644<br>index 0000000..f67fe87<br>--- /dev/null<br>+++ b/src/mainboard/lenovo/x131e/gpio.c<br>@@ -0,0 +1,229 @@<br>+/*<br>+ * This file is part of the coreboot project.<br>+ *<br>+ * Copyright (C) 2017 James Ye <jye836@gmail.com><br>+ *<br>+ * This program is free software; you can redistribute it and/or modify<br>+ * it under the terms of the GNU General Public License as published by<br>+ * the Free Software Foundation; version 2 of the License.<br>+ *<br>+ * This program is distributed in the hope that it will be useful,<br>+ * but WITHOUT ANY WARRANTY; without even the implied warranty of<br>+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the<br>+ * GNU General Public License for more details.<br>+ */<br>+<br>+#include <southbridge/intel/common/gpio.h><br>+<br>+const struct pch_gpio_set1 pch_gpio_set1_mode = {<br>+ .gpio0 = GPIO_MODE_GPIO,<br>+ .gpio1 = GPIO_MODE_GPIO,<br>+ .gpio2 = GPIO_MODE_GPIO,<br>+ .gpio3 = GPIO_MODE_GPIO,<br>+ .gpio4 = GPIO_MODE_GPIO,<br>+ .gpio5 = GPIO_MODE_GPIO,<br>+ .gpio6 = GPIO_MODE_GPIO,<br>+ .gpio7 = GPIO_MODE_GPIO,<br>+ .gpio8 = GPIO_MODE_GPIO,<br>+ .gpio12 = GPIO_MODE_GPIO,<br>+ .gpio13 = GPIO_MODE_GPIO,<br>+ .gpio15 = GPIO_MODE_GPIO,<br>+ .gpio16 = GPIO_MODE_GPIO,<br>+ .gpio17 = GPIO_MODE_GPIO,<br>+ .gpio19 = GPIO_MODE_GPIO,<br>+ .gpio21 = GPIO_MODE_GPIO,<br>+ .gpio22 = GPIO_MODE_GPIO,<br>+ .gpio23 = GPIO_MODE_GPIO,<br>+ .gpio24 = GPIO_MODE_GPIO,<br>+ .gpio27 = GPIO_MODE_GPIO,<br>+ .gpio28 = GPIO_MODE_GPIO,<br>+ .gpio29 = GPIO_MODE_GPIO,<br>+};<br>+<br>+const struct pch_gpio_set1 pch_gpio_set1_direction = {<br>+ .gpio1 = GPIO_DIR_INPUT,<br>+ .gpio6 = GPIO_DIR_INPUT,<br>+ .gpio7 = GPIO_DIR_INPUT,<br>+ .gpio9 = GPIO_DIR_INPUT,<br>+ .gpio10 = GPIO_DIR_INPUT,<br>+ .gpio11 = GPIO_DIR_INPUT,<br>+ .gpio14 = GPIO_DIR_INPUT,<br>+ .gpio15 = GPIO_DIR_INPUT,<br>+ .gpio18 = GPIO_DIR_INPUT,<br>+ .gpio20 = GPIO_DIR_INPUT,<br>+ .gpio22 = GPIO_DIR_INPUT,<br>+ .gpio25 = GPIO_DIR_INPUT,<br>+ .gpio26 = GPIO_DIR_INPUT,<br>+ .gpio27 = GPIO_DIR_INPUT,<br>+ .gpio31 = GPIO_DIR_INPUT,<br>+};<br>+<br>+const struct pch_gpio_set1 pch_gpio_set1_level = {<br>+ .gpio0 = GPIO_LEVEL_HIGH,<br>+ .gpio1 = GPIO_LEVEL_HIGH,<br>+ .gpio2 = GPIO_LEVEL_HIGH,<br>+ .gpio3 = GPIO_LEVEL_HIGH,<br>+ .gpio4 = GPIO_LEVEL_HIGH,<br>+ .gpio5 = GPIO_LEVEL_HIGH,<br>+ .gpio6 = GPIO_LEVEL_HIGH,<br>+ .gpio7 = GPIO_LEVEL_HIGH,<br>+ .gpio9 = GPIO_LEVEL_HIGH,<br>+ .gpio10 = GPIO_LEVEL_HIGH,<br>+ .gpio11 = GPIO_LEVEL_HIGH,<br>+ .gpio14 = GPIO_LEVEL_HIGH,<br>+ .gpio15 = GPIO_LEVEL_HIGH,<br>+ .gpio16 = GPIO_LEVEL_HIGH,<br>+ .gpio17 = GPIO_LEVEL_HIGH,<br>+ .gpio18 = GPIO_LEVEL_HIGH,<br>+ .gpio24 = GPIO_LEVEL_HIGH,<br>+ .gpio25 = GPIO_LEVEL_HIGH,<br>+ .gpio26 = GPIO_LEVEL_HIGH,<br>+ .gpio27 = GPIO_LEVEL_HIGH,<br>+ .gpio28 = GPIO_LEVEL_HIGH,<br>+ .gpio29 = GPIO_LEVEL_HIGH,<br>+ .gpio30 = GPIO_LEVEL_HIGH,<br>+ .gpio31 = GPIO_LEVEL_HIGH,<br>+};<br>+<br>+const struct pch_gpio_set1 pch_gpio_set1_reset = {<br>+ .gpio24 = GPIO_RESET_RSMRST,<br>+};<br>+<br>+const struct pch_gpio_set1 pch_gpio_set1_invert = {<br>+ .gpio1 = GPIO_INVERT,<br>+ .gpio6 = GPIO_INVERT,<br>+};<br>+<br>+const struct pch_gpio_set1 pch_gpio_set1_blink = {<br>+};<br>+<br>+const struct pch_gpio_set2 pch_gpio_set2_mode = {<br>+ .gpio33 = GPIO_MODE_GPIO,<br>+ .gpio34 = GPIO_MODE_GPIO,<br>+ .gpio35 = GPIO_MODE_GPIO,<br>+ .gpio36 = GPIO_MODE_GPIO,<br>+ .gpio37 = GPIO_MODE_GPIO,<br>+ .gpio38 = GPIO_MODE_GPIO,<br>+ .gpio39 = GPIO_MODE_GPIO,<br>+ .gpio40 = GPIO_MODE_GPIO,<br>+ .gpio41 = GPIO_MODE_GPIO,<br>+ .gpio48 = GPIO_MODE_GPIO,<br>+ .gpio49 = GPIO_MODE_GPIO,<br>+ .gpio51 = GPIO_MODE_GPIO,<br>+ .gpio53 = GPIO_MODE_GPIO,<br>+ .gpio54 = GPIO_MODE_GPIO,<br>+ .gpio57 = GPIO_MODE_GPIO,<br>+ .gpio59 = GPIO_MODE_GPIO,<br>+ .gpio60 = GPIO_MODE_GPIO,<br>+ .gpio61 = GPIO_MODE_GPIO,<br>+};<br>+<br>+const struct pch_gpio_set2 pch_gpio_set2_direction = {<br>+ .gpio36 = GPIO_DIR_INPUT,<br>+ .gpio37 = GPIO_DIR_INPUT,<br>+ .gpio38 = GPIO_DIR_INPUT,<br>+ .gpio39 = GPIO_DIR_INPUT,<br>+ .gpio40 = GPIO_DIR_INPUT,<br>+ .gpio41 = GPIO_DIR_INPUT,<br>+ .gpio42 = GPIO_DIR_INPUT,<br>+ .gpio43 = GPIO_DIR_INPUT,<br>+ .gpio44 = GPIO_DIR_INPUT,<br>+ .gpio45 = GPIO_DIR_INPUT,<br>+ .gpio46 = GPIO_DIR_INPUT,<br>+ .gpio47 = GPIO_DIR_INPUT,<br>+ .gpio49 = GPIO_DIR_INPUT,<br>+ .gpio50 = GPIO_DIR_INPUT,<br>+ .gpio52 = GPIO_DIR_INPUT,<br>+ .gpio54 = GPIO_DIR_INPUT,<br>+ .gpio56 = GPIO_DIR_INPUT,<br>+ .gpio57 = GPIO_DIR_INPUT,<br>+ .gpio58 = GPIO_DIR_INPUT,<br>+ .gpio59 = GPIO_DIR_INPUT,<br>+};<br>+<br>+const struct pch_gpio_set2 pch_gpio_set2_level = {<br>+ .gpio34 = GPIO_LEVEL_HIGH,<br>+ .gpio35 = GPIO_LEVEL_HIGH,<br>+ .gpio38 = GPIO_LEVEL_HIGH,<br>+ .gpio40 = GPIO_LEVEL_HIGH,<br>+ .gpio41 = GPIO_LEVEL_HIGH,<br>+ .gpio42 = GPIO_LEVEL_HIGH,<br>+ .gpio43 = GPIO_LEVEL_HIGH,<br>+ .gpio45 = GPIO_LEVEL_HIGH,<br>+ .gpio46 = GPIO_LEVEL_HIGH,<br>+ .gpio47 = GPIO_LEVEL_HIGH,<br>+ .gpio49 = GPIO_LEVEL_HIGH,<br>+ .gpio50 = GPIO_LEVEL_HIGH,<br>+ .gpio51 = GPIO_LEVEL_HIGH,<br>+ .gpio52 = GPIO_LEVEL_HIGH,<br>+ .gpio53 = GPIO_LEVEL_HIGH,<br>+ .gpio54 = GPIO_LEVEL_HIGH,<br>+ .gpio55 = GPIO_LEVEL_HIGH,<br>+ .gpio56 = GPIO_LEVEL_HIGH,<br>+ .gpio58 = GPIO_LEVEL_HIGH,<br>+ .gpio59 = GPIO_LEVEL_HIGH,<br>+ .gpio60 = GPIO_LEVEL_HIGH,<br>+ .gpio62 = GPIO_LEVEL_HIGH,<br>+ .gpio63 = GPIO_LEVEL_HIGH,<br>+};<br>+<br>+const struct pch_gpio_set2 pch_gpio_set2_reset = {<br>+};<br>+<br>+const struct pch_gpio_set3 pch_gpio_set3_mode = {<br>+ .gpio64 = GPIO_MODE_GPIO,<br>+ .gpio65 = GPIO_MODE_GPIO,<br>+ .gpio66 = GPIO_MODE_GPIO,<br>+ .gpio67 = GPIO_MODE_GPIO,<br>+ .gpio68 = GPIO_MODE_GPIO,<br>+ .gpio69 = GPIO_MODE_GPIO,<br>+ .gpio70 = GPIO_MODE_GPIO,<br>+ .gpio71 = GPIO_MODE_GPIO,<br>+ .gpio72 = GPIO_MODE_GPIO,<br>+};<br>+<br>+const struct pch_gpio_set3 pch_gpio_set3_direction = {<br>+ .gpio67 = GPIO_DIR_INPUT,<br>+ .gpio68 = GPIO_DIR_INPUT,<br>+ .gpio73 = GPIO_DIR_INPUT,<br>+ .gpio74 = GPIO_DIR_INPUT,<br>+ .gpio75 = GPIO_DIR_INPUT,<br>+};<br>+<br>+const struct pch_gpio_set3 pch_gpio_set3_level = {<br>+ .gpio64 = GPIO_LEVEL_HIGH,<br>+ .gpio66 = GPIO_LEVEL_HIGH,<br>+ .gpio68 = GPIO_LEVEL_HIGH,<br>+ .gpio70 = GPIO_LEVEL_HIGH,<br>+ .gpio71 = GPIO_LEVEL_HIGH,<br>+ .gpio72 = GPIO_LEVEL_HIGH,<br>+ .gpio73 = GPIO_LEVEL_HIGH,<br>+ .gpio74 = GPIO_LEVEL_HIGH,<br>+ .gpio75 = GPIO_LEVEL_HIGH,<br>+};<br>+<br>+const struct pch_gpio_set3 pch_gpio_set3_reset = {<br>+};<br>+<br>+const struct pch_gpio_map mainboard_gpio_map = {<br>+ .set1 = {<br>+ .mode = &pch_gpio_set1_mode,<br>+ .direction = &pch_gpio_set1_direction,<br>+ .level = &pch_gpio_set1_level,<br>+ .blink = &pch_gpio_set1_blink,<br>+ .invert = &pch_gpio_set1_invert,<br>+ .reset = &pch_gpio_set1_reset,<br>+ },<br>+ .set2 = {<br>+ .mode = &pch_gpio_set2_mode,<br>+ .direction = &pch_gpio_set2_direction,<br>+ .level = &pch_gpio_set2_level,<br>+ .reset = &pch_gpio_set2_reset,<br>+ },<br>+ .set3 = {<br>+ .mode = &pch_gpio_set3_mode,<br>+ .direction = &pch_gpio_set3_direction,<br>+ .level = &pch_gpio_set3_level,<br>+ .reset = &pch_gpio_set3_reset,<br>+ },<br>+};<br>diff --git a/src/mainboard/lenovo/x131e/hda_verb.c b/src/mainboard/lenovo/x131e/hda_verb.c<br>new file mode 100644<br>index 0000000..4b51b58<br>--- /dev/null<br>+++ b/src/mainboard/lenovo/x131e/hda_verb.c<br>@@ -0,0 +1,74 @@<br>+/*<br>+ * This file is part of the coreboot project.<br>+ *<br>+ * Copyright (C) 2017 James Ye <jye836@gmail.com><br>+ *<br>+ * This program is free software; you can redistribute it and/or modify<br>+ * it under the terms of the GNU General Public License as published by<br>+ * the Free Software Foundation; version 2 of the License.<br>+ *<br>+ * This program is distributed in the hope that it will be useful,<br>+ * but WITHOUT ANY WARRANTY; without even the implied warranty of<br>+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the<br>+ * GNU General Public License for more details.<br>+ */<br>+<br>+#include <device/azalia_device.h><br>+<br>+const u32 cim_verb_data[] = {<br>+ 0x10ec0269, /* Codec Vendor / Device ID: Realtek */<br>+ 0x17aa21fe, /* Subsystem ID */<br>+<br>+ 11, /* Number of 4 dword sets */<br>+ /* NID 0x01: Subsystem ID. */<br>+ AZALIA_SUBVENDOR(0x0, 0x17aa21fe),<br>+<br>+ /* NID 0x12. */<br>+ AZALIA_PIN_CFG(0x0, 0x12, 0x90a60930),<br>+<br>+ /* NID 0x14. */<br>+ AZALIA_PIN_CFG(0x0, 0x14, 0x90170110),<br>+<br>+ /* NID 0x15. */<br>+ AZALIA_PIN_CFG(0x0, 0x15, 0x0321101f),<br>+<br>+ /* NID 0x17. */<br>+ AZALIA_PIN_CFG(0x0, 0x17, 0x411111f0),<br>+<br>+ /* NID 0x18. */<br>+ AZALIA_PIN_CFG(0x0, 0x18, 0x03a11820),<br>+<br>+ /* NID 0x19. */<br>+ AZALIA_PIN_CFG(0x0, 0x19, 0x411111f0),<br>+<br>+ /* NID 0x1a. */<br>+ AZALIA_PIN_CFG(0x0, 0x1a, 0x411111f0),<br>+<br>+ /* NID 0x1b. */<br>+ AZALIA_PIN_CFG(0x0, 0x1b, 0x411111f0),<br>+<br>+ /* NID 0x1d. */<br>+ AZALIA_PIN_CFG(0x0, 0x1d, 0x4016862d),<br>+<br>+ /* NID 0x1e. */<br>+ AZALIA_PIN_CFG(0x0, 0x1e, 0x411111f0),<br>+ 0x80862806, /* Codec Vendor / Device ID: Intel */<br>+ 0x80860101, /* Subsystem ID */<br>+<br>+ 0x00000004, /* Number of 4 dword sets */<br>+ /* NID 0x01: Subsystem ID. */<br>+ AZALIA_SUBVENDOR(0x3, 0x80860101),<br>+<br>+ /* NID 0x05. */<br>+ AZALIA_PIN_CFG(0x3, 0x05, 0x18560010),<br>+<br>+ /* NID 0x06. */<br>+ AZALIA_PIN_CFG(0x3, 0x06, 0x58560020),<br>+<br>+ /* NID 0x07. */<br>+ AZALIA_PIN_CFG(0x3, 0x07, 0x58560030),<br>+};<br>+<br>+const u32 pc_beep_verbs[0] = {};<br>+<br>+AZALIA_ARRAY_SIZES;<br>diff --git a/src/mainboard/lenovo/x131e/mainboard.c b/src/mainboard/lenovo/x131e/mainboard.c<br>new file mode 100644<br>index 0000000..c68b956<br>--- /dev/null<br>+++ b/src/mainboard/lenovo/x131e/mainboard.c<br>@@ -0,0 +1,33 @@<br>+/*<br>+ * This file is part of the coreboot project.<br>+ *<br>+ * Copyright (C) 2017 James Ye <jye836@gmail.com><br>+ *<br>+ * This program is free software; you can redistribute it and/or modify<br>+ * it under the terms of the GNU General Public License as published by<br>+ * the Free Software Foundation; version 2 of the License.<br>+ *<br>+ * This program is distributed in the hope that it will be useful,<br>+ * but WITHOUT ANY WARRANTY; without even the implied warranty of<br>+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the<br>+ * GNU General Public License for more details.<br>+ */<br>+<br>+#include <device/device.h><br>+#include <drivers/intel/gma/int15.h><br>+#include <ec/lenovo/h8/h8.h><br>+<br>+static void mainboard_enable(device_t dev)<br>+{<br>+ install_intel_vga_int15_handler(GMA_INT15_ACTIVE_LFP_INT_LVDS,<br>+ GMA_INT15_PANEL_FIT_DEFAULT,<br>+ GMA_INT15_BOOT_DISPLAY_DEFAULT, 0);<br>+}<br>+<br>+void h8_mainboard_init_dock(void)<br>+{<br>+}<br>+<br>+struct chip_operations mainboard_ops = {<br>+ .enable_dev = mainboard_enable,<br>+};<br>diff --git a/src/mainboard/lenovo/x131e/romstage.c b/src/mainboard/lenovo/x131e/romstage.c<br>new file mode 100644<br>index 0000000..0ed1e0a<br>--- /dev/null<br>+++ b/src/mainboard/lenovo/x131e/romstage.c<br>@@ -0,0 +1,84 @@<br>+/*<br>+ * This file is part of the coreboot project.<br>+ *<br>+ * Copyright (C) 2007-2010 coresystems GmbH<br>+ * Copyright (C) 2011 The ChromiumOS Authors. All rights reserved.<br>+ * Copyright (C) 2017 James Ye <jye836@gmail.com><br>+ *<br>+ * This program is free software; you can redistribute it and/or modify<br>+ * it under the terms of the GNU General Public License as published by<br>+ * the Free Software Foundation; version 2 of the License.<br>+ *<br>+ * This program is distributed in the hope that it will be useful,<br>+ * but WITHOUT ANY WARRANTY; without even the implied warranty of<br>+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the<br>+ * GNU General Public License for more details.<br>+ */<br>+<br>+#include <stdint.h><br>+#include <string.h><br>+#include <lib.h><br>+#include <timestamp.h><br>+#include <arch/byteorder.h><br>+#include <arch/io.h><br>+#include <device/pci_def.h><br>+#include <device/pnp_def.h><br>+#include <cpu/x86/lapic.h><br>+#include <arch/acpi.h><br>+#include <console/console.h><br>+#include "northbridge/intel/sandybridge/sandybridge.h"<br>+#include "northbridge/intel/sandybridge/raminit_native.h"<br>+#include "southbridge/intel/bd82x6x/pch.h"<br>+#include <southbridge/intel/common/gpio.h><br>+#include <arch/cpu.h><br>+#include <cpu/x86/msr.h><br>+<br>+void pch_enable_lpc(void)<br>+{<br>+ pci_write_config16(PCI_DEV(0, 0x1f, 0), 0x82, 0x3f0f);<br>+ pci_write_config32(PCI_DEV(0, 0x1f, 0), 0x84, 0x007c1611);<br>+ pci_write_config32(PCI_DEV(0, 0x1f, 0), 0x88, 0x00040069);<br>+ pci_write_config32(PCI_DEV(0, 0x1f, 0), 0x8c, 0x000c0701);<br>+ pci_write_config32(PCI_DEV(0, 0x1f, 0), 0x90, 0x000c06a1);<br>+ pci_write_config16(PCI_DEV(0, 0x1f, 0), 0x80, 0x0010);<br>+ pci_write_config32(PCI_DEV(0, 0x1f, 0), 0xac, 0x80010000);<br>+}<br>+<br>+void rcba_config(void)<br>+{<br>+ /* Disable devices. */<br>+ RCBA32(FD) = 0;<br>+ RCBA32(BUC) = 0;<br>+}<br>+<br>+const struct southbridge_usb_port mainboard_usb_ports[] = {<br>+ /* enabled usb oc pin length */<br>+ {1, 0, 0}, /* P0: USB 3.0 1 (OC0) */<br>+ {1, 0, 0}, /* P1: USB 3.0 2 (OC0) */<br>+ {0, 0, 0}, /* P2: Empty */<br>+ {1, 0, -1}, /* P3: Camera (no OC) */<br>+ {1, 0, -1}, /* P4: WLAN (no OC) */<br>+ {1, 0, -1}, /* P5: WWAN (no OC) */<br>+ {0, 0, 0}, /* P6: Empty */<br>+ {0, 0, 0}, /* P7: Empty */<br>+ {0, 0, 0}, /* P8: Empty */<br>+ {1, 0, 4}, /* P9: USB 2.0 (AUO4) (OC4) */<br>+ {0, 0, 0}, /* P10: Empty */<br>+ {0, 0, 0}, /* P11: Empty */<br>+ {0, 0, 0}, /* P12: Empty */<br>+ {1, 0, -1}, /* P13: Bluetooth (no OC) */<br>+};<br>+<br>+void mainboard_get_spd(spd_raw_data *spd, bool id_only)<br>+{<br>+ read_spd(&spd[0], 0x50, id_only);<br>+ read_spd(&spd[2], 0x51, id_only);<br>+}<br>+<br>+void mainboard_early_init(int s3resume)<br>+{<br>+}<br>+<br>+void mainboard_config_superio(void)<br>+{<br>+}<br>diff --git a/src/mainboard/lenovo/x131e/smihandler.c b/src/mainboard/lenovo/x131e/smihandler.c<br>new file mode 100644<br>index 0000000..b8b38fc<br>--- /dev/null<br>+++ b/src/mainboard/lenovo/x131e/smihandler.c<br>@@ -0,0 +1,86 @@<br>+/*<br>+ * This file is part of the coreboot project.<br>+ *<br>+ * Copyright (C) 2008-2009 coresystems GmbH<br>+ * Copyright (C) 2014 Vladimir Serbinenko<br>+ * Copyright (C) 2017 James Ye <jye836@gmail.com><br>+ *<br>+ * This program is free software; you can redistribute it and/or<br>+ * modify it under the terms of the GNU General Public License as<br>+ * published by the Free Software Foundation; version 2 of<br>+ * the License.<br>+ *<br>+ * This program is distributed in the hope that it will be useful,<br>+ * but WITHOUT ANY WARRANTY; without even the implied warranty of<br>+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the<br>+ * GNU General Public License for more details.<br>+ */<br>+<br>+#include <arch/io.h><br>+#include <console/console.h><br>+#include <cpu/x86/smm.h><br>+#include <ec/acpi/ec.h><br>+#include <ec/lenovo/h8/h8.h><br>+#include <delay.h><br>+#include <southbridge/intel/bd82x6x/pch.h><br>+<br>+#define GPE_EC_SCI 6<br>+#define GPE_EC_WAKE 13<br>+<br>+static void mainboard_smi_handle_ec_sci(void)<br>+{<br>+ u8 status = inb(EC_SC);<br>+ u8 event;<br>+<br>+ if (!(status & EC_SCI_EVT))<br>+ return;<br>+<br>+ event = ec_query();<br>+ printk(BIOS_DEBUG, "EC event %02x\n", event);<br>+}<br>+<br>+void mainboard_smi_gpi(u32 gpi_sts)<br>+{<br>+ if (gpi_sts & (1 << GPE_EC_SCI))<br>+ mainboard_smi_handle_ec_sci();<br>+}<br>+<br>+int mainboard_smi_apmc(u8 data)<br>+{<br>+ switch (data) {<br>+ case APM_CNT_ACPI_ENABLE:<br>+ /* use 0x1600/0x1604 to prevent races with userspace */<br>+ ec_set_ports(0x1604, 0x1600);<br>+ /* route EC_SCI to SCI */<br>+ gpi_route_interrupt(GPE_EC_SCI, GPI_IS_SCI);<br>+ /* discard all events, and enable attention */<br>+ ec_write(0x80, 0x01);<br>+ break;<br>+ case APM_CNT_ACPI_DISABLE:<br>+ /* we have to use port 0x62/0x66, as 0x1600/0x1604 doesn't<br>+ provide a EC query function */<br>+ ec_set_ports(0x66, 0x62);<br>+ /* route EC_SCI to SMI */<br>+ gpi_route_interrupt(GPE_EC_SCI, GPI_IS_SMI);<br>+ /* discard all events, and enable attention */<br>+ ec_write(0x80, 0x01);<br>+ break;<br>+ default:<br>+ break;<br>+ }<br>+ return 0;<br>+}<br>+<br>+void mainboard_smi_sleep(u8 slp_typ)<br>+{<br>+ h8_usb_always_on();<br>+<br>+ if (slp_typ == 3) {<br>+ u8 ec_wake = ec_read(0x32);<br>+ /* If EC wake events are enabled, enable wake on EC WAKE GPE. */<br>+ if (ec_wake & 0x14) {<br>+ /* Redirect EC WAKE GPE to SCI. */<br>+ gpi_route_interrupt(GPE_EC_WAKE, GPI_IS_SCI);<br>+ }<br>+ }<br>+}<br>diff --git a/src/mainboard/lenovo/x131e/thermal.h b/src/mainboard/lenovo/x131e/thermal.h<br>new file mode 100644<br>index 0000000..ff92869<br>--- /dev/null<br>+++ b/src/mainboard/lenovo/x131e/thermal.h<br>@@ -0,0 +1,28 @@<br>+/*<br>+ * This file is part of the coreboot project.<br>+ *<br>+ * Copyright (C) 2011 The Chromium OS Authors. All rights reserved.<br>+ * Copyright (C) 2017 James Ye <jye836@gmail.com><br>+ *<br>+ * This program is free software; you can redistribute it and/or modify<br>+ * it under the terms of the GNU General Public License as published by<br>+ * the Free Software Foundation; version 2 of the License.<br>+ *<br>+ * This program is distributed in the hope that it will be useful,<br>+ * but WITHOUT ANY WARRANTY; without even the implied warranty of<br>+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the<br>+ * GNU General Public License for more details.<br>+ */<br>+<br>+#ifndef X131E_THERMAL_H<br>+#define X131E_THERMAL_H<br>+<br>+/* Active Thermal and fans are controlled by the EC. */<br>+<br>+/* Temperature which OS will shutdown at */<br>+#define CRITICAL_TEMPERATURE 100<br>+<br>+/* Temperature which OS will throttle CPU */<br>+#define PASSIVE_TEMPERATURE 90<br>+<br>+#endif /* X131E_THERMAL_H */<br></pre><p>To view, visit <a href="https://review.coreboot.org/20694">change 20694</a>. To unsubscribe, visit <a href="https://review.coreboot.org/settings">settings</a>.</p><div itemscope itemtype="http://schema.org/EmailMessage"><div itemscope itemprop="action" itemtype="http://schema.org/ViewAction"><link itemprop="url" href="https://review.coreboot.org/20694"/><meta itemprop="name" content="View Change"/></div></div>
<div style="display:none"> Gerrit-Project: coreboot </div>
<div style="display:none"> Gerrit-Branch: master </div>
<div style="display:none"> Gerrit-MessageType: newchange </div>
<div style="display:none"> Gerrit-Change-Id: If8de3a9308997e2d57aee869023ee9a43a2db872 </div>
<div style="display:none"> Gerrit-Change-Number: 20694 </div>
<div style="display:none"> Gerrit-PatchSet: 1 </div>
<div style="display:none"> Gerrit-Owner: James <jye836@gmail.com> </div>