<p>Martin Roth would like Lijian Zhao to <strong>review</strong> this change.</p><p><a href="https://review.coreboot.org/20687">View Change</a></p><pre style="font-family: monospace,monospace; white-space: pre-wrap;">soc/intel/cannonlake: Call into FSP siliconinit<br><br>The following changes can make system call into FSP siliconinit and exit<br>from that until payloads.<br><br>1. Add frame to call fspsinit.<br>2. Temporarily set all the USB OC pin to 0 to pass FSP siliconinit.<br><br>This patch was merged too early, and reverted.<br>Originally reviewed on https://review.coreboot.org/#/c/20581<br><br>Change-Id: I14eeba575af1658ff8013c9a00bd71013566bcbe<br>Signed-off-by: Lijian Zhao <lijian.zhao@intel.com><br>---<br>M src/soc/intel/cannonlake/Makefile.inc<br>A src/soc/intel/cannonlake/chip.c<br>A src/soc/intel/cannonlake/chip.h<br>A src/soc/intel/cannonlake/include/soc/ramstage.h<br>4 files changed, 117 insertions(+), 1 deletion(-)<br><br></pre><pre style="font-family: monospace,monospace; white-space: pre-wrap;">git pull ssh://review.coreboot.org:29418/coreboot refs/changes/87/20687/1</pre><pre style="font-family: monospace,monospace; white-space: pre-wrap;">diff --git a/src/soc/intel/cannonlake/Makefile.inc b/src/soc/intel/cannonlake/Makefile.inc<br>index 2549e4c..4de5814 100644<br>--- a/src/soc/intel/cannonlake/Makefile.inc<br>+++ b/src/soc/intel/cannonlake/Makefile.inc<br>@@ -16,7 +16,8 @@<br> romstage-y += reset.c<br> romstage-$(CONFIG_UART_DEBUG) += uart.c<br> <br>-ramstage-y += cbmem.c<br>+ramstage-y += chip.c<br>+ramstage-y += memmap.c<br> ramstage-$(CONFIG_PLATFORM_USES_FSP2_0) += reset.c<br> ramstage-$(CONFIG_UART_DEBUG) += uart.c<br> <br>diff --git a/src/soc/intel/cannonlake/chip.c b/src/soc/intel/cannonlake/chip.c<br>new file mode 100644<br>index 0000000..2f893e3<br>--- /dev/null<br>+++ b/src/soc/intel/cannonlake/chip.c<br>@@ -0,0 +1,59 @@<br>+/*<br>+ * This file is part of the coreboot project.<br>+ *<br>+ * Copyright (C) 2016-2017 Intel Corporation.<br>+ *<br>+ * This program is free software; you can redistribute it and/or modify<br>+ * it under the terms of the GNU General Public License as published by<br>+ * the Free Software Foundation; version 2 of the License.<br>+ *<br>+ * This program is distributed in the hope that it will be useful,<br>+ * but WITHOUT ANY WARRANTY; without even the implied warranty of<br>+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the<br>+ * GNU General Public License for more details.<br>+ */<br>+<br>+#include <chip.h><br>+#include <console/console.h><br>+#include <device/pci.h><br>+#include <fsp/api.h><br>+#include <fsp/api.h><br>+#include <fsp/util.h><br>+#include <romstage_handoff.h><br>+#include <soc/ramstage.h><br>+#include <string.h><br>+<br>+void soc_init_pre_device(void *chip_info)<br>+{<br>+ /* Perform silicon specific init. */<br>+ fsp_silicon_init(romstage_handoff_is_resume());<br>+}<br>+<br>+struct chip_operations soc_intel_cannonlake_ops = {<br>+ CHIP_NAME("Intel Cannonlake")<br>+ .init = &soc_init_pre_device,<br>+};<br>+<br>+/* UPD parameters to be initialized before SiliconInit */<br>+void platform_fsp_silicon_init_params_cb(FSPS_UPD *supd)<br>+{<br>+ int i;<br>+ FSP_S_CONFIG *params = &supd->FspsConfig;<br>+<br>+ /* Set USB OC pin to 0 first */<br>+ for (i = 0; i < ARRAY_SIZE(params->Usb2OverCurrentPin); i++) {<br>+ params->Usb2OverCurrentPin[i] = 0;<br>+ }<br>+<br>+ for (i = 0; i < ARRAY_SIZE(params->Usb3OverCurrentPin); i++) {<br>+ params->Usb3OverCurrentPin[i] = 0;<br>+ }<br>+<br>+ mainboard_silicon_init_params(params);<br>+}<br>+<br>+/* Mainboard GPIO Configuration */<br>+__attribute__((weak)) void mainboard_silicon_init_params(FSP_S_CONFIG *params)<br>+{<br>+ printk(BIOS_DEBUG, "WEAK: %s/%s called\n", __FILE__, __func__);<br>+}<br>diff --git a/src/soc/intel/cannonlake/chip.h b/src/soc/intel/cannonlake/chip.h<br>new file mode 100644<br>index 0000000..bbc5880<br>--- /dev/null<br>+++ b/src/soc/intel/cannonlake/chip.h<br>@@ -0,0 +1,28 @@<br>+/*<br>+ * This file is part of the coreboot project.<br>+ *<br>+ * Copyright (C) 2007-2008 coresystems GmbH<br>+ * Copyright (C) 2014 Google Inc.<br>+ * Copyright (C) 2017 Intel Corporation.<br>+ *<br>+ * This program is free software; you can redistribute it and/or modify<br>+ * it under the terms of the GNU General Public License as published by<br>+ * the Free Software Foundation; version 2 of the License.<br>+ *<br>+ * This program is distributed in the hope that it will be useful,<br>+ * but WITHOUT ANY WARRANTY; without even the implied warranty of<br>+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the<br>+ * GNU General Public License for more details.<br>+ */<br>+<br>+#ifndef _SOC_CHIP_H_<br>+#define _SOC_CHIP_H_<br>+<br>+#include <stdint.h><br>+<br>+struct soc_intel_cannonlake_config {<br>+};<br>+<br>+typedef struct soc_intel_cannonlake_config config_t;<br>+<br>+#endif<br>diff --git a/src/soc/intel/cannonlake/include/soc/ramstage.h b/src/soc/intel/cannonlake/include/soc/ramstage.h<br>new file mode 100644<br>index 0000000..4a96185<br>--- /dev/null<br>+++ b/src/soc/intel/cannonlake/include/soc/ramstage.h<br>@@ -0,0 +1,28 @@<br>+/*<br>+ * This file is part of the coreboot project.<br>+ *<br>+ * Copyright (C) 2014 Google Inc.<br>+ * Copyright (C) 2015-2017 Intel Corporation.<br>+ *<br>+ * This program is free software; you can redistribute it and/or modify<br>+ * it under the terms of the GNU General Public License as published by<br>+ * the Free Software Foundation; version 2 of the License.<br>+ *<br>+ * This program is distributed in the hope that it will be useful,<br>+ * but WITHOUT ANY WARRANTY; without even the implied warranty of<br>+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the<br>+ * GNU General Public License for more details.<br>+ */<br>+<br>+#ifndef _SOC_RAMSTAGE_H_<br>+#define _SOC_RAMSTAGE_H_<br>+<br>+#include <chip.h><br>+#include <device/device.h><br>+#include <fsp/api.h><br>+#include <fsp/util.h><br>+<br>+void mainboard_silicon_init_params(FSP_S_CONFIG *params);<br>+void soc_init_pre_device(void *chip_info);<br>+<br>+#endif<br></pre><p>To view, visit <a href="https://review.coreboot.org/20687">change 20687</a>. To unsubscribe, visit <a href="https://review.coreboot.org/settings">settings</a>.</p><div itemscope itemtype="http://schema.org/EmailMessage"><div itemscope itemprop="action" itemtype="http://schema.org/ViewAction"><link itemprop="url" href="https://review.coreboot.org/20687"/><meta itemprop="name" content="View Change"/></div></div>
<div style="display:none"> Gerrit-Project: coreboot </div>
<div style="display:none"> Gerrit-Branch: master </div>
<div style="display:none"> Gerrit-MessageType: newchange </div>
<div style="display:none"> Gerrit-Change-Id: I14eeba575af1658ff8013c9a00bd71013566bcbe </div>
<div style="display:none"> Gerrit-Change-Number: 20687 </div>
<div style="display:none"> Gerrit-PatchSet: 1 </div>
<div style="display:none"> Gerrit-Owner: Martin Roth <martinroth@google.com> </div>
<div style="display:none"> Gerrit-Reviewer: Lijian Zhao <lijian.zhao@intel.com> </div>