<p>Ravishankar Sarawadi has uploaded this change for <strong>review</strong>.</p><p><a href="https://review.coreboot.org/20673">View Change</a></p><pre style="font-family: monospace,monospace; white-space: pre-wrap;">vendorcode/intel/fsp/fsp2_0/glk: Update header files as per v52_27<br><br>Update glk header files as per v52_27 FSP code.<br><br>Change-Id: I8e313a2b854e60b1ad8a5c6e080641e323de56a8<br>Signed-off-by: Ravi Sarawadi <ravishankar.sarawadi@intel.com><br>---<br>M src/vendorcode/intel/fsp/fsp2_0/glk/FspUpd.h<br>M src/vendorcode/intel/fsp/fsp2_0/glk/FspmUpd.h<br>M src/vendorcode/intel/fsp/fsp2_0/glk/FspsUpd.h<br>3 files changed, 2,807 insertions(+), 2,645 deletions(-)<br><br></pre><pre style="font-family: monospace,monospace; white-space: pre-wrap;">git pull ssh://review.coreboot.org:29418/coreboot refs/changes/73/20673/1</pre><pre style="font-family: monospace,monospace; white-space: pre-wrap;">diff --git a/src/vendorcode/intel/fsp/fsp2_0/glk/FspUpd.h b/src/vendorcode/intel/fsp/fsp2_0/glk/FspUpd.h<br>index d1bb1fc..b2ec214 100644<br>--- a/src/vendorcode/intel/fsp/fsp2_0/glk/FspUpd.h<br>+++ b/src/vendorcode/intel/fsp/fsp2_0/glk/FspUpd.h<br>@@ -1,48 +1,48 @@<br>-/** @file<br>-<br>-Copyright (c) 2017, Intel Corporation. All rights reserved.<BR><br>-<br>-Redistribution and use in source and binary forms, with or without modification,<br>-are permitted provided that the following conditions are met:<br>-<br>-* Redistributions of source code must retain the above copyright notice, this<br>- list of conditions and the following disclaimer.<br>-* Redistributions in binary form must reproduce the above copyright notice, this<br>- list of conditions and the following disclaimer in the documentation and/or<br>- other materials provided with the distribution.<br>-* Neither the name of Intel Corporation nor the names of its contributors may<br>- be used to endorse or promote products derived from this software without<br>- specific prior written permission.<br>-<br>- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"<br>- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE<br>- IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE<br>- ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE<br>- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR<br>- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF<br>- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS<br>- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN<br>- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)<br>- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF<br>- THE POSSIBILITY OF SUCH DAMAGE.<br>-<br>- This file is automatically generated. Please do NOT modify !!!<br>-<br>-**/<br>-<br>-#ifndef __FSPUPD_H__<br>-#define __FSPUPD_H__<br>-<br>-#include <FspEas.h><br>-<br>-#pragma pack(push, 1)<br>-<br>-#define FSPT_UPD_SIGNATURE 0x545F4450554C5041 /* 'APLUPD_T' */<br>-<br>-#define FSPM_UPD_SIGNATURE 0x4D5F4450554C5041 /* 'APLUPD_M' */<br>-<br>-#define FSPS_UPD_SIGNATURE 0x535F4450554C5041 /* 'APLUPD_S' */<br>-<br>-#pragma pack(pop)<br>-<br>-#endif<br>+/** @file<br>+<br>+Copyright (c) 2017, Intel Corporation. All rights reserved.<BR><br>+<br>+Redistribution and use in source and binary forms, with or without modification,<br>+are permitted provided that the following conditions are met:<br>+<br>+* Redistributions of source code must retain the above copyright notice, this<br>+ list of conditions and the following disclaimer.<br>+* Redistributions in binary form must reproduce the above copyright notice, this<br>+ list of conditions and the following disclaimer in the documentation and/or<br>+ other materials provided with the distribution.<br>+* Neither the name of Intel Corporation nor the names of its contributors may<br>+ be used to endorse or promote products derived from this software without<br>+ specific prior written permission.<br>+<br>+ THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"<br>+ AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE<br>+ IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE<br>+ ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE<br>+ LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR<br>+ CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF<br>+ SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS<br>+ INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN<br>+ CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)<br>+ ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF<br>+ THE POSSIBILITY OF SUCH DAMAGE.<br>+<br>+ This file is automatically generated. Please do NOT modify !!!<br>+<br>+**/<br>+<br>+#ifndef __FSPUPD_H__<br>+#define __FSPUPD_H__<br>+<br>+#include <FspEas.h><br>+<br>+#pragma pack(1)<br>+<br>+#define FSPT_UPD_SIGNATURE 0x545F4450554B4C47 /* 'GLKUPD_T' */<br>+<br>+#define FSPM_UPD_SIGNATURE 0x4D5F4450554B4C47 /* 'GLKUPD_M' */<br>+<br>+#define FSPS_UPD_SIGNATURE 0x535F4450554B4C47 /* 'GLKUPD_S' */<br>+<br>+#pragma pack()<br>+<br>+#endif<br>diff --git a/src/vendorcode/intel/fsp/fsp2_0/glk/FspmUpd.h b/src/vendorcode/intel/fsp/fsp2_0/glk/FspmUpd.h<br>index 2619171..cf856e1 100644<br>--- a/src/vendorcode/intel/fsp/fsp2_0/glk/FspmUpd.h<br>+++ b/src/vendorcode/intel/fsp/fsp2_0/glk/FspmUpd.h<br>@@ -1,889 +1,1027 @@<br>-/** @file<br>-<br>-Copyright (c) 2017, Intel Corporation. All rights reserved.<BR><br>-<br>-Redistribution and use in source and binary forms, with or without modification,<br>-are permitted provided that the following conditions are met:<br>-<br>-* Redistributions of source code must retain the above copyright notice, this<br>- list of conditions and the following disclaimer.<br>-* Redistributions in binary form must reproduce the above copyright notice, this<br>- list of conditions and the following disclaimer in the documentation and/or<br>- other materials provided with the distribution.<br>-* Neither the name of Intel Corporation nor the names of its contributors may<br>- be used to endorse or promote products derived from this software without<br>- specific prior written permission.<br>-<br>- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"<br>- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE<br>- IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE<br>- ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE<br>- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR<br>- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF<br>- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS<br>- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN<br>- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)<br>- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF<br>- THE POSSIBILITY OF SUCH DAMAGE.<br>-<br>- This file is automatically generated. Please do NOT modify !!!<br>-<br>-**/<br>-<br>-#ifndef __FSPMUPD_H__<br>-#define __FSPMUPD_H__<br>-<br>-#include <FspUpd.h><br>-<br>-#pragma pack(push, 1)<br>-<br>-<br>-#define MAX_CHANNELS_NUM 4<br>-#define MAX_DIMMS_NUM 1<br>-<br>-typedef struct {<br>- UINT8 DimmId;<br>- UINT32 SizeInMb;<br>- UINT16 MfgId;<br>- /** Module part number for DRR3 is 18 bytes<br>- but DRR4 is 20 bytes as per JEDEC Spec, so<br>- reserving 20 bytes **/<br>- UINT8 ModulePartNum[20];<br>-} DIMM_INFO;<br>-<br>-typedef struct {<br>- UINT8 ChannelId;<br>- UINT8 DimmCount;<br>- DIMM_INFO DimmInfo[MAX_DIMMS_NUM];<br>-} CHANNEL_INFO;<br>-<br>-typedef struct {<br>- UINT8 Revision;<br>- UINT8 DataWidth;<br>- /** As defined in SMBIOS 3.0 spec<br>- Section 7.18.2 and Table 75<br>- **/<br>- UINT16 MemoryType;<br>- UINT16 MemoryFrequencyInMHz;<br>- /** As defined in SMBIOS 3.0 spec<br>- Section 7.17.3 and Table 72<br>- **/<br>- UINT8 ErrorCorrectionType;<br>- UINT8 ChannelCount;<br>- CHANNEL_INFO ChannelInfo[MAX_CHANNELS_NUM];<br>-} FSP_SMBIOS_MEMORY_INFO;<br>-<br>-<br>-/** Fsp M Configuration<br>-**/<br>-typedef struct {<br>-<br>-/** Offset 0x0040 - Debug Serial Port Base address<br>- Debug serial port base address. This option will be used only when the 'Serial Port<br>- Debug Device' option is set to 'External Device'. 0x00000000(Default).<br>-**/<br>- UINT32 SerialDebugPortAddress;<br>-<br>-/** Offset 0x0044 - Debug Serial Port Type<br>- 16550 compatible debug serial port resource type. NONE means no serial port support.<br>- 0x02:MMIO(Default).<br>- 0:NONE, 1:I/O, 2:MMIO<br>-**/<br>- UINT8 SerialDebugPortType;<br>-<br>-/** Offset 0x0045 - Serial Port Debug Device<br>- Select active serial port device for debug. For SOC UART devices,'Debug Serial Port<br>- Base' options will be ignored. 0x02:SOC UART2(Default).<br>- 0:SOC UART0, 1:SOC UART1, 2:SOC UART2, 3:External Device<br>-**/<br>- UINT8 SerialDebugPortDevice;<br>-<br>-/** Offset 0x0046 - Debug Serial Port Stride Size<br>- Debug serial port register map stride size in bytes. 0x00:1, 0x02:4(Default).<br>- 0:1, 2:4<br>-**/<br>- UINT8 SerialDebugPortStrideSize;<br>-<br>-/** Offset 0x0047 - Memory Fast Boot<br>- Enable/Disable MRC fast boot support. 0x00:Disable, 0x01:Enable(Default).<br>- $EN_DIS<br>-**/<br>- UINT8 MrcFastBoot;<br>-<br>-/** Offset 0x0048 - Integrated Graphics Device<br>- Enable : Enable Integrated Graphics Device (IGD) when selected as the Primary Video<br>- Adaptor. Disable: Always disable IGD. 0x00:Disable, 0x01:Enable(Default).<br>- $EN_DIS<br>-**/<br>- UINT8 Igd;<br>-<br>-/** Offset 0x0049 - DVMT Pre-Allocated<br>- Select DVMT 5.0 Pre-Allocated (Fixed) Graphics Memory size used by the Internal<br>- Graphics Device. 0x02:64 MB(Default).<br>- 0x02:64 MB, 0x03:96 MB, 0x04:128 MB, 0x05:160 MB, 0x06:192 MB, 0x07:224 MB, 0x08:256<br>- MB, 0x09:288 MB, 0x0A:320 MB, 0x0B:352 MB, 0x0C:384 MB, 0x0D:416 MB, 0x0E:448 MB,<br>- 0x0F:480 MB, 0x10:512 MB<br>-**/<br>- UINT8 IgdDvmt50PreAlloc;<br>-<br>-/** Offset 0x004A - Aperture Size<br>- Select the Aperture Size used by the Internal Graphics Device. 0x1:128 MB(Default),<br>- 0x2:256 MB, 0x3:512 MB.<br>- 0x1:128 MB, 0x2:256 MB, 0x3:512 MB<br>-**/<br>- UINT8 IgdApertureSize;<br>-<br>-/** Offset 0x004B - GTT Size<br>- Select the GTT Size used by the Internal Graphics Device. 0x1:2 MB, 0x2:4 MB, 0x3:8<br>- MB(Default).<br>- 0x1:2 MB, 0x2:4 MB, 0x3:8 MB<br>-**/<br>- UINT8 GttSize;<br>-<br>-/** Offset 0x004C - Primary Display<br>- Select which of IGD/PCI Graphics device should be Primary Display. 0x0:AUTO(Default),<br>- 0x2:IGD, 0x3:PCI<br>- 0x0:AUTO, 0x2:IGD, 0x3:PCI<br>-**/<br>- UINT8 PrimaryVideoAdaptor;<br>-<br>-/** Offset 0x004D - Package<br>- NOTE: Specifies CA Mapping for all technologies. Supported CA Mappings: 0 - SODIMM(Default);<br>- 1 - BGA; 2 - BGA mirrored (LPDDR3 only); 3 - SODIMM/UDIMM with Rank 1 Mirrored<br>- (DDR3L); Refer to the IAFW spec for specific details about each CA mapping.<br>- 0x0:SODIMM, 0x1:BGA, 0x2:BGA mirrored (LPDDR3 only), 0x3:SODIMM/UDIMM with Rank<br>- 1 Mirrored (DDR3L)<br>-**/<br>- UINT8 Package;<br>-<br>-/** Offset 0x004E - Profile<br>- Profile list. 0x19(Default).<br>- 0x1:WIO2_800_7_8_8, 0x2:WIO2_1066_9_10_10, 0x3:LPDDR3_1066_8_10_10, 0x4:LPDDR3_1333_10_12_12,<br>- 0x5:LPDDR3_1600_12_15_15, 0x6:LPDDR3_1866_14_17_17, 0x7:LPDDR3_2133_16_20_20, 0x8:LPDDR4_1066_10_10_10,<br>- 0x9:LPDDR4_1600_14_15_15, 0xA:LPDDR4_2133_20_20_20, 0xB:LPDDR4_2400_24_22_22, 0xC:LPDDR4_2666_24_24_24,<br>- 0xD:LPDDR4_2933_28_27_27, 0xE:LPDDR4_3200_28_29_29, 0xF:DDR3_1066_6_6_6, 0x10:DDR3_1066_7_7_7,<br>- 0x11:DDR3_1066_8_8_8, 0x12:DDR3_1333_7_7_7, 0x13:DDR3_1333_8_8_8, 0x14:DDR3_1333_9_9_9,<br>- 0x15:DDR3_1333_10_10_10, 0x16:DDR3_1600_8_8_8, 0x17:DDR3_1600_9_9_9, 0x18:DDR3_1600_10_10_10,<br>- 0x19:DDR3_1600_11_11_11, 0x1A:DDR3_1866_10_10_10, 0x1B:DDR3_1866_11_11_11, 0x1C:DDR3_1866_12_12_12,<br>- 0x1D:DDR3_1866_13_13_13, 0x1E:DDR3_2133_11_11_11, 0x1F:DDR3_2133_12_12_12, 0x20:DDR3_2133_13_13_13,<br>- 0x21:DDR3_2133_14_14_14, 0x22:DDR4_1333_10_10_10, 0x23:DDR4_1600_10_10_10, 0x24:DDR4_1600_11_11_11,<br>- 0x25:DDR4_1600_12_12_12, 0x26:DDR4_1866_12_12_12, 0x27:DDR4_1866_13_13_13, 0x28:DDR4_1866_14_14_14,<br>- 0x29:DDR4_2133_14_14_14, 0x2A:DDR4_2133_15_15_15, 0x2B:DDR4_2133_16_16_16, 0x2C:DDR4_2400_15_15_15,<br>- 0x2D:DDR4_2400_16_16_16, 0x2E:DDR4_2400_17_17_17, 0x2F:DDR4_2400_18_18_18<br>-**/<br>- UINT8 Profile;<br>-<br>-/** Offset 0x004F - MemoryDown<br>- Memory Down. 0x0(Default).<br>- 0x0:No, 0x1:Yes, 0x2:1MD+SODIMM (for DDR3L only) ACRD, 0x3:1x32 LPDDR4<br>-**/<br>- UINT8 MemoryDown;<br>-<br>-/** Offset 0x0050 - DDR3LPageSize<br>- NOTE: Only for memory down (soldered down memory with no SPD). 0x01:1KB(Default), 0x02:2KB.<br>- 0x1:1KB, 0x2:2KB<br>-**/<br>- UINT8 DDR3LPageSize;<br>-<br>-/** Offset 0x0051 - DDR3LASR<br>- NOTE: Only for memory down. This is specific to ddr3l and used for refresh adjustment<br>- in Self Refresh, does not affect LP4. 0x00:Not Supported(Default), 0x01:Supported.<br>- 0x0:Not Supported, 0x1:Supported<br>-**/<br>- UINT8 DDR3LASR;<br>-<br>-/** Offset 0x0052 - ScramblerSupport<br>- Scrambler Support - Enable or disable the memory scrambler. Data scrambling is<br>- provided as a means to increase signal integrity/reduce RFI generated by the DRAM<br>- interface. This is achieved by randomizing seed that encodes/decodes memory data<br>- so repeating a worse case pattern is hard to repeat. 00: Disable Scrambler Support,<br>- 01: Enable Scrambler Support<br>- $EN_DIS<br>-**/<br>- UINT8 ScramblerSupport;<br>-<br>-/** Offset 0x0053 - InterleavedMode<br>- This field is ignored if one of the PnP channel configurations is used. If the memory<br>- configuration is different, then the field is used directly to populate. 0x00:Disable(Default),<br>- 0x02:Enable.<br>- 0x0:Disable, 0x2:Enable<br>-**/<br>- UINT8 InterleavedMode;<br>-<br>-/** Offset 0x0054 - ChannelHashMask<br>- ChannelHashMask and SliceHashMask allow for the channel hashing algorithm to be<br>- modified. These inputs are not used for configurations where an optimized ChannelHashMask<br>- has been provided by the PnP validation teams. 0x00(Default).<br>-**/<br>- UINT16 ChannelHashMask;<br>-<br>-/** Offset 0x0056 - SliceHashMask<br>- ChannelHashMask and SliceHashMask allow for the channel hashing algorithm to be<br>- modified. These inputs are not used for configurations where an optimized ChannelHashMask<br>- has been provided by the PnP validation teams. 0x00(Default).<br>-**/<br>- UINT16 SliceHashMask;<br>-<br>-/** Offset 0x0058 - ChannelsSlicesEnable<br>- ChannelSlicesEnable field is not used at all on BXTP. The Channel Slice Configuration<br>- is calculated internally based on the enabled channel configuration. 0x00:Disable(Default),<br>- 0x01:Enable.<br>- $EN_DIS<br>-**/<br>- UINT8 ChannelsSlicesEnable;<br>-<br>-/** Offset 0x0059 - MinRefRate2xEnable<br>- Provided as a means to defend against Row-Hammer attacks. 0x00:Disable(Default),<br>- 0x01:Enable.<br>- $EN_DIS<br>-**/<br>- UINT8 MinRefRate2xEnable;<br>-<br>-/** Offset 0x005A - DualRankSupportEnable<br>- Dual Rank Support Enable. 0x00:Disable, 0x01:Enable(Default).<br>- $EN_DIS<br>-**/<br>- UINT8 DualRankSupportEnable;<br>-<br>-/** Offset 0x005B - RmtMode<br>- Rank Margin Tool Mode. 0x00(Default), 0x3(Enabled).<br>- 0x0:Disabled, 0x3:Enabled<br>-**/<br>- UINT8 RmtMode;<br>-<br>-/** Offset 0x005C - MemorySizeLimit<br>- Memory Size Limit: This value is used to restrict the total amount of memory and<br>- the calculations based on it. Value is in MB. Example encodings are: 0x400 = 1GB,<br>- 0x800 = 2GB, 0x1000 = 4GB, 0x2000 8GB. 0x0000(Default)<br>-**/<br>- UINT16 MemorySizeLimit;<br>-<br>-/** Offset 0x005E - LowMemoryMaxValue<br>- Low Memory Max Value: This value is used to restrict the amount of memory below<br>- 4GB and the calculations based on it. Value is in MB.Example encodings are: 0x400<br>- = 1GB, 0x800 = 2GB, 0x1000 = 4GB, 0x2000 8GB. 0x0000(Default).<br>-**/<br>- UINT16 LowMemoryMaxValue;<br>-<br>-/** Offset 0x0060 - HighMemoryMaxValue<br>- High Memory Max Value: This value is used to restrict the amount of memory above<br>- 4GB and the calculations based on it. Value is in MB. Example encodings are: 0x0400:1GB,<br>- 0x0800:2GB, 0x1000:4GB, 0x2000:8GB. 0x00(Default).<br>-**/<br>- UINT16 HighMemoryMaxValue;<br>-<br>-/** Offset 0x0062 - DisableFastBoot<br>- 00:Disabled; Use saved training data (if valid) after first boot(Default), 01:Enabled;<br>- Full re-train of memory on every boot.<br>- $EN_DIS<br>-**/<br>- UINT8 DisableFastBoot;<br>-<br>-/** Offset 0x0063 - DIMM0SPDAddress<br>- DIMM0 SPD Address (NOTE: Only for DDR3L only. Please put 0 for MemoryDown. 0xA0(Default).<br>-**/<br>- UINT8 DIMM0SPDAddress;<br>-<br>-/** Offset 0x0064 - DIMM1SPDAddress<br>- DIMM1 SPD Address (NOTE: Only for DDR3L only. Please put 0 for MemoryDown. 0xA4(Default).<br>-**/<br>- UINT8 DIMM1SPDAddress;<br>-<br>-/** Offset 0x0065 - Ch0_RankEnable<br>- NOTE: Only for memory down. This is a bit mask which specifies what ranks are enabled.<br>- NOTE: Only for memory down (soldered down memory with no SPD): BIT[0] Enable Rank<br>- 0: Must be set to 1 to enable use of this rank; BIT1[1] Enable Rank 1: Must be<br>- set to 1 to enable use of this rank.<br>-**/<br>- UINT8 Ch0_RankEnable;<br>-<br>-/** Offset 0x0066 - Ch0_DeviceWidth<br>- NOTE: Only for memory down. Must specify the DRAM device width per DRAM channel<br>- (not to be confused with the SoC Memory Channel width which is always x32 for LPDDR3\LPDDR4<br>- and x64 for DDR3L). LPDDR4 devices typically have two channels per die and a x16<br>- device width: 00 - x8; 01 - x16; 10 - x32; 11 - x64<br>- 0b0000:x8, 0b0001:x16, 0b0010:x32, 0b0011:x64<br>-**/<br>- UINT8 Ch0_DeviceWidth;<br>-<br>-/** Offset 0x0067 - Ch0_DramDensity<br>- NOTE: Only for memory down. For LPDDR3 and LPDDR4: Must specify the DRAM device<br>- density per rank (per Chip Select). The simplest way of identifying the density<br>- per rank is to divide the total SoC memory channel density by the number of ranks.<br>- For DDR3L: Must specify the DRAM device density per DRAM device. For example, an<br>- 8GB 2Rx8 configuration will utilize sixteen 4Gb density DRAMS. In this configuration,<br>- a 4Gb density setting would be selected in the MRC: 000 - 4Gb; 001 - 6Gb; 010 -<br>- 8Gb; 011 - 12Gb; 100 - 16Gb; 101 - 2Gb; 110-111 - Reserved<br>- 0b0000:4Gb, 0b0001:6Gb, 0b0010:8Gb, 0b0011:12Gb, 0b0100:16Gb<br>-**/<br>- UINT8 Ch0_DramDensity;<br>-<br>-/** Offset 0x0068 - Ch0_Option<br>- BIT[0] Rank Select Interleaving Enable. See Address Mapping section for full description:<br>- 0 - Rank Select Interleaving disabled; 1 - Rank Select Interleaving enabled. BIT[1]<br>- Bank Address Hashing Enable. See Address Mapping section for full description:<br>- 0 - Bank Address Hashing disabled; 1 - Bank Address Hashing enabled. BIT[2] CH1<br>- CLK Disable. Disables the CH1 CLK PHY Signal when set to 1. This is used on board<br>- designs where the CH1 CLK is not routed and left floating or stubbed out: 0 - CH1<br>- CLK is enabled; 1 - CH1 CLK is disabled. BIT[3] Reserved; BIT[5:4] This register<br>- specifies the address mapping to be used: 00 - 1KB (A); 01 - 2KB (B)<br>-**/<br>- UINT8 Ch0_Option;<br>-<br>-/** Offset 0x0069 - Ch0_OdtConfig<br>- [0] RX ODT - DDR3L & LPDDR3 only: Change the READ ODT strength , for SOC termination<br>- during a READ transaction, ON DQ BITs. STRONG ==> 60 OHMS roughly, WEAK ==> 120<br>- OHMS or so roughly. Purpose: Save power on these technologies which burn power<br>- directly proportional to ODT strength, because ODT looks like a PU and PD (e.g.<br>- a resistor divider, which always burns power when ODT is ON). 0 - WEAK_ODT_CONFIG,<br>- 1 - STRONG_ODT_CONFIG. LPDDR4: X - Don't Care. [1] CA ODT - LPDDR4 Only: The<br>- customer needs to choose this based on their actual board strapping (how they tie<br>- the DRAM's ODT PINs). Effect: LPDDR4 MR11 will be set based on this setting. CAODT_A_B_HIGH_LOW<br>- ==> MR11 = 0x34, which is CA ODT = 80 ohms. CAODT_A_B_HIGH_HIGH ==> MR11 = 0x24,<br>- which is CA ODT = 120 ohms (results in 60 ohm final effective impedance on CA/CLK/CS<br>- signals). Purpose: To improve signal integrity and provide a much more optimized<br>- CA VREF value during training. Not to save power. 0 - ODT_AB_HIGH_LOW (default),<br>- 1 - ODT_AB_HIGH_HIGH. DDR3L & LPDDR3: X - Don't Care. [4] TX ODT. DDR3L only:<br>- 0 = RZQ/4 (60 Ohms) = MRC_SMIP_DDR3L_TX_ODT_RTT_WR_60_OHMS, 1 = RZQ/2 (120<br>- Ohms) = MRC_SMIP_DDR3L_TX_ODT_RTT_WR_120_OHMS. LPDDR3 & LPDDR4: X = Don't Care<br>-**/<br>- UINT8 Ch0_OdtConfig;<br>-<br>-/** Offset 0x006A - Ch0_TristateClk1<br>- Not used<br>-**/<br>- UINT8 Ch0_TristateClk1;<br>-<br>-/** Offset 0x006B - Ch0_Mode2N<br>- DDR3L Only: Configures the DDR3L command timing mode. 2N Mode is a stretched command<br>- mode that provides more setup and hold time for DRAM commands on the DRAM command<br>- bus. This is useful for platforms with unusual CMD bus routing or marginal signal<br>- integrity: 0 - Auto (1N or 2N mode is automatically selected during Command and<br>- Control training), 1 - Force 2N Mode<br>- 0x0:Auto, 0x1:Force 2N CMD Timing Mode<br>-**/<br>- UINT8 Ch0_Mode2N;<br>-<br>-/** Offset 0x006C - Ch0_OdtLevels<br>- Parameter used to determine if ODT will be held high or low: 0 - ODT Connected to<br>- SoC, 1 - ODT held high<br>-**/<br>- UINT8 Ch0_OdtLevels;<br>-<br>-/** Offset 0x006D - Ch1_RankEnable<br>- NOTE: Only for memory down. This is a bit mask which specifies what ranks are enabled.<br>- NOTE: Only for memory down (soldered down memory with no SPD): BIT[0] Enable Rank<br>- 0: Must be set to 1 to enable use of this rank; BIT1[1] Enable Rank 1: Must be<br>- set to 1 to enable use of this rank.<br>-**/<br>- UINT8 Ch1_RankEnable;<br>-<br>-/** Offset 0x006E - Ch1_DeviceWidth<br>- NOTE: Only for memory down. Must specify the DRAM device width per DRAM channel<br>- (not to be confused with the SoC Memory Channel width which is always x32 for LPDDR3\LPDDR4<br>- and x64 for DDR3L). LPDDR4 devices typically have two channels per die and a x16<br>- device width: 00 - x8; 01 - x16; 10 - x32; 11 - x64<br>- 0b0000:x8, 0b0001:x16, 0b0010:x32, 0b0011:x64<br>-**/<br>- UINT8 Ch1_DeviceWidth;<br>-<br>-/** Offset 0x006F - Ch1_DramDensity<br>- NOTE: Only for memory down. For LPDDR3 and LPDDR4: Must specify the DRAM device<br>- density per rank (per Chip Select). The simplest way of identifying the density<br>- per rank is to divide the total SoC memory channel density by the number of ranks.<br>- For DDR3L: Must specify the DRAM device density per DRAM device. For example, an<br>- 8GB 2Rx8 configuration will utilize sixteen 4Gb density DRAMS. In this configuration,<br>- a 4Gb density setting would be selected in the MRC: 000 - 4Gb; 001 - 6Gb; 010 -<br>- 8Gb; 011 - 12Gb; 100 - 16Gb; 101 - 2Gb; 110-111 - Reserved<br>- 0b0000:4Gb, 0b0001:6Gb, 0b0010:8Gb, 0b0011:12Gb, 0b0100:16Gb<br>-**/<br>- UINT8 Ch1_DramDensity;<br>-<br>-/** Offset 0x0070 - Ch1_Option<br>- BIT[0] Rank Select Interleaving Enable. See Address Mapping section for full description:<br>- 0 - Rank Select Interleaving disabled; 1 - Rank Select Interleaving enabled. BIT[1]<br>- Bank Address Hashing Enable. See Address Mapping section for full description:<br>- 0 - Bank Address Hashing disabled; 1 - Bank Address Hashing enabled. BIT[2] CH1<br>- CLK Disable. Disables the CH1 CLK PHY Signal when set to 1. This is used on board<br>- designs where the CH1 CLK is not routed and left floating or stubbed out: 0 - CH1<br>- CLK is enabled; 1 - CH1 CLK is disabled. BIT[3] Reserved; BIT[5:4] This register<br>- specifies the address mapping to be used: 00 - 1KB (A); 01 - 2KB (B)<br>-**/<br>- UINT8 Ch1_Option;<br>-<br>-/** Offset 0x0071 - Ch1_OdtConfig<br>- BIT[0] TX ODT: DDR3L & LPDDR3 only: 0 - WEAK_ODT_CONFIG, 1 - STRONG_ODT_CONFIG;<br>- LPDDR4: X = Don't Care; BIT[4] RX ODT DDR3L only: 0 = RZQ/4 (60 Ohms) = MRC_SMIP_DDR3L_RX_ODT_RTT_WR_60_OHMS,<br>- 1 = RZQ/2 (120 Ohms) = MRC_SMIP_DDR3L_RX_ODT_RTT_WR_120_OHMS; LPDDR3 & LPDDR4:<br>- X = Don't Care<br>-**/<br>- UINT8 Ch1_OdtConfig;<br>-<br>-/** Offset 0x0072 - Ch1_TristateClk1<br>- Not used<br>-**/<br>- UINT8 Ch1_TristateClk1;<br>-<br>-/** Offset 0x0073 - Ch1_Mode2N<br>- DDR3L Only: Configures the DDR3L command timing mode. 2N Mode is a stretched command<br>- mode that provides more setup and hold time for DRAM commands on the DRAM command<br>- bus. This is useful for platforms with unusual CMD bus routing or marginal signal<br>- integrity: 0 - Auto (1N or 2N mode is automatically selected during Command and<br>- Control training), 1 - Force 2N Mode<br>- 0x0:Auto, 0x1:Force 2N CMD Timing Mode<br>-**/<br>- UINT8 Ch1_Mode2N;<br>-<br>-/** Offset 0x0074 - Ch1_OdtLevels<br>- DDR3L Only: Parameter used to determine if ODT will be held high or low: 0 - ODT_AB_HIGH_LOW<br>- (default), 1 - ODT_AB_HIGH_HIGH<br>-**/<br>- UINT8 Ch1_OdtLevels;<br>-<br>-/** Offset 0x0075 - Ch2_RankEnable<br>- NOTE: Only for memory down. This is a bit mask which specifies what ranks are enabled.<br>- NOTE: Only for memory down (soldered down memory with no SPD): BIT[0] Enable Rank<br>- 0: Must be set to 1 to enable use of this rank; BIT1[1] Enable Rank 1: Must be<br>- set to 1 to enable use of this rank.<br>-**/<br>- UINT8 Ch2_RankEnable;<br>-<br>-/** Offset 0x0076 - Ch2_DeviceWidth<br>- NOTE: Only for memory down. Must specify the DRAM device width per DRAM channel<br>- (not to be confused with the SoC Memory Channel width which is always x32 for LPDDR3\LPDDR4<br>- and x64 for DDR3L). LPDDR4 devices typically have two channels per die and a x16<br>- device width: 00 - x8; 01 - x16; 10 - x32; 11 - x64<br>- 0b0000:x8, 0b0001:x16, 0b0010:x32, 0b0011:x64<br>-**/<br>- UINT8 Ch2_DeviceWidth;<br>-<br>-/** Offset 0x0077 - Ch2_DramDensity<br>- NOTE: Only for memory down. For LPDDR3 and LPDDR4: Must specify the DRAM device<br>- density per rank (per Chip Select). The simplest way of identifying the density<br>- per rank is to divide the total SoC memory channel density by the number of ranks.<br>- For DDR3L: Must specify the DRAM device density per DRAM device. For example, an<br>- 8GB 2Rx8 configuration will utilize sixteen 4Gb density DRAMS. In this configuration,<br>- a 4Gb density setting would be selected in the MRC: 000 - 4Gb; 001 - 6Gb; 010 -<br>- 8Gb; 011 - 12Gb; 100 - 16Gb; 101 - 2Gb; 110-111 - Reserved<br>- 0b0000:4Gb, 0b0001:6Gb, 0b0010:8Gb, 0b0011:12Gb, 0b0100:16Gb<br>-**/<br>- UINT8 Ch2_DramDensity;<br>-<br>-/** Offset 0x0078 - Ch2_Option<br>- BIT[0] Rank Select Interleaving Enable. See Address Mapping section for full description:<br>- 0 - Rank Select Interleaving disabled; 1 - Rank Select Interleaving enabled. BIT[1]<br>- Bank Address Hashing Enable. See Address Mapping section for full description:<br>- 0 - Bank Address Hashing disabled; 1 - Bank Address Hashing enabled. BIT[2] CH1<br>- CLK Disable. Disables the CH1 CLK PHY Signal when set to 1. This is used on board<br>- designs where the CH1 CLK is not routed and left floating or stubbed out: 0 - CH1<br>- CLK is enabled; 1 - CH1 CLK is disabled. BIT[3] Reserved; BIT[5:4] This register<br>- specifies the address mapping to be used: 00 - 1KB (A); 01 - 2KB (B)<br>-**/<br>- UINT8 Ch2_Option;<br>-<br>-/** Offset 0x0079 - Ch2_OdtConfig<br>- BIT[0] TX ODT: DDR3L & LPDDR3 only: 0 - WEAK_ODT_CONFIG, 1 - STRONG_ODT_CONFIG;<br>- LPDDR4: X = Don't Care; BIT[4] RX ODT DDR3L only: 0 = RZQ/4 (60 Ohms) = MRC_SMIP_DDR3L_RX_ODT_RTT_WR_60_OHMS,<br>- 1 = RZQ/2 (120 Ohms) = MRC_SMIP_DDR3L_RX_ODT_RTT_WR_120_OHMS; LPDDR3 & LPDDR4:<br>- X = Don't Care<br>-**/<br>- UINT8 Ch2_OdtConfig;<br>-<br>-/** Offset 0x007A - Ch2_TristateClk1<br>- Not used<br>-**/<br>- UINT8 Ch2_TristateClk1;<br>-<br>-/** Offset 0x007B - Ch2_Mode2N<br>- DDR3L Only: Configures the DDR3L command timing mode. 2N Mode is a stretched command<br>- mode that provides more setup and hold time for DRAM commands on the DRAM command<br>- bus. This is useful for platforms with unusual CMD bus routing or marginal signal<br>- integrity: 0 - Auto (1N or 2N mode is automatically selected during Command and<br>- Control training), 1 - Force 2N Mode<br>- 0x0:Auto, 0x1:Force 2N CMD Timing Mode<br>-**/<br>- UINT8 Ch2_Mode2N;<br>-<br>-/** Offset 0x007C - Ch2_OdtLevels<br>- DDR3L Only: Parameter used to determine if ODT will be held high or low: 0 - ODT_AB_HIGH_LOW<br>- (default), 1 - ODT_AB_HIGH_HIGH<br>-**/<br>- UINT8 Ch2_OdtLevels;<br>-<br>-/** Offset 0x007D - Ch3_RankEnable<br>- NOTE: Only for memory down. This is a bit mask which specifies what ranks are enabled.<br>- NOTE: Only for memory down (soldered down memory with no SPD): BIT[0] Enable Rank<br>- 0: Must be set to 1 to enable use of this rank; BIT1[1] Enable Rank 1: Must be<br>- set to 1 to enable use of this rank.<br>-**/<br>- UINT8 Ch3_RankEnable;<br>-<br>-/** Offset 0x007E - Ch3_DeviceWidth<br>- NOTE: Only for memory down. Must specify the DRAM device width per DRAM channel<br>- (not to be confused with the SoC Memory Channel width which is always x32 for LPDDR3\LPDDR4<br>- and x64 for DDR3L). LPDDR4 devices typically have two channels per die and a x16<br>- device width: 00 - x8; 01 - x16; 10 - x32; 11 - x64<br>- 0b0000:x8, 0b0001:x16, 0b0010:x32, 0b0011:x64<br>-**/<br>- UINT8 Ch3_DeviceWidth;<br>-<br>-/** Offset 0x007F - Ch3_DramDensity<br>- NOTE: Only for memory down. For LPDDR3 and LPDDR4: Must specify the DRAM device<br>- density per rank (per Chip Select). The simplest way of identifying the density<br>- per rank is to divide the total SoC memory channel density by the number of ranks.<br>- For DDR3L: Must specify the DRAM device density per DRAM device. For example, an<br>- 8GB 2Rx8 configuration will utilize sixteen 4Gb density DRAMS. In this configuration,<br>- a 4Gb density setting would be selected in the MRC: 000 - 4Gb; 001 - 6Gb; 010 -<br>- 8Gb; 011 - 12Gb; 100 - 16Gb; 101 - 2Gb; 110-111 - Reserved<br>- 0b0000:4Gb, 0b0001:6Gb, 0b0010:8Gb, 0b0011:12Gb, 0b0100:16Gb<br>-**/<br>- UINT8 Ch3_DramDensity;<br>-<br>-/** Offset 0x0080 - Ch3_Option<br>- BIT[0] Rank Select Interleaving Enable. See Address Mapping section for full description:<br>- 0 - Rank Select Interleaving disabled; 1 - Rank Select Interleaving enabled. BIT[1]<br>- Bank Address Hashing Enable. See Address Mapping section for full description:<br>- 0 - Bank Address Hashing disabled; 1 - Bank Address Hashing enabled. BIT[2] CH1<br>- CLK Disable. Disables the CH1 CLK PHY Signal when set to 1. This is used on board<br>- designs where the CH1 CLK is not routed and left floating or stubbed out: 0 - CH1<br>- CLK is enabled; 1 - CH1 CLK is disabled. BIT[3] Reserved; BIT[5:4] This register<br>- specifies the address mapping to be used: 00 - 1KB (A); 01 - 2KB (B)<br>-**/<br>- UINT8 Ch3_Option;<br>-<br>-/** Offset 0x0081 - Ch3_OdtConfig<br>- BIT[0] TX ODT: DDR3L & LPDDR3 only: 0 - WEAK_ODT_CONFIG, 1 - STRONG_ODT_CONFIG;<br>- LPDDR4: X = Don't Care; BIT[4] RX ODT DDR3L only: 0 = RZQ/4 (60 Ohms) = MRC_SMIP_DDR3L_RX_ODT_RTT_WR_60_OHMS,<br>- 1 = RZQ/2 (120 Ohms) = MRC_SMIP_DDR3L_RX_ODT_RTT_WR_120_OHMS; LPDDR3 & LPDDR4:<br>- X = Don't Care<br>-**/<br>- UINT8 Ch3_OdtConfig;<br>-<br>-/** Offset 0x0082 - Ch3_TristateClk1<br>- Not used<br>-**/<br>- UINT8 Ch3_TristateClk1;<br>-<br>-/** Offset 0x0083 - Ch3_Mode2N<br>- DDR3L Only: Configures the DDR3L command timing mode. 2N Mode is a stretched command<br>- mode that provides more setup and hold time for DRAM commands on the DRAM command<br>- bus. This is useful for platforms with unusual CMD bus routing or marginal signal<br>- integrity: 0 - Auto (1N or 2N mode is automatically selected during Command and<br>- Control training), 1 - Force 2N Mode<br>- 0x0:Auto, 0x1:Force 2N CMD Timing Mode<br>-**/<br>- UINT8 Ch3_Mode2N;<br>-<br>-/** Offset 0x0084 - Ch3_OdtLevels<br>- DDR3L Only: Parameter used to determine if ODT will be held high or low: 0 - ODT_AB_HIGH_LOW<br>- (default), 1 - ODT_AB_HIGH_HIGH<br>-**/<br>- UINT8 Ch3_OdtLevels;<br>-<br>-/** Offset 0x0085 - RmtCheckRun<br>- Parameter used to determine whether to run the margin check. Bit 0 is used for MINIMUM<br>- MARGIN CHECK and bit 1 is used for DEGRADE MARGIN CHECK<br>-**/<br>- UINT8 RmtCheckRun;<br>-<br>-/** Offset 0x0086 - RmtMarginCheckScaleHighThreshold<br>- Percentage used to determine the margin tolerances over the failing margin.<br>-**/<br>- UINT16 RmtMarginCheckScaleHighThreshold;<br>-<br>-/** Offset 0x0088 - Ch0_Bit_swizzling<br>- Channel 0 PHY to DUnit DQ mapping (only used if not 1-1 mapping)Range: 0-32. Frequently<br>- asked questions: Q: The DQS (strobes) need to go with the corresponding byte lanes<br>- on the DDR module. Are the DQS being swapped around as well? Ans: Yes, DQ strobes<br>- need to follow the DQ byte lane they correspond too. So for example if you have<br>- DQ[7:0] swapped with DQ[15:8], DQS0 pair also need to be swapped with DQS1 pair.<br>- Also, the spreadsheet used for Amenia is essentially a swizzle value lookup that<br>- specifies what DRAM DQ bit a particular SoC DQ bit is connected to. Some confusion<br>- can arrise from the fact that the indexes to the array do not necessarily map 1:1<br>- to an SoC DQ pin. For example, the CH0 array at index 0 maps to SoC DQB8. The value<br>- of 9 at index 0 tells us that SoC DQB8 is connected to DRAM DQA9. Q: The PDG indicates<br>- a 2 physical channels need to be stuffed and operated together. Are the CHx_A and<br>- CHx_B physical channels operated in tandem or completely separate? If separate,<br>- why requirement of pairing them? Ans: We have 2 PHY instances on the SoC each supporting<br>- up to 2 x32 LP4 channels. If you have 4 channels both PHYs are active, but if you<br>- have 2 channels in order to power gate one PHY, those two channel populated must<br>- be on one PHY instance. So yes all channels are independent of each other, but<br>- there are some restrictions on how they need to be populated. Q: How is it that<br>- an LPDDR4 device is identified as having a x16 width when all 32-bits are used<br>- at the same time with a single chip select? That's effectively a x32 device. Ans:LPDDR4<br>- DRAM devices are x16. Each die has 2 x16 devices on them. To make a x32 channel<br>- the CS of the two devices in the same die are connected together to make a single<br>- rank of one x32 channel (SDP). The second die in the DDP package makes the second rank.<br>-**/<br>- UINT8 Ch0_Bit_swizzling[32];<br>-<br>-/** Offset 0x00A8 - Ch1_Bit_swizzling<br>- Channel 1 PHY to DUnit DQ mapping (only used if not 1-1 mapping)Range: 0-32.<br>-**/<br>- UINT8 Ch1_Bit_swizzling[32];<br>-<br>-/** Offset 0x00C8 - Ch2_Bit_swizzling<br>- Channel 2 PHY to DUnit DQ mapping (only used if not 1-1 mapping)Range: 0-32.<br>-**/<br>- UINT8 Ch2_Bit_swizzling[32];<br>-<br>-/** Offset 0x00E8 - Ch3_Bit_swizzling<br>- Channel 3 PHY to DUnit DQ mapping (only used if not 1-1 mapping)Range: 0-32.<br>-**/<br>- UINT8 Ch3_Bit_swizzling[32];<br>-<br>-/** Offset 0x0108 - MsgLevelMask<br>- 32 bits used to mask out debug messages. Masking out bit 0 mask all other messages.<br>-**/<br>- UINT32 MsgLevelMask;<br>-<br>-/** Offset 0x010C<br>-**/<br>- UINT8 UnusedUpdSpace0[4];<br>-<br>-/** Offset 0x0110 - PreMem GPIO Pin Number for each table<br>- Number of Pins in each PreMem GPIO Table. 0(Default).<br>-**/<br>- UINT8 PreMemGpioTablePinNum[4];<br>-<br>-/** Offset 0x0114 - PreMem GPIO Table Pointer<br>- Pointer to Array of pointers to PreMem GPIO Table. 0x00000000(Default).<br>-**/<br>- UINT32 PreMemGpioTablePtr;<br>-<br>-/** Offset 0x0118 - PreMem GPIO Table Entry Number. Currently maximum entry number is 4<br>- Number of Entries in PreMem GPIO Table. 0(Default).<br>-**/<br>- UINT8 PreMemGpioTableEntryNum;<br>-<br>-/** Offset 0x0119 - Enhance the port 8xh decoding<br>- Enable/Disable Enhance the port 8xh decoding. 0:Disable, 1:Enable(Default).<br>- $EN_DIS<br>-**/<br>- UINT8 EnhancePort8xhDecoding;<br>-<br>-/** Offset 0x011A - SPD Data Write<br>- Enable/Disable SPD data write on the SMBUS. 0x00:Disable(Default), 0x01:Enable.<br>- $EN_DIS<br>-**/<br>- UINT8 SpdWriteEnable;<br>-<br>-/** Offset 0x011B - MRC Training Data Saving<br>- Enable/Disable MRC training data saving in FSP. 0x00:Disable(Default), 0x01:Enable.<br>- $EN_DIS<br>-**/<br>- UINT8 MrcDataSaving;<br>-<br>-/** Offset 0x011C - OEM File Loading Address<br>- Determine the memory base address to load a specified file from CSE file system<br>- after memory is available.<br>-**/<br>- UINT32 OemLoadingBase;<br>-<br>-/** Offset 0x0120 - OEM File Name to Load<br>- Specify a file name to load from CSE file system after memory is available. Empty<br>- indicates no file needs to be loaded.<br>-**/<br>- UINT8 OemFileName[16];<br>-<br>-/** Offset 0x0130<br>-**/<br>- VOID* MrcBootDataPtr;<br>-<br>-/** Offset 0x0134 - eMMC Trace Length<br>- Select eMMC trace length to load OEM file from when loading OEM file name is specified.<br>- 0x0:Long(Default), 0x1:Short.<br>- 0x0:Long, 0x1:Short<br>-**/<br>- UINT8 eMMCTraceLen;<br>-<br>-/** Offset 0x0135 - Skip CSE RBP to support zero sized IBB<br>- Enable/Disable skip CSE RBP for bootloader which loads IBB without assistance of<br>- CSE. 0x00:Disable(Default), 0x01:Enable.<br>- $EN_DIS<br>-**/<br>- UINT8 SkipCseRbp;<br>-<br>-/** Offset 0x0136 - Trace Hub Enable<br>- Disable Npk/Host Debugger/Target Debugger. 0:Disable(Default), 1:Host Debugger,<br>- 2:Target Debugger.<br>- 0:Disable, 1:Host Debugger, 2:Target Debugger<br>-**/<br>- UINT8 TraceHubEn;<br>-<br>-/** Offset 0x0137 - FW Trace Enable<br>- Enable/Disable FW Trace. 0:Disable, 1:Enable(Default).<br>- $EN_DIS<br>-**/<br>- UINT8 FwTraceEn;<br>-<br>-/** Offset 0x0138 - FW Trace Destination<br>- FW Trace Destination. 1-NPK_TRACE_TO_MEMORY, 2-NPK_TRACE_TO_DCI, 3-NPK_TRACE_TO_BSSB,<br>- 4-NPK_TRACE_TO_PTI(Default).<br>-**/<br>- UINT8 FwTraceDestination;<br>-<br>-/** Offset 0x0139 - NPK Recovery Dump<br>- Enable/Disable NPK Recovery Dump. 0:Disable(Default), 1:Enable.<br>- $EN_DIS<br>-**/<br>- UINT8 RecoverDump;<br>-<br>-/** Offset 0x013A - Memory Region 0 Buffer WrapAround<br>- Memory Region 0 Buffer WrapAround. 0-n0-warp, 1-warp(Default).<br>-**/<br>- UINT8 Msc0Wrap;<br>-<br>-/** Offset 0x013B - Memory Region 1 Buffer WrapAround<br>- Memory Region 1 Buffer WrapAround. 0-n0-warp, 1-warp(Default).<br>-**/<br>- UINT8 Msc1Wrap;<br>-<br>-/** Offset 0x013C - Memory Region 0 Buffer Size<br>- Memory Region 0 Buffer Size. 0-0MB(Default), 1-1MB, 2-8MB, 3-64MB, 4-128MB, 5-256MB,<br>- 6-512MB, 7-1GB.<br>-**/<br>- UINT32 Msc0Size;<br>-<br>-/** Offset 0x0140 - Memory Region 1 Buffer Size<br>- Memory Region 1 Buffer Size, 0-0MB(Default), 1-1MB, 2-8MB, 3-64MB, 4-128MB, 5-256MB,<br>- 6-512MB, 7-1GB.<br>-**/<br>- UINT32 Msc1Size;<br>-<br>-/** Offset 0x0144 - PTI Mode<br>- PTI Mode. 0-0ff, 1-x4(Default), 2-x8, 3-x12, 4-x16.<br>-**/<br>- UINT8 PtiMode;<br>-<br>-/** Offset 0x0145 - PTI Training<br>- PTI Training. 0-off(Default), 1-6=1-6.<br>-**/<br>- UINT8 PtiTraining;<br>-<br>-/** Offset 0x0146 - PTI Speed<br>- PTI Speed. 0-full, 1-half, 2-quarter(Default).<br>-**/<br>- UINT8 PtiSpeed;<br>-<br>-/** Offset 0x0147 - Punit Message Level<br>- Punit Message Output Verbosity Level. 0, 1(Default), 2-4=2-4.<br>-**/<br>- UINT8 PunitMlvl;<br>-<br>-/** Offset 0x0148 - PMC Message Level<br>- PMC Message Output Verbosity Level. 0, 1(Default), 2-4=2-4.<br>-**/<br>- UINT8 PmcMlvl;<br>-<br>-/** Offset 0x0149 - SW Trace Enable<br>- Enable/Disable SW Trace. 0:Disable(Default), 1:Enable.<br>- $EN_DIS<br>-**/<br>- UINT8 SwTraceEn;<br>-<br>-/** Offset 0x014A - SGX mode<br>- Select SGX mode. 0:Disable, 1:Enable, 2:Software control (default)<br>- 0:Disable, 1:Enable, 2:Software control (default)<br>-**/<br>- UINT8 EnableSgx;<br>-<br>-/** Offset 0x014B - PRMRR size<br>- PRMRR size. 0:Invalid (default), 1:32MB, 2:64MB 3:128MB<br>- 0:Invalid (default), 1:32MB, 2:64MB 3:128MB<br>-**/<br>- UINT32 PrmrrSize;<br>-<br>-/** Offset 0x014F - Periodic Retraining Disable<br>- Periodic Retraining Disable - This option allows customers to disable LPDDR4 Periodic<br>- Retraining for debug purposes. Periodic Retraining should be enabled in production.<br>- Periodic retraining allows the platform to operate reliably over a larger voltage<br>- and temperature range. This field has no effect for DDR3L and LPDDR3 memory type<br>- configurations. 0x00: Enable Periodic Retraining (default); 0x01: Disable Periodic<br>- Retraining (debug configuration only)<br>- 0x0:Enabled, 0x1:Disabled<br>-**/<br>- UINT8 PeriodicRetrainingDisable;<br>-<br>-/** Offset 0x0150 - Enable Reset System<br>- Enable FSP to trigger reset instead of returning reset request. 0x00: Return the<br>- Return Status from FSP if a reset is required. (default); 0x01: Perform Reset inside<br>- FSP instead of returning from the API.<br>- 0x0:Disabled, 0x1:Eabled<br>-**/<br>- UINT8 EnableResetSystem;<br>-<br>-/** Offset 0x0151 - Enable HECI2 in S3 resume path<br>- Enable HECI2 in S3 resume path. 0x00: Skip HECI2 initialization in S3 resume. ;<br>- 0x01: Enable HECI2 in S3 resume path.(Default)<br>- 0x0:Disabled, 0x1:Eabled<br>-**/<br>- UINT8 EnableS3Heci2;<br>-<br>-/** Offset 0x0152<br>-**/<br>- UINT8 ReservedFspmUpd[3];<br>-} FSP_M_CONFIG;<br>-<br>-/** Fsp M Test Configuration<br>-**/<br>-typedef struct {<br>-<br>-/** Offset 0x0155<br>-**/<br>- UINT32 Signature;<br>-<br>-/** Offset 0x0159<br>-**/<br>- UINT8 ReservedFspmTestUpd[28];<br>-} FSP_M_TEST_CONFIG;<br>-<br>-/** Fsp M Restricted Configuration<br>-**/<br>-typedef struct {<br>-<br>-/** Offset 0x0175<br>-**/<br>- UINT32 Signature;<br>-<br>-/** Offset 0x0179<br>-**/<br>- UINT8 ReservedFspmRestrictedUpd[124];<br>-} FSP_M_RESTRICTED_CONFIG;<br>-<br>-/** Fsp M UPD Configuration<br>-**/<br>-typedef struct {<br>-<br>-/** Offset 0x0000<br>-**/<br>- FSP_UPD_HEADER FspUpdHeader;<br>-<br>-/** Offset 0x0020<br>-**/<br>- FSPM_ARCH_UPD FspmArchUpd;<br>-<br>-/** Offset 0x0040<br>-**/<br>- FSP_M_CONFIG FspmConfig;<br>-<br>-/** Offset 0x0155<br>-**/<br>- FSP_M_TEST_CONFIG FspmTestConfig;<br>-<br>-/** Offset 0x0175<br>-**/<br>- FSP_M_RESTRICTED_CONFIG FspmRestrictedConfig;<br>-<br>-/** Offset 0x01F5<br>-**/<br>- UINT8 UnusedUpdSpace1[14];<br>-<br>-/** Offset 0x0203<br>-**/<br>- UINT16 UpdTerminator;<br>-} FSPM_UPD;<br>-<br>-#pragma pack(pop)<br>-<br>-#endif<br>+/** @file<br>+<br>+Copyright (c) 2017, Intel Corporation. All rights reserved.<BR><br>+<br>+Redistribution and use in source and binary forms, with or without modification,<br>+are permitted provided that the following conditions are met:<br>+<br>+* Redistributions of source code must retain the above copyright notice, this<br>+ list of conditions and the following disclaimer.<br>+* Redistributions in binary form must reproduce the above copyright notice, this<br>+ list of conditions and the following disclaimer in the documentation and/or<br>+ other materials provided with the distribution.<br>+* Neither the name of Intel Corporation nor the names of its contributors may<br>+ be used to endorse or promote products derived from this software without<br>+ specific prior written permission.<br>+<br>+ THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"<br>+ AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE<br>+ IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE<br>+ ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE<br>+ LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR<br>+ CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF<br>+ SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS<br>+ INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN<br>+ CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)<br>+ ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF<br>+ THE POSSIBILITY OF SUCH DAMAGE.<br>+<br>+ This file is automatically generated. Please do NOT modify !!!<br>+<br>+**/<br>+<br>+#ifndef __FSPMUPD_H__<br>+#define __FSPMUPD_H__<br>+<br>+#include <FspUpd.h><br>+<br>+#pragma pack(1)<br>+<br>+<br>+#define MAX_NODE_NUM 1<br>+#define MAX_CHANNELS_NUM 4<br>+#define MAX_DIMMS_NUM 1<br>+<br>+#define MAX_PROFILE_NUM 4 // number of memory profiles supported<br>+#define MAX_XMP_PROFILE_NUM 2 // number of XMP profiles supported<br>+<br>+//<br>+// Matches MAX_SPD_SAVE define in MRC<br>+//<br>+#ifndef MAX_SPD_SAVE<br>+#define MAX_SPD_SAVE 29<br>+#endif<br>+<br>+//<br>+// MRC version description.<br>+//<br>+typedef struct {<br>+ UINT8 Major; ///< Major version number<br>+ UINT8 Minor; ///< Minor version number<br>+ UINT8 Rev; ///< Revision number<br>+ UINT8 Build; ///< Build number<br>+} SiMrcVersion;<br>+<br>+//<br>+// DIMM timings<br>+//<br>+typedef struct {<br>+ UINT32 tCK; ///< Memory cycle time, in femtoseconds.<br>+ UINT16 NMode; ///< Number of tCK cycles for the channel DIMM's command rate mode.<br>+ UINT16 tCL; ///< Number of tCK cycles for the channel DIMM's CAS latency.<br>+ UINT16 tCWL; ///< Number of tCK cycles for the channel DIMM's minimum CAS write latency time.<br>+ UINT16 tFAW; ///< Number of tCK cycles for the channel DIMM's minimum four activate window delay time.<br>+ UINT16 tRAS; ///< Number of tCK cycles for the channel DIMM's minimum active to precharge delay time.<br>+ UINT16 tRCDtRP; ///< Number of tCK cycles for the channel DIMM's minimum RAS# to CAS# delay time and Row Precharge delay time.<br>+ UINT16 tREFI; ///< Number of tCK cycles for the channel DIMM's minimum Average Periodic Refresh Interval.<br>+ UINT16 tRFC; ///< Number of tCK cycles for the channel DIMM's minimum refresh recovery delay time.<br>+ UINT16 tRFCpb; ///< Number of tCK cycles for the channel DIMM's minimum per bank refresh recovery delay time.<br>+ UINT16 tRFC2; ///< Number of tCK cycles for the channel DIMM's minimum refresh recovery delay time.<br>+ UINT16 tRFC4; ///< Number of tCK cycles for the channel DIMM's minimum refresh recovery delay time.<br>+ UINT16 tRPab; ///< Number of tCK cycles for the channel DIMM's minimum row precharge delay time for all banks.<br>+ UINT16 tRRD; ///< Number of tCK cycles for the channel DIMM's minimum row active to row active delay time.<br>+ UINT16 tRRD_L; ///< Number of tCK cycles for the channel DIMM's minimum row active to row active delay time for same bank groups.<br>+ UINT16 tRRD_S; ///< Number of tCK cycles for the channel DIMM's minimum row active to row active delay time for different bank groups.<br>+ UINT16 tRTP; ///< Number of tCK cycles for the channel DIMM's minimum internal read to precharge command delay time.<br>+ UINT16 tWR; ///< Number of tCK cycles for the channel DIMM's minimum write recovery time.<br>+ UINT16 tWTR; ///< Number of tCK cycles for the channel DIMM's minimum internal write to read command delay time.<br>+ UINT16 tWTR_L; ///< Number of tCK cycles for the channel DIMM's minimum internal write to read command delay time for same bank groups.<br>+ UINT16 tWTR_S; ///< Number of tCK cycles for the channel DIMM's minimum internal write to read command delay time for different bank groups.<br>+ UINT16 tCCD_L; ///< Number of tCK cycles for the channel DIMM's minimum CAS-to-CAS delay for same bank group.<br>+} MRC_CH_TIMING;<br>+<br>+///<br>+/// Memory SMBIOS & OC Memory Data Hob<br>+///<br>+typedef struct {<br>+ UINT8 Status; ///< See MrcDimmStatus for the definition of this field.<br>+ UINT8 DimmId;<br>+ UINT32 DimmCapacity; ///< DIMM size in MBytes.<br>+ UINT16 MfgId;<br>+ UINT8 ModulePartNum[20]; ///< Module part number for DDR3 is 18 bytes however for DRR4 20 bytes as per JEDEC Spec, so reserving 20 bytes<br>+ UINT8 RankInDimm; ///< The number of ranks in this DIMM.<br>+ UINT8 SpdDramDeviceType; ///< Save SPD DramDeviceType information needed for SMBIOS structure creation.<br>+ UINT8 SpdModuleType; ///< Save SPD ModuleType information needed for SMBIOS structure creation.<br>+ UINT8 SpdModuleMemoryBusWidth;///< Save SPD ModuleMemoryBusWidth information needed for SMBIOS structure creation.<br>+ UINT8 SpdSave[MAX_SPD_SAVE]; ///< Save SPD Manufacturing information needed for SMBIOS structure creation.<br>+} DIMM_INFO;<br>+<br>+typedef struct {<br>+ UINT8 Status; ///< Indicates whether this channel should be used.<br>+ UINT8 ChannelId;<br>+ UINT8 DimmCount; ///< Number of valid DIMMs that exist in the channel.<br>+ MRC_CH_TIMING Timing[MAX_PROFILE_NUM]; ///< The channel timing values.<br>+ DIMM_INFO DimmInfo[MAX_DIMMS_NUM]; ///< Save the DIMM output characteristics.<br>+} CHANNEL_INFO;<br>+<br>+typedef struct {<br>+ UINT8 Status; ///< Indicates whether this controller should be used.<br>+ UINT16 DeviceId; ///< The PCI device id of this memory controller.<br>+ UINT8 RevisionId; ///< The PCI revision id of this memory controller.<br>+ UINT8 ChannelCount; ///< Number of valid channels that exist on the controller.<br>+ CHANNEL_INFO ChannelInfo[MAX_CHANNELS_NUM]; ///< The following are channel level definitions.<br>+} CONTROLLER_INFO;<br>+<br>+typedef struct {<br>+ UINT8 Revision;<br>+ UINT16 DataWidth; ///< Data width, in bits, of this memory device<br>+ /** As defined in SMBIOS 3.0 spec<br>+ Section 7.18.2 and Table 75<br>+ **/<br>+ UINT8 MemoryType; ///< DDR type: DDR3, DDR4, or LPDDR3<br>+ UINT16 MaximumMemoryClockSpeed;///< The maximum capable speed of the device, in megahertz (MHz)<br>+ UINT16 ConfiguredMemoryClockSpeed; ///< The configured clock speed to the memory device, in megahertz (MHz)<br>+ /** As defined in SMBIOS 3.0 spec<br>+ Section 7.17.3 and Table 72<br>+ **/<br>+ UINT8 ErrorCorrectionType;<br>+<br>+ SiMrcVersion Version;<br>+ BOOLEAN EccSupport;<br>+ UINT8 MemoryProfile;<br>+ UINT32 TotalPhysicalMemorySize;<br>+ UINT32 DefaultXmptCK[MAX_XMP_PROFILE_NUM];///< Stores the tCK value read from SPD XMP profiles if they exist.<br>+ UINT8 XmpProfileEnable; ///< If XMP capable DIMMs are detected, this will indicate which XMP Profiles are common among all DIMMs.<br>+ UINT8 Ratio;<br>+ UINT8 RefClk;<br>+ UINT32 VddVoltage[MAX_PROFILE_NUM];<br>+ CONTROLLER_INFO Controller[MAX_NODE_NUM];<br>+} FSP_SMBIOS_MEMORY_INFO;<br>+<br>+typedef struct {<br>+ UINT16 TotalNumberOfSockets;<br>+ UINT16 CurrentSocketNumber;<br>+ UINT8 ProcessorType; ///< ENUM defined in SMBIOS Spec v3.0 Section 7.5.1<br>+ /** This info is used for both ProcessorFamily and ProcessorFamily2 fields<br>+ See ENUM defined in SMBIOS Spec v3.0 Section 7.5.2<br>+ **/<br>+ UINT16 ProcessorFamily;<br>+ UINT8 ProcessorManufacturerStrIndex; ///< Index of the String in the String Buffer<br>+ UINT64 ProcessorId; ///< ENUM defined in SMBIOS Spec v3.0 Section 7.5.3<br>+ UINT8 ProcessorVersionStrIndex; ///< Index of the String in the String Buffer<br>+ UINT8 Voltage; ///< Format defined in SMBIOS Spec v3.0 Section 7.5.4<br>+ UINT16 ExternalClockInMHz; ///< External Clock Frequency. Set to 0 if unknown.<br>+ UINT16 CurrentSpeedInMHz; ///< Snapshot of current processor speed during boot<br>+ UINT8 Status; ///< Format defined in the SMBIOS Spec v3.0 Table 21<br>+ UINT8 ProcessorUpgrade; ///< ENUM defined in SMBIOS Spec v3.0 Section 7.5.5<br>+ /** This info is used for both CoreCount & CoreCount2 fields<br>+ See detailed description in SMBIOS Spec v3.0 Section 7.5.6<br>+ **/<br>+ UINT16 CoreCount;<br>+ /** This info is used for both CoreEnabled & CoreEnabled2 fields<br>+ See detailed description in SMBIOS Spec v3.0 Section 7.5.7<br>+ **/<br>+ UINT16 EnabledCoreCount;<br>+ /** This info is used for both ThreadCount & ThreadCount2 fields<br>+ See detailed description in SMBIOS Spec v3.0 Section 7.5.8<br>+ **/<br>+ UINT16 ThreadCount;<br>+ UINT16 ProcessorCharacteristics; ///< Format defined in SMBIOS Spec v3.0 Section 7.5.9<br>+ /**<br>+ String Buffer - each string terminated by NULL "0x00"<br>+ String buffer terminated by double NULL "0x0000"<br>+ **/<br>+} FSP_SMBIOS_PROCESSOR_INFO;<br>+<br>+typedef struct {<br>+ UINT16 ProcessorSocketNumber;<br>+ UINT16 NumberOfCacheLevels; ///< Based on Number of Cache Types L1/L2/L3<br>+ UINT8 SocketDesignationStrIndex; ///< String Index in the string Buffer. Example "L1-CACHE"<br>+ UINT16 CacheConfiguration; ///< Format defined in SMBIOS Spec v3.0 Section7.8 Table36<br>+ UINT16 MaxCacheSize; ///< Format defined in SMBIOS Spec v3.0 Section7.8.1<br>+ UINT16 InstalledSize; ///< Format defined in SMBIOS Spec v3.0 Section7.8.1<br>+ UINT16 SupportedSramType; ///< Format defined in SMBIOS Spec v3.0 Section7.8.2<br>+ UINT16 CurrentSramType; ///< Format defined in SMBIOS Spec v3.0 Section7.8.2<br>+ UINT8 CacheSpeed; ///< Cache Speed in nanoseconds. 0 if speed is unknown.<br>+ UINT8 ErrorCorrectionType; ///< ENUM Format defined in SMBIOS Spec v3.0 Section 7.8.3<br>+ UINT8 SystemCacheType; ///< ENUM Format defined in SMBIOS Spec v3.0 Section 7.8.4<br>+ UINT8 Associativity; ///< ENUM Format defined in SMBIOS Spec v3.0 Section 7.8.5<br>+ /**<br>+ String Buffer - each string terminated by NULL "0x00"<br>+ String buffer terminated by double NULL "0x0000"<br>+ **/<br>+} FSP_SMBIOS_CACHE_INFO;<br>+<br>+<br>+/** Fsp M Configuration<br>+**/<br>+typedef struct {<br>+<br>+/** Offset 0x0040 - Debug Serial Port Base address<br>+ Debug serial port base address. This option will be used only when the 'Serial Port<br>+ Debug Device' option is set to 'External Device'. 0x00000000(Default).<br>+**/<br>+ UINT32 SerialDebugPortAddress;<br>+<br>+/** Offset 0x0044 - Debug Serial Port Type<br>+ 16550 compatible debug serial port resource type. NONE means no serial port support.<br>+ 0x02:MMIO(Default).<br>+ 0:NONE, 1:I/O, 2:MMIO<br>+**/<br>+ UINT8 SerialDebugPortType;<br>+<br>+/** Offset 0x0045 - Serial Port Debug Device<br>+ Select active serial port device for debug. For SOC UART devices,'Debug Serial Port<br>+ Base' options will be ignored. 0x02:SOC UART2(Default).<br>+ 0:SOC UART0, 1:SOC UART1, 2:SOC UART2, 3:External Device<br>+**/<br>+ UINT8 SerialDebugPortDevice;<br>+<br>+/** Offset 0x0046 - Debug Serial Port Stride Size<br>+ Debug serial port register map stride size in bytes. 0x00:1, 0x02:4(Default).<br>+ 0:1, 2:4<br>+**/<br>+ UINT8 SerialDebugPortStrideSize;<br>+<br>+/** Offset 0x0047 - Memory Fast Boot<br>+ Enable/Disable MRC fast boot support. 0x00:Disable, 0x01:Enable(Default).<br>+ $EN_DIS<br>+**/<br>+ UINT8 MrcFastBoot;<br>+<br>+/** Offset 0x0048 - Integrated Graphics Device<br>+ Enable : Enable Integrated Graphics Device (IGD) when selected as the Primary Video<br>+ Adaptor. Disable: Always disable IGD. 0x00:Disable, 0x01:Enable(Default).<br>+ $EN_DIS<br>+**/<br>+ UINT8 Igd;<br>+<br>+/** Offset 0x0049 - DVMT Pre-Allocated<br>+ Select DVMT 5.0 Pre-Allocated (Fixed) Graphics Memory size used by the Internal<br>+ Graphics Device. 0x02:64 MB(Default).<br>+ 0x02:64 MB, 0x03:96 MB, 0x04:128 MB, 0x05:160 MB, 0x06:192 MB, 0x07:224 MB, 0x08:256<br>+ MB, 0x09:288 MB, 0x0A:320 MB, 0x0B:352 MB, 0x0C:384 MB, 0x0D:416 MB, 0x0E:448 MB,<br>+ 0x0F:480 MB, 0x10:512 MB<br>+**/<br>+ UINT8 IgdDvmt50PreAlloc;<br>+<br>+/** Offset 0x004A - Aperture Size<br>+ Select the Aperture Size used by the Internal Graphics Device. 0x1:128 MB(Default),<br>+ 0x2:256 MB, 0x3:512 MB.<br>+ 0x1:128 MB, 0x2:256 MB, 0x3:512 MB<br>+**/<br>+ UINT8 IgdApertureSize;<br>+<br>+/** Offset 0x004B - GTT Size<br>+ Select the GTT Size used by the Internal Graphics Device. 0x1:2 MB, 0x2:4 MB, 0x3:8<br>+ MB(Default).<br>+ 0x1:2 MB, 0x2:4 MB, 0x3:8 MB<br>+**/<br>+ UINT8 GttSize;<br>+<br>+/** Offset 0x004C - Primary Display<br>+ Select which of IGD/PCI Graphics device should be Primary Display. 0x0:AUTO(Default),<br>+ 0x2:IGD, 0x3:PCI<br>+ 0x0:AUTO, 0x2:IGD, 0x3:PCI<br>+**/<br>+ UINT8 PrimaryVideoAdaptor;<br>+<br>+/** Offset 0x004D - Package<br>+ NOTE: Specifies CA Mapping for all technologies. Supported CA Mappings: 0 - SODIMM(Default);<br>+ 1 - BGA; 2 - BGA mirrored (LPDDR3 only); 3 - SODIMM/UDIMM with Rank 1 Mirrored<br>+ (DDR3L); Refer to the IAFW spec for specific details about each CA mapping.<br>+ 0x0:SODIMM, 0x1:BGA, 0x2:BGA mirrored (LPDDR3 only), 0x3:SODIMM/UDIMM with Rank<br>+ 1 Mirrored (DDR3L)<br>+**/<br>+ UINT8 Package;<br>+<br>+/** Offset 0x004E - Profile<br>+ Profile list. 0x15(Default).<br>+ 0x01:LPDDR3_1333_10_12_12, 0x02:LPDDR3_1600_12_15_15, 0x03:LPDDR3_1866_14_17_17,<br>+ 0x04:LPDDR4_1600_14_15_15, 0x05:LPDDR4_1866_20_17_17, 0x06:LPDDR4_2133_20_20_20,<br>+ 0x07:LPDDR4_2400_24_22_22, 0x08:LPDDR4_2666_24_24_24, 0x09:LPDDR4_3200_28_29_29,<br>+ 0x0A:DDR4_1600_10_10_10, 0x0B:DDR4_1600_11_11_11, 0x0C:DDR4_1600_12_12_12, 0x0D:DDR4_1866_12_12_12,<br>+ 0x0E:DDR4_1866_13_13_13, 0x0F:DDR4_1866_14_14_14, 0x10:DDR4_2133_14_14_14, 0x11:DDR4_2133_15_15_15,<br>+ 0x12:DDR4_2133_16_16_16, 0x13:DDR4_2400_15_15_15, 0x14:DDR4_2400_16_16_16, 0x15:DDR4_2400_17_17_17,<br>+ 0x16:DDR4_2400_18_18_18, 0x17:DDR4_2666_17_17_17, 0x18:DDR4_2666_18_18_18, 0x19:DDR4_2666_19_19_19,<br>+ 0x1A:DDR4_2666_20_20_20<br>+**/<br>+ UINT8 Profile;<br>+<br>+/** Offset 0x004F - MemoryDown<br>+ Memory Down. 0x0(Default).<br>+ 0x0:No, 0x1:Yes, 0x2:1MD+SODIMM (for DDR3L/4 only) ACRD, 0x3:1x32 LPDDR4<br>+**/<br>+ UINT8 MemoryDown;<br>+<br>+/** Offset 0x0050 - DDR3LPageSize<br>+ NOTE: Only for memory down (soldered down memory with no SPD). 0x01:1KB(Default), 0x02:2KB.<br>+ 0x1:1KB, 0x2:2KB<br>+**/<br>+ UINT8 DDR3LPageSize;<br>+<br>+/** Offset 0x0051 - DDR3LASR<br>+ NOTE: Only for memory down. This is specific to ddr3l and used for refresh adjustment<br>+ in Self Refresh, does not affect LP4. 0x00:Not Supported(Default), 0x01:Supported.<br>+ 0x0:Not Supported, 0x1:Supported<br>+**/<br>+ UINT8 DDR3LASR;<br>+<br>+/** Offset 0x0052 - ScramblerSupport<br>+ Scrambler Support - Enable or disable the memory scrambler. Data scrambling is<br>+ provided as a means to increase signal integrity/reduce RFI generated by the DRAM<br>+ interface. This is achieved by randomizing seed that encodes/decodes memory data<br>+ so repeating a worse case pattern is hard to repeat. 00: Disable Scrambler Support,<br>+ 01: Enable Scrambler Support<br>+ $EN_DIS<br>+**/<br>+ UINT8 ScramblerSupport;<br>+<br>+/** Offset 0x0053 - InterleavedMode<br>+ This field is ignored if one of the PnP channel configurations is used. If the memory<br>+ configuration is different, then the field is used directly to populate. 0x00:Disable(Default),<br>+ 0x02:Enable.<br>+ 0x0:Disable, 0x2:Enable<br>+**/<br>+ UINT8 InterleavedMode;<br>+<br>+/** Offset 0x0054 - ChannelHashMask<br>+ ChannelHashMask and SliceHashMask allow for the channel hashing algorithm to be<br>+ modified. These inputs are not used for configurations where an optimized ChannelHashMask<br>+ has been provided by the PnP validation teams. 0x00(Default).<br>+**/<br>+ UINT16 ChannelHashMask;<br>+<br>+/** Offset 0x0056 - SliceHashMask<br>+ ChannelHashMask and SliceHashMask allow for the channel hashing algorithm to be<br>+ modified. These inputs are not used for configurations where an optimized ChannelHashMask<br>+ has been provided by the PnP validation teams. 0x00(Default).<br>+**/<br>+ UINT16 SliceHashMask;<br>+<br>+/** Offset 0x0058 - ChannelsSlicesEnable<br>+ ChannelSlicesEnable field is not used at all on BXTP. The Channel Slice Configuration<br>+ is calculated internally based on the enabled channel configuration. 0x00:Disable(Default),<br>+ 0x01:Enable.<br>+ $EN_DIS<br>+**/<br>+ UINT8 ChannelsSlicesEnable;<br>+<br>+/** Offset 0x0059 - MinRefRate2xEnable<br>+ Provided as a means to defend against Row-Hammer attacks. 0x00:Disable(Default),<br>+ 0x01:Enable.<br>+ $EN_DIS<br>+**/<br>+ UINT8 MinRefRate2xEnable;<br>+<br>+/** Offset 0x005A - DualRankSupportEnable<br>+ Dual Rank Support Enable. 0x00:Disable, 0x01:Enable(Default).<br>+ $EN_DIS<br>+**/<br>+ UINT8 DualRankSupportEnable;<br>+<br>+/** Offset 0x005B - RmtMode<br>+ Rank Margin Tool Mode. 0x00(Default), 0x3(Enabled).<br>+ 0x0:Disabled, 0x3:Enabled<br>+**/<br>+ UINT8 RmtMode;<br>+<br>+/** Offset 0x005C - MemorySizeLimit<br>+ Memory Size Limit: This value is used to restrict the total amount of memory and<br>+ the calculations based on it. Value is in MB. Example encodings are: 0x400 = 1GB,<br>+ 0x800 = 2GB, 0x1000 = 4GB, 0x2000 8GB. 0x0000(Default)<br>+**/<br>+ UINT16 MemorySizeLimit;<br>+<br>+/** Offset 0x005E - LowMemoryMaxValue<br>+ Low Memory Max Value: This value is used to restrict the amount of memory below<br>+ 4GB and the calculations based on it. Value is in MB.Example encodings are: 0x400<br>+ = 1GB, 0x800 = 2GB, 0x1000 = 4GB, 0x2000 8GB. 0x0000(Default).<br>+**/<br>+ UINT16 LowMemoryMaxValue;<br>+<br>+/** Offset 0x0060 - HighMemoryMaxValue<br>+ High Memory Max Value: This value is used to restrict the amount of memory above<br>+ 4GB and the calculations based on it. Value is in MB. Example encodings are: 0x0400:1GB,<br>+ 0x0800:2GB, 0x1000:4GB, 0x2000:8GB. 0x00(Default).<br>+**/<br>+ UINT16 HighMemoryMaxValue;<br>+<br>+/** Offset 0x0062 - DisableFastBoot<br>+ 00:Disabled; Use saved training data (if valid) after first boot(Default), 01:Enabled;<br>+ Full re-train of memory on every boot.<br>+ $EN_DIS<br>+**/<br>+ UINT8 DisableFastBoot;<br>+<br>+/** Offset 0x0063 - DIMM0SPDAddress<br>+ DIMM0 SPD Address (NOTE: Only for DDR3L only. Please put 0 for MemoryDown. 0xA0(Default).<br>+**/<br>+ UINT8 DIMM0SPDAddress;<br>+<br>+/** Offset 0x0064 - DIMM1SPDAddress<br>+ DIMM1 SPD Address (NOTE: Only for DDR3L only. Please put 0 for MemoryDown. 0xA4(Default).<br>+**/<br>+ UINT8 DIMM1SPDAddress;<br>+<br>+/** Offset 0x0065 - Ch0_RankEnable<br>+ NOTE: Only for memory down. This is a bit mask which specifies what ranks are enabled.<br>+ NOTE: Only for memory down (soldered down memory with no SPD): BIT[0] Enable Rank<br>+ 0: Must be set to 1 to enable use of this rank; BIT1[1] Enable Rank 1: Must be<br>+ set to 1 to enable use of this rank.<br>+**/<br>+ UINT8 Ch0_RankEnable;<br>+<br>+/** Offset 0x0066 - Ch0_DeviceWidth<br>+ NOTE: Only for memory down. Must specify the DRAM device width per DRAM channel<br>+ (not to be confused with the SoC Memory Channel width which is always x32 for LPDDR3\LPDDR4<br>+ and x64 for DDR3L). LPDDR4 devices typically have two channels per die and a x16<br>+ device width: 00 - x8; 01 - x16; 10 - x32; 11 - x64<br>+ 0x00:x8, 0x01:x16, 0x02:x32, 0x03:x64<br>+**/<br>+ UINT8 Ch0_DeviceWidth;<br>+<br>+/** Offset 0x0067 - Ch0_DramDensity<br>+ NOTE: Only for memory down. For LPDDR3 and LPDDR4: Must specify the DRAM device<br>+ density per rank (per Chip Select). The simplest way of identifying the density<br>+ per rank is to divide the total SoC memory channel density by the number of ranks.<br>+ For DDR3L: Must specify the DRAM device density per DRAM device. For example, an<br>+ 8GB 2Rx8 configuration will utilize sixteen 4Gb density DRAMS. In this configuration,<br>+ a 4Gb density setting would be selected in the MRC: 000 - 4Gb; 001 - 6Gb; 010 -<br>+ 8Gb; 011 - 12Gb; 100 - 16Gb; 101 - 2Gb; 110-111 - Reserved<br>+ 0x00:4Gb, 0x01:6Gb, 0x02:8Gb, 0x03:12Gb, 0x04:16Gb<br>+**/<br>+ UINT8 Ch0_DramDensity;<br>+<br>+/** Offset 0x0068 - Ch0_Option<br>+ BIT[0] Rank Select Interleaving Enable. See Address Mapping section for full description:<br>+ 0 - Rank Select Interleaving disabled; 1 - Rank Select Interleaving enabled. BIT[1]<br>+ Bank Address Hashing Enable. See Address Mapping section for full description:<br>+ 0 - Bank Address Hashing disabled; 1 - Bank Address Hashing enabled. BIT[2] CH1<br>+ CLK Disable. Disables the CH1 CLK PHY Signal when set to 1. This is used on board<br>+ designs where the CH1 CLK is not routed and left floating or stubbed out: 0 - CH1<br>+ CLK is enabled; 1 - CH1 CLK is disabled. BIT[3] Reserved; BIT[5:4] This register<br>+ specifies the address mapping to be used: 00 - 1KB (A); 01 - 2KB (B)<br>+**/<br>+ UINT8 Ch0_Option;<br>+<br>+/** Offset 0x0069 - Ch0_OdtConfig<br>+ [0] RX ODT - DDR3L & LPDDR3 only: Change the READ ODT strength , for SOC termination<br>+ during a READ transaction, ON DQ BITs. STRONG ==> 60 OHMS roughly, WEAK ==> 120<br>+ OHMS or so roughly. Purpose: Save power on these technologies which burn power<br>+ directly proportional to ODT strength, because ODT looks like a PU and PD (e.g.<br>+ a resistor divider, which always burns power when ODT is ON). 0 - WEAK_ODT_CONFIG,<br>+ 1 - STRONG_ODT_CONFIG. LPDDR4: X - Don't Care. [1] CA ODT - LPDDR4 Only: The<br>+ customer needs to choose this based on their actual board strapping (how they tie<br>+ the DRAM's ODT PINs). Effect: LPDDR4 MR11 will be set based on this setting. CAODT_A_B_HIGH_LOW<br>+ ==> MR11 = 0x34, which is CA ODT = 80 ohms. CAODT_A_B_HIGH_HIGH ==> MR11 = 0x24,<br>+ which is CA ODT = 120 ohms (results in 60 ohm final effective impedance on CA/CLK/CS<br>+ signals). Purpose: To improve signal integrity and provide a much more optimized<br>+ CA VREF value during training. Not to save power. 0 - ODT_AB_HIGH_LOW (default),<br>+ 1 - ODT_AB_HIGH_HIGH. DDR3L & LPDDR3: X - Don't Care. [4] TX ODT. DDR3L only:<br>+ 0 = RZQ/4 (60 Ohms) = MRC_SMIP_DDR3L_TX_ODT_RTT_WR_60_OHMS, 1 = RZQ/2 (120<br>+ Ohms) = MRC_SMIP_DDR3L_TX_ODT_RTT_WR_120_OHMS. LPDDR3 & LPDDR4: X = Don't Care<br>+**/<br>+ UINT8 Ch0_OdtConfig;<br>+<br>+/** Offset 0x006A - Ch0_TristateClk1<br>+ Not used<br>+**/<br>+ UINT8 Ch0_TristateClk1;<br>+<br>+/** Offset 0x006B - Ch0_Mode2N<br>+ DDR3L Only: Configures the DDR3L command timing mode. 2N Mode is a stretched command<br>+ mode that provides more setup and hold time for DRAM commands on the DRAM command<br>+ bus. This is useful for platforms with unusual CMD bus routing or marginal signal<br>+ integrity: 0 - Auto (1N or 2N mode is automatically selected during Command and<br>+ Control training), 1 - Force 2N Mode<br>+ 0x0:Auto, 0x1:Force 2N CMD Timing Mode<br>+**/<br>+ UINT8 Ch0_Mode2N;<br>+<br>+/** Offset 0x006C - Ch0_OdtLevels<br>+ Parameter used to determine if ODT will be held high or low: 0 - ODT Connected to<br>+ SoC, 1 - ODT held high<br>+**/<br>+ UINT8 Ch0_OdtLevels;<br>+<br>+/** Offset 0x006D - Ch1_RankEnable<br>+ NOTE: Only for memory down. This is a bit mask which specifies what ranks are enabled.<br>+ NOTE: Only for memory down (soldered down memory with no SPD): BIT[0] Enable Rank<br>+ 0: Must be set to 1 to enable use of this rank; BIT1[1] Enable Rank 1: Must be<br>+ set to 1 to enable use of this rank.<br>+**/<br>+ UINT8 Ch1_RankEnable;<br>+<br>+/** Offset 0x006E - Ch1_DeviceWidth<br>+ NOTE: Only for memory down. Must specify the DRAM device width per DRAM channel<br>+ (not to be confused with the SoC Memory Channel width which is always x32 for LPDDR3\LPDDR4<br>+ and x64 for DDR3L). LPDDR4 devices typically have two channels per die and a x16<br>+ device width: 00 - x8; 01 - x16; 10 - x32; 11 - x64<br>+ 0x00:x8, 0x01:x16, 0x02:x32, 0x03:x64<br>+**/<br>+ UINT8 Ch1_DeviceWidth;<br>+<br>+/** Offset 0x006F - Ch1_DramDensity<br>+ NOTE: Only for memory down. For LPDDR3 and LPDDR4: Must specify the DRAM device<br>+ density per rank (per Chip Select). The simplest way of identifying the density<br>+ per rank is to divide the total SoC memory channel density by the number of ranks.<br>+ For DDR3L: Must specify the DRAM device density per DRAM device. For example, an<br>+ 8GB 2Rx8 configuration will utilize sixteen 4Gb density DRAMS. In this configuration,<br>+ a 4Gb density setting would be selected in the MRC: 000 - 4Gb; 001 - 6Gb; 010 -<br>+ 8Gb; 011 - 12Gb; 100 - 16Gb; 101 - 2Gb; 110-111 - Reserved<br>+ 0x00:4Gb, 0x01:6Gb, 0x02:8Gb, 0x03:12Gb, 0x04:16Gb<br>+**/<br>+ UINT8 Ch1_DramDensity;<br>+<br>+/** Offset 0x0070 - Ch1_Option<br>+ BIT[0] Rank Select Interleaving Enable. See Address Mapping section for full description:<br>+ 0 - Rank Select Interleaving disabled; 1 - Rank Select Interleaving enabled. BIT[1]<br>+ Bank Address Hashing Enable. See Address Mapping section for full description:<br>+ 0 - Bank Address Hashing disabled; 1 - Bank Address Hashing enabled. BIT[2] CH1<br>+ CLK Disable. Disables the CH1 CLK PHY Signal when set to 1. This is used on board<br>+ designs where the CH1 CLK is not routed and left floating or stubbed out: 0 - CH1<br>+ CLK is enabled; 1 - CH1 CLK is disabled. BIT[3] Reserved; BIT[5:4] This register<br>+ specifies the address mapping to be used: 00 - 1KB (A); 01 - 2KB (B)<br>+**/<br>+ UINT8 Ch1_Option;<br>+<br>+/** Offset 0x0071 - Ch1_OdtConfig<br>+ BIT[0] TX ODT: DDR3L & LPDDR3 only: 0 - WEAK_ODT_CONFIG, 1 - STRONG_ODT_CONFIG;<br>+ LPDDR4: X = Don't Care; BIT[4] RX ODT DDR3L only: 0 = RZQ/4 (60 Ohms) = MRC_SMIP_DDR3L_RX_ODT_RTT_WR_60_OHMS,<br>+ 1 = RZQ/2 (120 Ohms) = MRC_SMIP_DDR3L_RX_ODT_RTT_WR_120_OHMS; LPDDR3 & LPDDR4:<br>+ X = Don't Care<br>+**/<br>+ UINT8 Ch1_OdtConfig;<br>+<br>+/** Offset 0x0072 - Ch1_TristateClk1<br>+ Not used<br>+**/<br>+ UINT8 Ch1_TristateClk1;<br>+<br>+/** Offset 0x0073 - Ch1_Mode2N<br>+ DDR3L Only: Configures the DDR3L command timing mode. 2N Mode is a stretched command<br>+ mode that provides more setup and hold time for DRAM commands on the DRAM command<br>+ bus. This is useful for platforms with unusual CMD bus routing or marginal signal<br>+ integrity: 0 - Auto (1N or 2N mode is automatically selected during Command and<br>+ Control training), 1 - Force 2N Mode<br>+ 0x0:Auto, 0x1:Force 2N CMD Timing Mode<br>+**/<br>+ UINT8 Ch1_Mode2N;<br>+<br>+/** Offset 0x0074 - Ch1_OdtLevels<br>+ DDR3L Only: Parameter used to determine if ODT will be held high or low: 0 - ODT_AB_HIGH_LOW<br>+ (default), 1 - ODT_AB_HIGH_HIGH<br>+**/<br>+ UINT8 Ch1_OdtLevels;<br>+<br>+/** Offset 0x0075 - Ch2_RankEnable<br>+ NOTE: Only for memory down. This is a bit mask which specifies what ranks are enabled.<br>+ NOTE: Only for memory down (soldered down memory with no SPD): BIT[0] Enable Rank<br>+ 0: Must be set to 1 to enable use of this rank; BIT1[1] Enable Rank 1: Must be<br>+ set to 1 to enable use of this rank.<br>+**/<br>+ UINT8 Ch2_RankEnable;<br>+<br>+/** Offset 0x0076 - Ch2_DeviceWidth<br>+ NOTE: Only for memory down. Must specify the DRAM device width per DRAM channel<br>+ (not to be confused with the SoC Memory Channel width which is always x32 for LPDDR3\LPDDR4<br>+ and x64 for DDR3L). LPDDR4 devices typically have two channels per die and a x16<br>+ device width: 00 - x8; 01 - x16; 10 - x32; 11 - x64<br>+ 0x00:x8, 0x01:x16, 0x02:x32, 0x03:x64<br>+**/<br>+ UINT8 Ch2_DeviceWidth;<br>+<br>+/** Offset 0x0077 - Ch2_DramDensity<br>+ NOTE: Only for memory down. For LPDDR3 and LPDDR4: Must specify the DRAM device<br>+ density per rank (per Chip Select). The simplest way of identifying the density<br>+ per rank is to divide the total SoC memory channel density by the number of ranks.<br>+ For DDR3L: Must specify the DRAM device density per DRAM device. For example, an<br>+ 8GB 2Rx8 configuration will utilize sixteen 4Gb density DRAMS. In this configuration,<br>+ a 4Gb density setting would be selected in the MRC: 000 - 4Gb; 001 - 6Gb; 010 -<br>+ 8Gb; 011 - 12Gb; 100 - 16Gb; 101 - 2Gb; 110-111 - Reserved<br>+ 0x00:4Gb, 0x01:6Gb, 0x02:8Gb, 0x03:12Gb, 0x04:16Gb<br>+**/<br>+ UINT8 Ch2_DramDensity;<br>+<br>+/** Offset 0x0078 - Ch2_Option<br>+ BIT[0] Rank Select Interleaving Enable. See Address Mapping section for full description:<br>+ 0 - Rank Select Interleaving disabled; 1 - Rank Select Interleaving enabled. BIT[1]<br>+ Bank Address Hashing Enable. See Address Mapping section for full description:<br>+ 0 - Bank Address Hashing disabled; 1 - Bank Address Hashing enabled. BIT[2] CH1<br>+ CLK Disable. Disables the CH1 CLK PHY Signal when set to 1. This is used on board<br>+ designs where the CH1 CLK is not routed and left floating or stubbed out: 0 - CH1<br>+ CLK is enabled; 1 - CH1 CLK is disabled. BIT[3] Reserved; BIT[5:4] This register<br>+ specifies the address mapping to be used: 00 - 1KB (A); 01 - 2KB (B)<br>+**/<br>+ UINT8 Ch2_Option;<br>+<br>+/** Offset 0x0079 - Ch2_OdtConfig<br>+ BIT[0] TX ODT: DDR3L & LPDDR3 only: 0 - WEAK_ODT_CONFIG, 1 - STRONG_ODT_CONFIG;<br>+ LPDDR4: X = Don't Care; BIT[4] RX ODT DDR3L only: 0 = RZQ/4 (60 Ohms) = MRC_SMIP_DDR3L_RX_ODT_RTT_WR_60_OHMS,<br>+ 1 = RZQ/2 (120 Ohms) = MRC_SMIP_DDR3L_RX_ODT_RTT_WR_120_OHMS; LPDDR3 & LPDDR4:<br>+ X = Don't Care<br>+**/<br>+ UINT8 Ch2_OdtConfig;<br>+<br>+/** Offset 0x007A - Ch2_TristateClk1<br>+ Not used<br>+**/<br>+ UINT8 Ch2_TristateClk1;<br>+<br>+/** Offset 0x007B - Ch2_Mode2N<br>+ DDR3L Only: Configures the DDR3L command timing mode. 2N Mode is a stretched command<br>+ mode that provides more setup and hold time for DRAM commands on the DRAM command<br>+ bus. This is useful for platforms with unusual CMD bus routing or marginal signal<br>+ integrity: 0 - Auto (1N or 2N mode is automatically selected during Command and<br>+ Control training), 1 - Force 2N Mode<br>+ 0x0:Auto, 0x1:Force 2N CMD Timing Mode<br>+**/<br>+ UINT8 Ch2_Mode2N;<br>+<br>+/** Offset 0x007C - Ch2_OdtLevels<br>+ DDR3L Only: Parameter used to determine if ODT will be held high or low: 0 - ODT_AB_HIGH_LOW<br>+ (default), 1 - ODT_AB_HIGH_HIGH<br>+**/<br>+ UINT8 Ch2_OdtLevels;<br>+<br>+/** Offset 0x007D - Ch3_RankEnable<br>+ NOTE: Only for memory down. This is a bit mask which specifies what ranks are enabled.<br>+ NOTE: Only for memory down (soldered down memory with no SPD): BIT[0] Enable Rank<br>+ 0: Must be set to 1 to enable use of this rank; BIT1[1] Enable Rank 1: Must be<br>+ set to 1 to enable use of this rank.<br>+**/<br>+ UINT8 Ch3_RankEnable;<br>+<br>+/** Offset 0x007E - Ch3_DeviceWidth<br>+ NOTE: Only for memory down. Must specify the DRAM device width per DRAM channel<br>+ (not to be confused with the SoC Memory Channel width which is always x32 for LPDDR3\LPDDR4<br>+ and x64 for DDR3L). LPDDR4 devices typically have two channels per die and a x16<br>+ device width: 00 - x8; 01 - x16; 10 - x32; 11 - x64<br>+ 0x00:x8, 0x01:x16, 0x02:x32, 0x03:x64<br>+**/<br>+ UINT8 Ch3_DeviceWidth;<br>+<br>+/** Offset 0x007F - Ch3_DramDensity<br>+ NOTE: Only for memory down. For LPDDR3 and LPDDR4: Must specify the DRAM device<br>+ density per rank (per Chip Select). The simplest way of identifying the density<br>+ per rank is to divide the total SoC memory channel density by the number of ranks.<br>+ For DDR3L: Must specify the DRAM device density per DRAM device. For example, an<br>+ 8GB 2Rx8 configuration will utilize sixteen 4Gb density DRAMS. In this configuration,<br>+ a 4Gb density setting would be selected in the MRC: 000 - 4Gb; 001 - 6Gb; 010 -<br>+ 8Gb; 011 - 12Gb; 100 - 16Gb; 101 - 2Gb; 110-111 - Reserved<br>+ 0x00:4Gb, 0x01:6Gb, 0x02:8Gb, 0x03:12Gb, 0x04:16Gb<br>+**/<br>+ UINT8 Ch3_DramDensity;<br>+<br>+/** Offset 0x0080 - Ch3_Option<br>+ BIT[0] Rank Select Interleaving Enable. See Address Mapping section for full description:<br>+ 0 - Rank Select Interleaving disabled; 1 - Rank Select Interleaving enabled. BIT[1]<br>+ Bank Address Hashing Enable. See Address Mapping section for full description:<br>+ 0 - Bank Address Hashing disabled; 1 - Bank Address Hashing enabled. BIT[2] CH1<br>+ CLK Disable. Disables the CH1 CLK PHY Signal when set to 1. This is used on board<br>+ designs where the CH1 CLK is not routed and left floating or stubbed out: 0 - CH1<br>+ CLK is enabled; 1 - CH1 CLK is disabled. BIT[3] Reserved; BIT[5:4] This register<br>+ specifies the address mapping to be used: 00 - 1KB (A); 01 - 2KB (B)<br>+**/<br>+ UINT8 Ch3_Option;<br>+<br>+/** Offset 0x0081 - Ch3_OdtConfig<br>+ BIT[0] TX ODT: DDR3L & LPDDR3 only: 0 - WEAK_ODT_CONFIG, 1 - STRONG_ODT_CONFIG;<br>+ LPDDR4: X = Don't Care; BIT[4] RX ODT DDR3L only: 0 = RZQ/4 (60 Ohms) = MRC_SMIP_DDR3L_RX_ODT_RTT_WR_60_OHMS,<br>+ 1 = RZQ/2 (120 Ohms) = MRC_SMIP_DDR3L_RX_ODT_RTT_WR_120_OHMS; LPDDR3 & LPDDR4:<br>+ X = Don't Care<br>+**/<br>+ UINT8 Ch3_OdtConfig;<br>+<br>+/** Offset 0x0082 - Ch3_TristateClk1<br>+ Not used<br>+**/<br>+ UINT8 Ch3_TristateClk1;<br>+<br>+/** Offset 0x0083 - Ch3_Mode2N<br>+ DDR3L Only: Configures the DDR3L command timing mode. 2N Mode is a stretched command<br>+ mode that provides more setup and hold time for DRAM commands on the DRAM command<br>+ bus. This is useful for platforms with unusual CMD bus routing or marginal signal<br>+ integrity: 0 - Auto (1N or 2N mode is automatically selected during Command and<br>+ Control training), 1 - Force 2N Mode<br>+ 0x0:Auto, 0x1:Force 2N CMD Timing Mode<br>+**/<br>+ UINT8 Ch3_Mode2N;<br>+<br>+/** Offset 0x0084 - Ch3_OdtLevels<br>+ DDR3L Only: Parameter used to determine if ODT will be held high or low: 0 - ODT_AB_HIGH_LOW<br>+ (default), 1 - ODT_AB_HIGH_HIGH<br>+**/<br>+ UINT8 Ch3_OdtLevels;<br>+<br>+/** Offset 0x0085 - RmtCheckRun<br>+ Parameter used to determine whether to run the margin check. Bit 0 is used for MINIMUM<br>+ MARGIN CHECK and bit 1 is used for DEGRADE MARGIN CHECK<br>+**/<br>+ UINT8 RmtCheckRun;<br>+<br>+/** Offset 0x0086 - RmtMarginCheckScaleHighThreshold<br>+ Percentage used to determine the margin tolerances over the failing margin.<br>+**/<br>+ UINT16 RmtMarginCheckScaleHighThreshold;<br>+<br>+/** Offset 0x0088 - Ch0_Bit_swizzling<br>+ Channel 0 PHY to DUnit DQ mapping (only used if not 1-1 mapping)Range: 0-32. Frequently<br>+ asked questions: Q: The DQS (strobes) need to go with the corresponding byte lanes<br>+ on the DDR module. Are the DQS being swapped around as well? Ans: Yes, DQ strobes<br>+ need to follow the DQ byte lane they correspond too. So for example if you have<br>+ DQ[7:0] swapped with DQ[15:8], DQS0 pair also need to be swapped with DQS1 pair.<br>+ Also, the spreadsheet used for Amenia is essentially a swizzle value lookup that<br>+ specifies what DRAM DQ bit a particular SoC DQ bit is connected to. Some confusion<br>+ can arrise from the fact that the indexes to the array do not necessarily map 1:1<br>+ to an SoC DQ pin. For example, the CH0 array at index 0 maps to SoC DQB8. The value<br>+ of 9 at index 0 tells us that SoC DQB8 is connected to DRAM DQA9. Q: The PDG indicates<br>+ a 2 physical channels need to be stuffed and operated together. Are the CHx_A and<br>+ CHx_B physical channels operated in tandem or completely separate? If separate,<br>+ why requirement of pairing them? Ans: We have 2 PHY instances on the SoC each supporting<br>+ up to 2 x32 LP4 channels. If you have 4 channels both PHYs are active, but if you<br>+ have 2 channels in order to power gate one PHY, those two channel populated must<br>+ be on one PHY instance. So yes all channels are independent of each other, but<br>+ there are some restrictions on how they need to be populated. Q: How is it that<br>+ an LPDDR4 device is identified as having a x16 width when all 32-bits are used<br>+ at the same time with a single chip select? That's effectively a x32 device. Ans:LPDDR4<br>+ DRAM devices are x16. Each die has 2 x16 devices on them. To make a x32 channel<br>+ the CS of the two devices in the same die are connected together to make a single<br>+ rank of one x32 channel (SDP). The second die in the DDP package makes the second rank.<br>+**/<br>+ UINT8 Ch0_Bit_swizzling[32];<br>+<br>+/** Offset 0x00A8 - Ch1_Bit_swizzling<br>+ Channel 1 PHY to DUnit DQ mapping (only used if not 1-1 mapping)Range: 0-32.<br>+**/<br>+ UINT8 Ch1_Bit_swizzling[32];<br>+<br>+/** Offset 0x00C8 - Ch2_Bit_swizzling<br>+ Channel 2 PHY to DUnit DQ mapping (only used if not 1-1 mapping)Range: 0-32.<br>+**/<br>+ UINT8 Ch2_Bit_swizzling[32];<br>+<br>+/** Offset 0x00E8 - Ch3_Bit_swizzling<br>+ Channel 3 PHY to DUnit DQ mapping (only used if not 1-1 mapping)Range: 0-32.<br>+**/<br>+ UINT8 Ch3_Bit_swizzling[32];<br>+<br>+/** Offset 0x0108 - MsgLevelMask<br>+ 32 bits used to mask out debug messages. Masking out bit 0 mask all other messages.<br>+**/<br>+ UINT32 MsgLevelMask;<br>+<br>+/** Offset 0x010C<br>+**/<br>+ UINT8 UnusedUpdSpace0[4];<br>+<br>+/** Offset 0x0110 - PreMem GPIO Pin Number for each table<br>+ Number of Pins in each PreMem GPIO Table. 0(Default).<br>+**/<br>+ UINT8 PreMemGpioTablePinNum[4];<br>+<br>+/** Offset 0x0114 - PreMem GPIO Table Pointer<br>+ Pointer to Array of pointers to PreMem GPIO Table. 0x00000000(Default).<br>+**/<br>+ UINT32 PreMemGpioTablePtr;<br>+<br>+/** Offset 0x0118 - PreMem GPIO Table Entry Number. Currently maximum entry number is 4<br>+ Number of Entries in PreMem GPIO Table. 0(Default).<br>+**/<br>+ UINT8 PreMemGpioTableEntryNum;<br>+<br>+/** Offset 0x0119 - Enhance the port 8xh decoding<br>+ Enable/Disable Enhance the port 8xh decoding. 0:Disable, 1:Enable(Default).<br>+ $EN_DIS<br>+**/<br>+ UINT8 EnhancePort8xhDecoding;<br>+<br>+/** Offset 0x011A - SPD Data Write<br>+ Enable/Disable SPD data write on the SMBUS. 0x00:Disable(Default), 0x01:Enable.<br>+ $EN_DIS<br>+**/<br>+ UINT8 SpdWriteEnable;<br>+<br>+/** Offset 0x011B - MRC Training Data Saving<br>+ Enable/Disable MRC training data saving in FSP. 0x00:Disable(Default), 0x01:Enable.<br>+ $EN_DIS<br>+**/<br>+ UINT8 MrcDataSaving;<br>+<br>+/** Offset 0x011C - OEM File Loading Address<br>+ Determine the memory base address to load a specified file from CSE file system<br>+ after memory is available.<br>+**/<br>+ UINT32 OemLoadingBase;<br>+<br>+/** Offset 0x0120 - OEM File Name to Load<br>+ Specify a file name to load from CSE file system after memory is available. Empty<br>+ indicates no file needs to be loaded.<br>+**/<br>+ UINT8 OemFileName[16];<br>+<br>+/** Offset 0x0130<br>+**/<br>+ VOID* MrcBootDataPtr;<br>+<br>+/** Offset 0x0134 - eMMC Trace Length<br>+ Select eMMC trace length to load OEM file from when loading OEM file name is specified.<br>+ 0x0:Long(Default), 0x1:Short.<br>+ 0x0:Long, 0x1:Short<br>+**/<br>+ UINT8 eMMCTraceLen;<br>+<br>+/** Offset 0x0135 - Skip CSE RBP to support zero sized IBB<br>+ Enable/Disable skip CSE RBP for bootloader which loads IBB without assistance of<br>+ CSE. 0x00:Disable(Default), 0x01:Enable.<br>+ $EN_DIS<br>+**/<br>+ UINT8 SkipCseRbp;<br>+<br>+/** Offset 0x0136 - Trace Hub Enable<br>+ Disable Npk/Host Debugger/Target Debugger. 0:Disable(Default), 1:Host Debugger,<br>+ 2:Target Debugger.<br>+ 0:Disable, 1:Host Debugger, 2:Target Debugger<br>+**/<br>+ UINT8 TraceHubEn;<br>+<br>+/** Offset 0x0137 - FW Trace Enable<br>+ Enable/Disable FW Trace. 0:Disable, 1:Enable(Default).<br>+ $EN_DIS<br>+**/<br>+ UINT8 FwTraceEn;<br>+<br>+/** Offset 0x0138 - FW Trace Destination<br>+ FW Trace Destination. 1-NPK_TRACE_TO_MEMORY, 2-NPK_TRACE_TO_DCI, 3-NPK_TRACE_TO_BSSB,<br>+ 4-NPK_TRACE_TO_PTI(Default).<br>+**/<br>+ UINT8 FwTraceDestination;<br>+<br>+/** Offset 0x0139 - NPK Recovery Dump<br>+ Enable/Disable NPK Recovery Dump. 0:Disable(Default), 1:Enable.<br>+ $EN_DIS<br>+**/<br>+ UINT8 RecoverDump;<br>+<br>+/** Offset 0x013A - Memory Region 0 Buffer WrapAround<br>+ Memory Region 0 Buffer WrapAround. 0-n0-warp, 1-warp(Default).<br>+**/<br>+ UINT8 Msc0Wrap;<br>+<br>+/** Offset 0x013B - Memory Region 1 Buffer WrapAround<br>+ Memory Region 1 Buffer WrapAround. 0-n0-warp, 1-warp(Default).<br>+**/<br>+ UINT8 Msc1Wrap;<br>+<br>+/** Offset 0x013C - Memory Region 0 Buffer Size<br>+ Memory Region 0 Buffer Size. 0-0MB(Default), 1-1MB, 2-8MB, 3-64MB, 4-128MB, 5-256MB,<br>+ 6-512MB, 7-1GB.<br>+**/<br>+ UINT32 Msc0Size;<br>+<br>+/** Offset 0x0140 - Memory Region 1 Buffer Size<br>+ Memory Region 1 Buffer Size, 0-0MB(Default), 1-1MB, 2-8MB, 3-64MB, 4-128MB, 5-256MB,<br>+ 6-512MB, 7-1GB.<br>+**/<br>+ UINT32 Msc1Size;<br>+<br>+/** Offset 0x0144 - PTI Mode<br>+ PTI Mode. 0-0ff, 1-x4(Default), 2-x8, 3-x12, 4-x16.<br>+**/<br>+ UINT8 PtiMode;<br>+<br>+/** Offset 0x0145 - PTI Training<br>+ PTI Training. 0-off(Default), 1-6=1-6.<br>+**/<br>+ UINT8 PtiTraining;<br>+<br>+/** Offset 0x0146 - PTI Speed<br>+ PTI Speed. 0-full, 1-half, 2-quarter(Default).<br>+**/<br>+ UINT8 PtiSpeed;<br>+<br>+/** Offset 0x0147 - Punit Message Level<br>+ Punit Message Output Verbosity Level. 0, 1(Default), 2-4=2-4.<br>+**/<br>+ UINT8 PunitMlvl;<br>+<br>+/** Offset 0x0148 - PMC Message Level<br>+ PMC Message Output Verbosity Level. 0, 1(Default), 2-4=2-4.<br>+**/<br>+ UINT8 PmcMlvl;<br>+<br>+/** Offset 0x0149 - SW Trace Enable<br>+ Enable/Disable SW Trace. 0:Disable(Default), 1:Enable.<br>+ $EN_DIS<br>+**/<br>+ UINT8 SwTraceEn;<br>+<br>+/** Offset 0x014A - SGX mode<br>+ Select SGX mode. 0:Disable, 1:Enable, 2:Software control (default)<br>+ 0:Disable, 1:Enable, 2:Software control (default)<br>+**/<br>+ UINT8 EnableSgx;<br>+<br>+/** Offset 0x014B - PRMRR size<br>+ PRMRR size. 0:Invalid (default), 1:32MB, 2:64MB 3:128MB<br>+ 0:Invalid (default), 1:32MB, 2:64MB 3:128MB<br>+**/<br>+ UINT32 PrmrrSize;<br>+<br>+/** Offset 0x014F - Periodic Retraining Disable<br>+ Periodic Retraining Disable - This option allows customers to disable LPDDR4 Periodic<br>+ Retraining for debug purposes. Periodic Retraining should be enabled in production.<br>+ Periodic retraining allows the platform to operate reliably over a larger voltage<br>+ and temperature range. This field has no effect for DDR3L and LPDDR3 memory type<br>+ configurations. 0x00: Enable Periodic Retraining (default); 0x01: Disable Periodic<br>+ Retraining (debug configuration only)<br>+ 0x0:Enabled, 0x1:Disabled<br>+**/<br>+ UINT8 PeriodicRetrainingDisable;<br>+<br>+/** Offset 0x0150 - Enable Reset System<br>+ Enable FSP to trigger reset instead of returning reset request. 0x00: Return the<br>+ Return Status from FSP if a reset is required. (default); 0x01: Perform Reset inside<br>+ FSP instead of returning from the API.<br>+ 0x0:Disabled, 0x1:Eabled<br>+**/<br>+ UINT8 EnableResetSystem;<br>+<br>+/** Offset 0x0151 - Enable HECI2 in S3 resume path<br>+ Enable HECI2 in S3 resume path. 0x00: Skip HECI2 initialization in S3 resume. ;<br>+ 0x01: Enable HECI2 in S3 resume path.(Default)<br>+ 0x0:Disabled, 0x1:Eabled<br>+**/<br>+ UINT8 EnableS3Heci2;<br>+<br>+/** Offset 0x0152 - PCI Express Root Port<br>+ Control the PCI Express Root Port . 0:Disable, 1:Enable, 2:Auto(Default).<br>+**/<br>+ UINT8 PcieRootPortEn[6];<br>+<br>+/** Offset 0x0158 - PCIE SLOT Power Enable Assert Time - PFET.<br>+ ACPI Timer Ticker to measure when PCIE Slot Power is enabled through PFET. FSP will<br>+ wait for 100ms for the power to be stable, before de-asserting PERST bin. Customer<br>+ who designed the board PCIE slot Power automatically enabled, can pass value of<br>+ zero here.<br>+**/<br>+ UINT64 StartTimerTickerOfPfetAssert;<br>+<br>+/** Offset 0x0160<br>+**/<br>+ VOID* VariableNvsBufferPtr;<br>+<br>+/** Offset 0x0164<br>+**/<br>+ UINT8 ReservedFspmUpd[4];<br>+} FSP_M_CONFIG;<br>+<br>+/** Fsp M Test Configuration<br>+**/<br>+typedef struct {<br>+<br>+/** Offset 0x0168<br>+**/<br>+ UINT32 Signature;<br>+<br>+/** Offset 0x016C<br>+**/<br>+ UINT8 ReservedFspmTestUpd[18];<br>+} FSP_M_TEST_CONFIG;<br>+<br>+/** Fsp M Restricted Configuration<br>+**/<br>+typedef struct {<br>+<br>+/** Offset 0x017E<br>+**/<br>+ UINT32 Signature;<br>+<br>+/** Offset 0x0182<br>+**/<br>+ UINT8 ReservedFspmRestrictedUpd[124];<br>+} FSP_M_RESTRICTED_CONFIG;<br>+<br>+/** Fsp M UPD Configuration<br>+**/<br>+typedef struct {<br>+<br>+/** Offset 0x0000<br>+**/<br>+ FSP_UPD_HEADER FspUpdHeader;<br>+<br>+/** Offset 0x0020<br>+**/<br>+ FSPM_ARCH_UPD FspmArchUpd;<br>+<br>+/** Offset 0x0040<br>+**/<br>+ FSP_M_CONFIG FspmConfig;<br>+<br>+/** Offset 0x0168<br>+**/<br>+ FSP_M_TEST_CONFIG FspmTestConfig;<br>+<br>+/** Offset 0x017E<br>+**/<br>+ FSP_M_RESTRICTED_CONFIG FspmRestrictedConfig;<br>+<br>+/** Offset 0x01FE<br>+**/<br>+ UINT16 UpdTerminator;<br>+} FSPM_UPD;<br>+<br>+#pragma pack()<br>+<br>+#endif<br>diff --git a/src/vendorcode/intel/fsp/fsp2_0/glk/FspsUpd.h b/src/vendorcode/intel/fsp/fsp2_0/glk/FspsUpd.h<br>index 081fb94..54c8c5f 100644<br>--- a/src/vendorcode/intel/fsp/fsp2_0/glk/FspsUpd.h<br>+++ b/src/vendorcode/intel/fsp/fsp2_0/glk/FspsUpd.h<br>@@ -1,1708 +1,1732 @@<br>-/** @file<br>-<br>-Copyright (c) 2017, Intel Corporation. All rights reserved.<BR><br>-<br>-Redistribution and use in source and binary forms, with or without modification,<br>-are permitted provided that the following conditions are met:<br>-<br>-* Redistributions of source code must retain the above copyright notice, this<br>- list of conditions and the following disclaimer.<br>-* Redistributions in binary form must reproduce the above copyright notice, this<br>- list of conditions and the following disclaimer in the documentation and/or<br>- other materials provided with the distribution.<br>-* Neither the name of Intel Corporation nor the names of its contributors may<br>- be used to endorse or promote products derived from this software without<br>- specific prior written permission.<br>-<br>- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"<br>- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE<br>- IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE<br>- ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE<br>- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR<br>- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF<br>- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS<br>- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN<br>- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)<br>- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF<br>- THE POSSIBILITY OF SUCH DAMAGE.<br>-<br>- This file is automatically generated. Please do NOT modify !!!<br>-<br>-**/<br>-<br>-#ifndef __FSPSUPD_H__<br>-#define __FSPSUPD_H__<br>-<br>-#include <FspUpd.h><br>-<br>-#pragma pack(push, 1)<br>-<br>-<br>-/** Fsp S Configuration<br>-**/<br>-typedef struct {<br>-<br>-/** Offset 0x0020 - ActiveProcessorCores<br>- Number of active cores. 0:Disable(Default), 1:Enable.<br>-**/<br>- UINT8 ActiveProcessorCores;<br>-<br>-/** Offset 0x0021 - Disable Core1<br>- Disable/Enable Core1. 0:Disable, 1:Enable(Default).<br>- $EN_DIS<br>-**/<br>- UINT8 DisableCore1;<br>-<br>-/** Offset 0x0022 - Disable Core2<br>- Disable/Enable Core2. 0:Disable, 1:Enable(Default).<br>- $EN_DIS<br>-**/<br>- UINT8 DisableCore2;<br>-<br>-/** Offset 0x0023 - Disable Core3<br>- Disable/Enable Core3. 0:Disable, 1:Enable(Default).<br>- $EN_DIS<br>-**/<br>- UINT8 DisableCore3;<br>-<br>-/** Offset 0x0024 - VMX Enable<br>- Enable or Disable VMX. 0:Disable, 1:Enable(Default).<br>- $EN_DIS<br>-**/<br>- UINT8 VmxEnable;<br>-<br>-/** Offset 0x0025 - Memory region allocation for Processor Trace<br>- Memory region allocation for Processor Trace, allowed range is from 4K (0x0) to<br>- 128MB (0xF); <b>0xFF: Disable. 0xFF:Disable(Default)<br>-**/<br>- UINT8 ProcTraceMemSize;<br>-<br>-/** Offset 0x0026 - Enable Processor Trace<br>- Enable or Disable Processor Trace feature. 0:Disable(Default), 1:Enable.<br>- $EN_DIS<br>-**/<br>- UINT8 ProcTraceEnable;<br>-<br>-/** Offset 0x0027 - Eist<br>- Enable or Disable Intel SpeedStep Technology. 0:Disable, 1:Enable(Default).<br>- $EN_DIS<br>-**/<br>- UINT8 Eist;<br>-<br>-/** Offset 0x0028 - Boot PState<br>- Boot PState with HFM or LFM. 0:HFM(Default), 1:LFM.<br>-**/<br>- UINT8 BootPState;<br>-<br>-/** Offset 0x0029 - CPU power states (C-states)<br>- Enable or Disable CPU power states (C-states). 0:Disable, 1:Enable(Default).<br>- $EN_DIS<br>-**/<br>- UINT8 EnableCx;<br>-<br>-/** Offset 0x002A - Enhanced C-states<br>- Enable or Disable Enhanced C-states. 0:Disable(Default), 1:Enable.<br>- $EN_DIS<br>-**/<br>- UINT8 C1e;<br>-<br>-/** Offset 0x002B - Bi-Directional PROCHOT#<br>- Enable or Disable Bi-Directional PROCHOT#. 0:Disable, 1:Enable(Default).<br>- $EN_DIS<br>-**/<br>- UINT8 BiProcHot;<br>-<br>-/** Offset 0x002C - Max Pkg Cstate<br>- Max Pkg Cstate. 0:PkgC0C1, 1:PkgC2, 2:PkgC3(Default), 3:PkgC6, 4:PkgC7, 5:PkgC7s,<br>- 6:PkgC8, 7:PkgC9, 8:PkgC10, 9:PkgCMax, 254:PkgCpuDefault, 255:PkgAuto.<br>-**/<br>- UINT8 PkgCStateLimit;<br>-<br>-/** Offset 0x002D - C-State auto-demotion<br>- C-State Auto Demotion. 0:Disable(Default) C1 and C3 Auto-demotion, 1:Enable C3/C6/C7<br>- Auto-demotion to C1, 2:Enable C6/C7 Auto-demotion to C3, 3:Enable C6/C7 Auto-demotion<br>- to C1 and C3.<br>-**/<br>- UINT8 CStateAutoDemotion;<br>-<br>-/** Offset 0x002E - C-State un-demotion<br>- C-State un-demotion. 0:Disable(Default) C1 and C3 Un-demotion, 1:Enable C1 Un-demotion,<br>- 2:Enable C3 Un-demotion, 3:Enable C1 and C3 Un-demotion.<br>-**/<br>- UINT8 CStateUnDemotion;<br>-<br>-/** Offset 0x002F - Max Core C-State<br>- Max Core C-State. 0:Unlimited, 1:C1, 2:C3, 3:C6, 4:C7, 5:C8, 6:C9, 7:C10, 8:CCx(Default).<br>-**/<br>- UINT8 MaxCoreCState;<br>-<br>-/** Offset 0x0030 - Package C-State Demotion<br>- Enable or Disable Package Cstate Demotion. 0:Disable(Default), 1:Enable.<br>- $EN_DIS<br>-**/<br>- UINT8 PkgCStateDemotion;<br>-<br>-/** Offset 0x0031 - Package C-State Un-demotion<br>- Enable or Disable Package Cstate UnDemotion. 0:Disable(Default), 1:Enable.<br>- $EN_DIS<br>-**/<br>- UINT8 PkgCStateUnDemotion;<br>-<br>-/** Offset 0x0032 - Turbo Mode<br>- Enable or Disable long duration Turbo Mode. 0:Disable, 1:Enable(Default).<br>- $EN_DIS<br>-**/<br>- UINT8 TurboMode;<br>-<br>-/** Offset 0x0033 - SC HDA Verb Table Entry Number<br>- Number of Entries in Verb Table. 0(Default).<br>-**/<br>- UINT8 HdaVerbTableEntryNum;<br>-<br>-/** Offset 0x0034 - SC HDA Verb Table Pointer<br>- Pointer to Array of pointers to Verb Table. 0x00000000(Default).<br>-**/<br>- UINT32 HdaVerbTablePtr;<br>-<br>-/** Offset 0x0038 - Enable/Disable P2SB device hidden.<br>- Enable/Disable P2SB device hidden. 0:Disable(Default), 1:Enable.<br>- $EN_DIS<br>-**/<br>- UINT8 P2sbUnhide;<br>-<br>-/** Offset 0x0039 - IPU Enable/Disable<br>- Enable/Disable IPU Device. 0:Disable, 1:Enable(Default).<br>- $EN_DIS<br>-**/<br>- UINT8 IpuEn;<br>-<br>-/** Offset 0x003A - IMGU ACPI mode selection<br>- 0:Auto, 1:IGFX Child device(Default), 2:ACPI device.<br>- 0:Disable, 1:IGFX Child device, 2:ACPI device<br>-**/<br>- UINT8 IpuAcpiMode;<br>-<br>-/** Offset 0x003B - Enable ForceWake<br>- Enable/disable ForceWake Models. 0:Disable(Default), 1:Enable.<br>- $EN_DIS<br>-**/<br>- UINT8 ForceWake;<br>-<br>-/** Offset 0x003C - GttMmAdr<br>- GttMmAdr structure for initialization. 0xBF000000(Default).<br>-**/<br>- UINT32 GttMmAdr;<br>-<br>-/** Offset 0x0040 - GmAdr<br>- GmAdr structure for initialization. 0xA0000000(Default).<br>-**/<br>- UINT32 GmAdr;<br>-<br>-/** Offset 0x0044 - Enable PavpLock<br>- Enable/disable PavpLock. 0:Disable(Default), 1:Enable.<br>- $EN_DIS<br>-**/<br>- UINT8 PavpLock;<br>-<br>-/** Offset 0x0045 - Enable GraphicsFreqModify<br>- Enable/disable GraphicsFreqModify. 0:Disable(Default), 1:Enable.<br>- $EN_DIS<br>-**/<br>- UINT8 GraphicsFreqModify;<br>-<br>-/** Offset 0x0046 - Enable GraphicsFreqReq<br>- Enable/disable GraphicsFreqReq. 0:Disable(Default), 1:Enable.<br>- $EN_DIS<br>-**/<br>- UINT8 GraphicsFreqReq;<br>-<br>-/** Offset 0x0047 - Enable GraphicsVideoFreq<br>- Enable/disable GraphicsVideoFreq. 0:Disable(Default), 1:Enable.<br>- $EN_DIS<br>-**/<br>- UINT8 GraphicsVideoFreq;<br>-<br>-/** Offset 0x0048 - Enable PmLock<br>- Enable/disable PmLock. 0:Disable(Default), 1:Enable.<br>- $EN_DIS<br>-**/<br>- UINT8 PmLock;<br>-<br>-/** Offset 0x0049 - Enable DopClockGating<br>- Enable/disable DopClockGating. 0:Disable(Default), 1:Enable.<br>- $EN_DIS<br>-**/<br>- UINT8 DopClockGating;<br>-<br>-/** Offset 0x004A - Enable UnsolicitedAttackOverride<br>- Enable/disable UnsolicitedAttackOverride. 0:Disable(Default), 1:Enable.<br>- $EN_DIS<br>-**/<br>- UINT8 UnsolicitedAttackOverride;<br>-<br>-/** Offset 0x004B - Enable WOPCMSupport<br>- Enable/disable WOPCMSupport. 0:Disable(Default), 1:Enable.<br>- $EN_DIS<br>-**/<br>- UINT8 WOPCMSupport;<br>-<br>-/** Offset 0x004C - Enable WOPCMSize<br>- Enable/disable WOPCMSize. 0:Disable(Default), 1:Enable.<br>- $EN_DIS<br>-**/<br>- UINT8 WOPCMSize;<br>-<br>-/** Offset 0x004D - Enable PowerGating<br>- Enable/disable PowerGating. 0:Disable(Default), 1:Enable.<br>- $EN_DIS<br>-**/<br>- UINT8 PowerGating;<br>-<br>-/** Offset 0x004E - Enable UnitLevelClockGating<br>- Enable/disable UnitLevelClockGating. 0:Disable(Default), 1:Enable.<br>- $EN_DIS<br>-**/<br>- UINT8 UnitLevelClockGating;<br>-<br>-/** Offset 0x004F - Enable FastBoot<br>- Enable/disable FastBoot. 0:Disable(Default), 1:Enable.<br>- $EN_DIS<br>-**/<br>- UINT8 FastBoot;<br>-<br>-/** Offset 0x0050 - Enable DynSR<br>- Enable/disable DynSR. 0:Disable(Default), 1:Enable.<br>- $EN_DIS<br>-**/<br>- UINT8 DynSR;<br>-<br>-/** Offset 0x0051 - Enable SaIpuEnable<br>- Enable/disable SaIpuEnable. 0:Disable(Default), 1:Enable.<br>- $EN_DIS<br>-**/<br>- UINT8 SaIpuEnable;<br>-<br>-/** Offset 0x0052 - GT PM Support<br>- Enable/Disable GT power management support. 0:Disable, 1:Enable(Default).<br>- $EN_DIS<br>-**/<br>- UINT8 PmSupport;<br>-<br>-/** Offset 0x0053 - RC6(Render Standby)<br>- Enable/Disable render standby support. 0:Disable, 1:Enable(Default).<br>- $EN_DIS<br>-**/<br>- UINT8 EnableRenderStandby;<br>-<br>-/** Offset 0x0054 - BMP Logo Data Size<br>- BMP logo data buffer size. 0x00000000(Default).<br>-**/<br>- UINT32 LogoSize;<br>-<br>-/** Offset 0x0058 - BMP Logo Data Pointer<br>- BMP logo data pointer to a BMP format buffer. 0x00000000(Default).<br>-**/<br>- UINT32 LogoPtr;<br>-<br>-/** Offset 0x005C - Graphics Configuration Data Pointer<br>- Graphics configuration data used for initialization. 0x00000000(Default).<br>-**/<br>- UINT32 GraphicsConfigPtr;<br>-<br>-/** Offset 0x0060 - PAVP Enable<br>- Enable/Disable Protected Audio Visual Path (PAVP). 0:Disable, 1:Enable(Default).<br>- $EN_DIS<br>-**/<br>- UINT8 PavpEnable;<br>-<br>-/** Offset 0x0061 - PAVP PR3<br>- Enable/Disable PAVP PR3 0:Disable, 1:Enable(Default).<br>- $EN_DIS<br>-**/<br>- UINT8 PavpPr3;<br>-<br>-/** Offset 0x0062 - CdClock Frequency selection<br>- 0:144MHz, 1:288MHz, 2:384MHz, 3:576MHz, 4:624MHz(Default).<br>- 0: 144 MHz, 1: 288 MHz, 2: 384 MHz, 3: 576 MHz, 4: 624 MHz<br>-**/<br>- UINT8 CdClock;<br>-<br>-/** Offset 0x0063 - Enable/Disable PeiGraphicsPeimInit<br>- Enable/Disable PeiGraphicsPeimInit 0:Disable, 1:Enable(Default).<br>- $EN_DIS<br>-**/<br>- UINT8 PeiGraphicsPeimInit;<br>-<br>-/** Offset 0x0064 - Write Protection Support<br>- Enable/disable Write Protection. 0:Disable, 1:Enable(Default).<br>-**/<br>- UINT8 WriteProtectionEnable[5];<br>-<br>-/** Offset 0x0069 - Read Protection Support<br>- Enable/disable Read Protection. 0:Disable, 1:Enable(Default).<br>-**/<br>- UINT8 ReadProtectionEnable[5];<br>-<br>-/** Offset 0x006E - Protected Range Limitation<br>- The address of the upper limit of protection, 0x0FFFh(Default).<br>-**/<br>- UINT16 ProtectedRangeLimit[5];<br>-<br>-/** Offset 0x0078 - Protected Range Base<br>- The base address of the upper limit of protection. 0x0000(Default).<br>-**/<br>- UINT16 ProtectedRangeBase[5];<br>-<br>-/** Offset 0x0082 - Enable SC Gaussian Mixture Models<br>- Enable/disable SC Gaussian Mixture Models. 0:Disable, 1:Enable(Default).<br>- $EN_DIS<br>-**/<br>- UINT8 Gmm;<br>-<br>-/** Offset 0x0083 - GMM Clock Gating - PGCB Clock Trunk<br>- Enable/disable PGCB Clock Trunk. 0:Disable, 1:Enable(Default).<br>- $EN_DIS<br>-**/<br>- UINT8 ClkGatingPgcbClkTrunk;<br>-<br>-/** Offset 0x0084 - GMM Clock Gating - Sideband<br>- Enable/disable Sideband. 0:Disable, 1:Enable(Default).<br>- $EN_DIS<br>-**/<br>- UINT8 ClkGatingSb;<br>-<br>-/** Offset 0x0085 - GMM Clock Gating - Sideband<br>- Enable/disable Sideband. 0:Disable, 1:Enable(Default).<br>- $EN_DIS<br>-**/<br>- UINT8 ClkGatingSbClkTrunk;<br>-<br>-/** Offset 0x0086 - GMM Clock Gating - Sideband Clock Partition<br>- Enable/disable Sideband Clock Partition. 0:Disable, 1:Enable(Default).<br>- $EN_DIS<br>-**/<br>- UINT8 ClkGatingSbClkPartition;<br>-<br>-/** Offset 0x0087 - GMM Clock Gating - Core<br>- Enable/disable Core. 0:Disable, 1:Enable(Default).<br>- $EN_DIS<br>-**/<br>- UINT8 ClkGatingCore;<br>-<br>-/** Offset 0x0088 - GMM Clock Gating - DMA<br>- Enable/disable DMA. 0:Disable, 1:Enable(Default).<br>- $EN_DIS<br>-**/<br>- UINT8 ClkGatingDma;<br>-<br>-/** Offset 0x0089 - GMM Clock Gating - Register Access<br>- Enable/disable Register Access. 0:Disable, 1:Enable(Default).<br>- $EN_DIS<br>-**/<br>- UINT8 ClkGatingRegAccess;<br>-<br>-/** Offset 0x008A - GMM Clock Gating - Host<br>- Enable/disable Host. 0:Disable, 1:Enable(Default).<br>- $EN_DIS<br>-**/<br>- UINT8 ClkGatingHost;<br>-<br>-/** Offset 0x008B - GMM Clock Gating - Partition<br>- Enable/disable Partition. 0:Disable, 1:Enable(Default).<br>- $EN_DIS<br>-**/<br>- UINT8 ClkGatingPartition;<br>-<br>-/** Offset 0x008C - Clock Gating - Trunk<br>- Enable/disable Trunk. 0:Disable, 1:Enable(Default).<br>- $EN_DIS<br>-**/<br>- UINT8 ClkGatingTrunk;<br>-<br>-/** Offset 0x008D - HD Audio Support<br>- Enable/disable HDA Audio Feature. 0:Disable, 1:Enable(Default).<br>- $EN_DIS<br>-**/<br>- UINT8 HdaEnable;<br>-<br>-/** Offset 0x008E - HD Audio DSP Support<br>- Enable/disable HDA Audio DSP Feature. 0:Disable, 1:Enable(Default).<br>- $EN_DIS<br>-**/<br>- UINT8 DspEnable;<br>-<br>-/** Offset 0x008F - Azalia wake-on-ring<br>- Enable/disable Azalia wake-on-ring. 0:Disable(Default), 1:Enable.<br>- $EN_DIS<br>-**/<br>- UINT8 Pme;<br>-<br>-/** Offset 0x0090 - HD-Audio I/O Buffer Ownership<br>- Set HD-Audio I/O Buffer Ownership. 0:HD-Audio link owns all the I/O buffers(Default)<br>- 0:HD-Audio link owns all the I/O buffers, 1:HD-Audio link owns 4 I/O buffers and<br>- I2S port owns 4 I/O buffers, 3:I2S port owns all the I/O buffers<br>-**/<br>- UINT8 HdAudioIoBufferOwnership;<br>-<br>-/** Offset 0x0091 - HD-Audio I/O Buffer Voltage<br>- HD-Audio I/O Buffer Voltage Mode Selectiton . 0:3.3V(Default), 1:1.8V.<br>- 0: 3.3V, 1: 1.8V<br>-**/<br>- UINT8 HdAudioIoBufferVoltage;<br>-<br>-/** Offset 0x0092 - HD-Audio Virtual Channel Type<br>- HD-Audio Virtual Channel Type Selectiton. 0:VC0(Default), 1:VC1.<br>- 0: VC0, 1: VC1<br>-**/<br>- UINT8 HdAudioVcType;<br>-<br>-/** Offset 0x0093 - HD-Audio Link Frequency<br>- HD-Audio Virtual Channel Type Selectiton. 0:6MHz(Default), 1:12MHz, 2:24MHz, 3:48MHz,<br>- 4:96MHz, 5:Invalid.<br>- 0: 6MHz, 1: 12MHz, 2: 24MHz, 3: 48MHz, 4: 96MHz, 5: Invalid<br>-**/<br>- UINT8 HdAudioLinkFrequency;<br>-<br>-/** Offset 0x0094 - HD-Audio iDisp-Link Frequency<br>- HD-Audio iDisp-Link Frequency Selectiton. 0:6MHz(Default), 1:12MHz, 2:24MHz, 3:48MHz,<br>- 4:96MHz, 5:Invalid.<br>- 0: 6MHz, 1: 12MHz, 2: 24MHz, 3: 48MHz, 4: 96MHz, 5: Invalid<br>-**/<br>- UINT8 HdAudioIDispLinkFrequency;<br>-<br>-/** Offset 0x0095 - HD-Audio iDisp-Link T-Mode<br>- HD-Audio iDisp-Link T-Mode Selectiton. 0:2T(Default), 1:1T.<br>- 0: 2T, 1: 1T<br>-**/<br>- UINT8 HdAudioIDispLinkTmode;<br>-<br>-/** Offset 0x0096 - HD-Audio Disp DMIC<br>- HD-Audio Disp DMIC Selectiton. 0:Disable, 1:2ch array(Default), 2:4ch array.<br>- 0: Disable, 1: 2ch array, 2: 4ch array<br>-**/<br>- UINT8 DspEndpointDmic;<br>-<br>-/** Offset 0x0097 - HD-Audio Bluetooth<br>- Enable/Disable HD-Audio bluetooth. 0:Disable, 1:Enable(Default).<br>- $EN_DIS<br>-**/<br>- UINT8 DspEndpointBluetooth;<br>-<br>-/** Offset 0x0098 - HD-Audio I2S SHK<br>- Enable/Disable HD-Audio I2S SHK. 0:Disable(Default), 1:Enable.<br>- $EN_DIS<br>-**/<br>- UINT8 DspEndpointI2sSkp;<br>-<br>-/** Offset 0x0099 - HD-Audio I2S HP<br>- Enable/Disable HD-Audio I2S HP. 0:Disable(Default), 1:Enable.<br>- $EN_DIS<br>-**/<br>- UINT8 DspEndpointI2sHp;<br>-<br>-/** Offset 0x009A - HD-Audio Controller Power Gating<br>- Enable/Disable HD-Audio Controller Power Gating. This option is deprecated.<br>- $EN_DIS<br>-**/<br>- UINT8 AudioCtlPwrGate;<br>-<br>-/** Offset 0x009B - HD-Audio ADSP Power Gating<br>- Enable/Disable HD-Audio ADSP Power Gating. This option is deprecated.<br>- $EN_DIS<br>-**/<br>- UINT8 AudioDspPwrGate;<br>-<br>-/** Offset 0x009C - HD-Audio CSME Memory Transfers<br>- Enable/Disable HD-Audio CSME Memory Transfers. 0:VC0(Default), 1:VC2.<br>- 0: VC0, 1: VC2<br>-**/<br>- UINT8 Mmt;<br>-<br>-/** Offset 0x009D - HD-Audio Host Memory Transfers<br>- Enable/Disable HD-Audio Host Memory Transfers. 0:VC0(Default), 1:VC2.<br>- 0: VC0, 1: VC2<br>-**/<br>- UINT8 Hmt;<br>-<br>-/** Offset 0x009E - HD-Audio Power Gating<br>- Enable/Disable HD-Audio BIOS Configuration Lock Down. 0:Disable(Default), 1:Enable.<br>- $EN_DIS<br>-**/<br>- UINT8 HDAudioPwrGate;<br>-<br>-/** Offset 0x009F - HD-Audio Clock Gatingn<br>- Enable/Disable HD-Audio Clock Gating. 0:Disable(Default), 1:Enable.<br>- $EN_DIS<br>-**/<br>- UINT8 HDAudioClkGate;<br>-<br>-/** Offset 0x00A0 - Bitmask of DSP Feature<br>- Set Bitmask of HD-Audio DSP Feature. 0x00000000(Default).<br>- [BIT0] - WoV, [BIT1] - BT Sideband, [BIT2] - Codec VAD, [BIT5] - BT Intel HFP, [BIT6]<br>- - BT Intel A2DP, [BIT7] - DSP based speech pre-processing disabled, [BIT8] - 0:<br>- Intel WoV, 1: Windows Voice Activation<br>-**/<br>- UINT32 DspFeatureMask;<br>-<br>-/** Offset 0x00A4 - Bitmask of supported DSP Post-Processing Modules<br>- Set HD-Audio Bitmask of supported DSP Post-Processing Modules. 0x00000000(Default).<br>- [BIT0] - WoV, [BIT1] - BT Sideband, [BIT2] - Codec VAD, [BIT5] - BT Intel HFP, [BIT6]<br>- - BT Intel A2DP, [BIT7] - DSP based speech pre-processing disabled, [BIT8] - 0:<br>- Intel WoV, 1: Windows Voice Activation<br>-**/<br>- UINT32 DspPpModuleMask;<br>-<br>-/** Offset 0x00A8 - HD-Audio BIOS Configuration Lock Down<br>- Enable/Disable HD-Audio BIOS Configuration Lock Down. 0:Disable(Default), 1:Enable.<br>- This option is deprecated<br>- $EN_DIS<br>-**/<br>- UINT8 BiosCfgLockDown;<br>-<br>-/** Offset 0x00A9 - Enable High Precision Timer<br>- Enable/Disable Hpet. 0:Disable, 1:Enable(Default).<br>- $EN_DIS<br>-**/<br>- UINT8 Hpet;<br>-<br>-/** Offset 0x00AA - Hpet Valid BDF Value<br>- Enable/Disable Hpet Valid BDF Value. 0:Disable(Default), 1:Enable.<br>- $EN_DIS<br>-**/<br>- UINT8 HpetBdfValid;<br>-<br>-/** Offset 0x00AB - Bus Number of Hpet<br>- Completer ID of Bus Number of Hpet. Default = 0xFA(Default).<br>-**/<br>- UINT8 HpetBusNumber;<br>-<br>-/** Offset 0x00AC - Device Number of Hpet<br>- Completer ID of Device Number of Hpet. 0x1F(Default).<br>-**/<br>- UINT8 HpetDeviceNumber;<br>-<br>-/** Offset 0x00AD - Function Number of Hpet<br>- Completer ID of Function Number of Hpet. 0x00(Default).<br>-**/<br>- UINT8 HpetFunctionNumber;<br>-<br>-/** Offset 0x00AE - IoApic Valid BDF Value<br>- Enable/Disable IoApic Valid BDF Value. 0:Disable(Default), 1:Enable.<br>- $EN_DIS<br>-**/<br>- UINT8 IoApicBdfValid;<br>-<br>-/** Offset 0x00AF - Bus Number of IoApic<br>- Completer ID of Bus Number of IoApic. 0xFA(Default).<br>-**/<br>- UINT8 IoApicBusNumber;<br>-<br>-/** Offset 0x00B0 - Device Number of IoApic<br>- Completer ID of Device Number of IoApic. 0x0F(Default).<br>-**/<br>- UINT8 IoApicDeviceNumber;<br>-<br>-/** Offset 0x00B1 - Function Number of IoApic<br>- Completer ID of Function Number of IoApic. 0x00(Default).<br>-**/<br>- UINT8 IoApicFunctionNumber;<br>-<br>-/** Offset 0x00B2 - IOAPIC Entry 24-119<br>- Enable/Disable IOAPIC Entry 24-119. 0:Disable, 1:Enable(Default).<br>- $EN_DIS<br>-**/<br>- UINT8 IoApicEntry24_119;<br>-<br>-/** Offset 0x00B3 - IO APIC ID<br>- This member determines IOAPIC ID. 0x01(Default).<br>-**/<br>- UINT8 IoApicId;<br>-<br>-/** Offset 0x00B4 - IoApic Range<br>- Define address bits 19:12 for the IOxAPIC range. 0x00(Default).<br>-**/<br>- UINT8 IoApicRangeSelect;<br>-<br>-/** Offset 0x00B5 - ISH Controller<br>- Enable/Disable ISH Controller. 0:Disable, 1:Enable(Default).<br>- $EN_DIS<br>-**/<br>- UINT8 IshEnable;<br>-<br>-/** Offset 0x00B6 - BIOS Interface Lock Down<br>- Enable/Disable BIOS Interface Lock Down bit to prevent writes to the Backup Control<br>- Register. 0:Disable, 1:Enable(Default).<br>- $EN_DIS<br>-**/<br>- UINT8 BiosInterface;<br>-<br>-/** Offset 0x00B7 - Bios LockDown Enable<br>- Enable the BIOS Lock Enable (BLE) feature and set EISS bit. 0:Disable(Default), 1:Enable.<br>- $EN_DIS<br>-**/<br>- UINT8 BiosLock;<br>-<br>-/** Offset 0x00B8 - SPI EISS Status<br>- Enable/Disable InSMM.STS (EISS) in SPI. 0:Disable, 1:Enable(Default).<br>- $EN_DIS<br>-**/<br>- UINT8 SpiEiss;<br>-<br>-/** Offset 0x00B9 - BiosLock SWSMI Number<br>- This member describes the SwSmi value for Bios Lock. 0xA9(Default).<br>-**/<br>- UINT8 BiosLockSwSmiNumber;<br>-<br>-/** Offset 0x00BA - LPSS IOSF PMCTL S0ix Enable<br>- Enable/Disable LPSS IOSF Bridge PMCTL Register S0ix Bits. 0:Disable(Default), 1:Enable.<br>- $EN_DIS<br>-**/<br>- UINT8 LPSS_S0ixEnable;<br>-<br>-/** Offset 0x00BB<br>-**/<br>- UINT8 UnusedUpdSpace0[1];<br>-<br>-/** Offset 0x00BC - LPSS I2C Clock Gating Configuration<br>- Enable/Disable LPSS I2C Clock Gating. 0:Disable, 1:Enable(Default).<br>-**/<br>- UINT8 I2cClkGateCfg[8];<br>-<br>-/** Offset 0x00C4 - PSS HSUART Clock Gating Configuration<br>- Enable/Disable LPSS HSUART Clock Gating. 0:Disable, 1:Enable(Default).<br>-**/<br>- UINT8 HsuartClkGateCfg[4];<br>-<br>-/** Offset 0x00C8 - LPSS SPI Clock Gating Configuration<br>- Enable/Disable LPSS SPI Clock Gating. 0:Disable, 1:Enable(Default).<br>-**/<br>- UINT8 SpiClkGateCfg[3];<br>-<br>-/** Offset 0x00CB - I2C Device 0<br>- Enable/Disable I2C Device 0. 0:Disabled, 1:PCI Mode(Default), 2:ACPI Mode.<br>- 0: Disabled, 1: PCI Mode, 2: ACPI Mode<br>-**/<br>- UINT8 I2c0Enable;<br>-<br>-/** Offset 0x00CC - I2C Device 1<br>- Enable/Disable I2C Device 1. 0:Disabled, 1:PCI Mode(Default), 2:ACPI Mode.<br>- 0: Disabled, 1: PCI Mode, 2: ACPI Mode<br>-**/<br>- UINT8 I2c1Enable;<br>-<br>-/** Offset 0x00CD - I2C Device 2<br>- Enable/Disable I2C Device 2. 0:Disabled, 1:PCI Mode(Default), 2:ACPI Mode.<br>- 0: Disabled, 1: PCI Mode, 2: ACPI Mode<br>-**/<br>- UINT8 I2c2Enable;<br>-<br>-/** Offset 0x00CE - I2C Device 3<br>- Enable/Disable I2C Device 3. 0:Disabled, 1:PCI Mode(Default), 2:ACPI Mode.<br>- 0: Disabled, 1: PCI Mode, 2: ACPI Mode<br>-**/<br>- UINT8 I2c3Enable;<br>-<br>-/** Offset 0x00CF - I2C Device 4<br>- Enable/Disable I2C Device 4. 0:Disabled, 1:PCI Mode(Default), 2:ACPI Mode.<br>- 0: Disabled, 1: PCI Mode, 2: ACPI Mode<br>-**/<br>- UINT8 I2c4Enable;<br>-<br>-/** Offset 0x00D0 - I2C Device 5<br>- Enable/Disable I2C Device 5. 0:Disabled, 1:PCI Mode(Default), 2:ACPI Mode.<br>- 0: Disabled, 1: PCI Mode, 2: ACPI Mode<br>-**/<br>- UINT8 I2c5Enable;<br>-<br>-/** Offset 0x00D1 - I2C Device 6<br>- Enable/Disable I2C Device 6. 0:Disabled, 1:PCI Mode(Default), 2:ACPI Mode.<br>- 0: Disabled, 1: PCI Mode, 2: ACPI Mode<br>-**/<br>- UINT8 I2c6Enable;<br>-<br>-/** Offset 0x00D2 - I2C Device 7<br>- Enable/Disable I2C Device 7. 0:Disabled, 1:PCI Mode(Default), 2:ACPI Mode.<br>- 0: Disabled, 1: PCI Mode, 2: ACPI Mode<br>-**/<br>- UINT8 I2c7Enable;<br>-<br>-/** Offset 0x00D3 - UART Device 0<br>- Enable/Disable UART Device 0. 0:Disabled, 1:PCI Mode(Default), 2:ACPI Mode.<br>- 0: Disabled, 1: PCI Mode, 2: ACPI Mode<br>-**/<br>- UINT8 Hsuart0Enable;<br>-<br>-/** Offset 0x00D4 - UART Device 1<br>- Enable/Disable UART Device 1. 0:Disabled, 1:PCI Mode(Default), 2:ACPI Mode.<br>- 0: Disabled, 1: PCI Mode, 2: ACPI Mode<br>-**/<br>- UINT8 Hsuart1Enable;<br>-<br>-/** Offset 0x00D5 - UART Device 2<br>- Enable/Disable UART Device 2. 0:Disabled, 1:PCI Mode(Default), 2:ACPI Mode.<br>- 0: Disabled, 1: PCI Mode, 2: ACPI Mode<br>-**/<br>- UINT8 Hsuart2Enable;<br>-<br>-/** Offset 0x00D6 - UART Device 3<br>- Enable/Disable UART Device 3. 0:Disabled, 1:PCI Mode(Default), 2:ACPI Mode.<br>- 0: Disabled, 1: PCI Mode, 2: ACPI Mode<br>-**/<br>- UINT8 Hsuart3Enable;<br>-<br>-/** Offset 0x00D7 - SPI UART Device 0<br>- Enable/Disable SPI Device 0. 0:Disabled, 1:PCI Mode(Default), 2:ACPI Mode.<br>- 0: Disabled, 1: PCI Mode, 2: ACPI Mode<br>-**/<br>- UINT8 Spi0Enable;<br>-<br>-/** Offset 0x00D8 - SPI UART Device 1<br>- Enable/Disable SPI Device 1. 0:Disabled, 1:PCI Mode(Default), 2:ACPI Mode.<br>- 0: Disabled, 1: PCI Mode, 2: ACPI Mode<br>-**/<br>- UINT8 Spi1Enable;<br>-<br>-/** Offset 0x00D9 - SPI UART Device 2<br>- Enable/Disable SPI Device 2. 0:Disabled, 1:PCI Mode(Default), 2:ACPI Mode.<br>- 0: Disabled, 1: PCI Mode, 2: ACPI Mode<br>-**/<br>- UINT8 Spi2Enable;<br>-<br>-/** Offset 0x00DA - OS Debug Feature<br>- Enable/Disable OS Debug Feature. 0:Disable(Default), 1: Enable.<br>- $EN_DIS<br>-**/<br>- UINT8 OsDbgEnable;<br>-<br>-/** Offset 0x00DB - DCI Feature<br>- Enable/Disable DCI Feature. 0:Disable(Default), 1: Enable.<br>- $EN_DIS<br>-**/<br>- UINT8 DciEn;<br>-<br>-/** Offset 0x00DC - UART Debug Base Address<br>- UART Debug Base Address. 0x00000000(Default).<br>-**/<br>- UINT32 Uart2KernelDebugBaseAddress;<br>-<br>-/** Offset 0x00E0 - Enable PCIE Clock Gating<br>- Enable/disable PCIE Clock Gating. 0:Enable, 1:Disable(Default).<br>- 0:Enable, 1:Disable<br>-**/<br>- UINT8 PcieClockGatingDisabled;<br>-<br>-/** Offset 0x00E1 - Enable PCIE Root Port 8xh Decode<br>- Enable/disable PCIE Root Port 8xh Decode. 0:Disable, 1:Enable(Default).<br>- $EN_DIS<br>-**/<br>- UINT8 PcieRootPort8xhDecode;<br>-<br>-/** Offset 0x00E2 - PCIE 8xh Decode Port Index<br>- PCIE 8xh Decode Port Index. 0x00(Default).<br>-**/<br>- UINT8 Pcie8xhDecodePortIndex;<br>-<br>-/** Offset 0x00E3 - Enable PCIE Root Port Peer Memory Write<br>- Enable/disable PCIE root port peer memory write. 0:Disable(Default), 1:Enable.<br>- $EN_DIS<br>-**/<br>- UINT8 PcieRootPortPeerMemoryWriteEnable;<br>-<br>-/** Offset 0x00E4 - PCIE SWSMI Number<br>- This member describes the SwSmi value for override PCIe ASPM table. 0xAA(Default).<br>-**/<br>- UINT8 PcieAspmSwSmiNumber;<br>-<br>-/** Offset 0x00E5<br>-**/<br>- UINT8 UnusedUpdSpace1[1];<br>-<br>-/** Offset 0x00E6 - PCI Express Root Port<br>- Control the PCI Express Root Port . 0:Disable, 1:Enable(Default).<br>-**/<br>- UINT8 PcieRootPortEn[6];<br>-<br>-/** Offset 0x00EC - Hide PCIE Root Port Configuration Space<br>- Enable/disable Hide PCIE Root Port Configuration Space. 0:Disable(Default), 1:Enable.<br>-**/<br>- UINT8 PcieRpHide[6];<br>-<br>-/** Offset 0x00F2 - PCIE Root Port Slot Implement<br>- Enable/disable PCIE Root Port Slot Implement. 0:Disable, 1:Enable(Default).<br>-**/<br>- UINT8 PcieRpSlotImplemented[6];<br>-<br>-/** Offset 0x00F8 - Hot Plug<br>- PCI Express Hot Plug Enable/Disable. 0:Disable, 1:Enable(Default).<br>-**/<br>- UINT8 PcieRpHotPlug[6];<br>-<br>-/** Offset 0x00FE - PCIE PM SCI<br>- Enable/Disable PCI Express PME SCI. 0:Disable(Default), 1:Enable.<br>-**/<br>- UINT8 PcieRpPmSci[6];<br>-<br>-/** Offset 0x0104 - PCIE Root Port Extended Sync<br>- Enable/Disable PCIE Root Port Extended Sync. 0:Disable, 1:Enable(Default).<br>-**/<br>- UINT8 PcieRpExtSync[6];<br>-<br>-/** Offset 0x010A - Transmitter Half Swing<br>- Transmitter Half Swing Enable/Disable. 0:Disable, 1:Enable(Default).<br>-**/<br>- UINT8 PcieRpTransmitterHalfSwing[6];<br>-<br>-/** Offset 0x0110 - ACS<br>- Enable/Disable Access Control Services Extended Capability. 0:Disable, 1:Enable(Default).<br>-**/<br>- UINT8 PcieRpAcsEnabled[6];<br>-<br>-/** Offset 0x0116 - Clock Request Support<br>- Enable/Disable CLKREQ# Support. 0:Disable, 1:Enable(Default).<br>-**/<br>- UINT8 PcieRpClkReqSupported[6];<br>-<br>-/** Offset 0x011C - Configure CLKREQ Number<br>- Configure Root Port CLKREQ Number if CLKREQ is supported. Default=0x04, 0x05, 0x00,<br>- 0x01, 0x02, 0x03.<br>-**/<br>- UINT8 PcieRpClkReqNumber[6];<br>-<br>-/** Offset 0x0122 - CLKREQ# Detection<br>- Enable/Disable CLKREQ# Detection Probe. 0: Disable(Default), 1: Enable.<br>-**/<br>- UINT8 PcieRpClkReqDetect[6];<br>-<br>-/** Offset 0x0128 - Advanced Error Reporting<br>- Enable/Disable Advanced Error Reporting. 0: Disable(Default), 1: Enable.<br>-**/<br>- UINT8 AdvancedErrorReporting[6];<br>-<br>-/** Offset 0x012E - PME Interrupt<br>- Enable/Disable PME Interrupt. 0: Disable(Default), 1: Enable.<br>-**/<br>- UINT8 PmeInterrupt[6];<br>-<br>-/** Offset 0x0134 - URR<br>- PCI Express Unsupported Request Reporting Enable/Disable. 0:Disable(Default), 1:Enable.<br>-**/<br>- UINT8 UnsupportedRequestReport[6];<br>-<br>-/** Offset 0x013A - FER<br>- PCI Express Device Fatal Error Reporting Enable/Disable. 0:Disable(Default), 1:Enable.<br>-**/<br>- UINT8 FatalErrorReport[6];<br>-<br>-/** Offset 0x0140 - NFER<br>- PCI Express Device Non-Fatal Error Reporting Enable/Disable. 0:Disable(Default), 1:Enable.<br>-**/<br>- UINT8 NoFatalErrorReport[6];<br>-<br>-/** Offset 0x0146 - CER<br>- PCI Express Device Correctable Error Reporting Enable/Disable. 0:Disable(Default), 1:Enable.<br>-**/<br>- UINT8 CorrectableErrorReport[6];<br>-<br>-/** Offset 0x014C - SEFE<br>- Root PCI Express System Error on Fatal Error Enable/Disable. 0:Disable(Default), 1:Enable.<br>-**/<br>- UINT8 SystemErrorOnFatalError[6];<br>-<br>-/** Offset 0x0152 - SENFE<br>- Root PCI Express System Error on Non-Fatal Error Enable/Disable. 0:Disable(Default), 1:Enable.<br>-**/<br>- UINT8 SystemErrorOnNonFatalError[6];<br>-<br>-/** Offset 0x0158 - SECE<br>- Root PCI Express System Error on Correctable Error Enable/Disable. 0:Disable(Default), 1:Enable.<br>-**/<br>- UINT8 SystemErrorOnCorrectableError[6];<br>-<br>-/** Offset 0x015E - PCIe Speed<br>- Configure PCIe Speed. 0:Auto(Default), 1:Gen1, 2:Gen2, 3:Gen3.<br>-**/<br>- UINT8 PcieRpSpeed[6];<br>-<br>-/** Offset 0x0164 - Physical Slot Number<br>- Physical Slot Number for PCIE Root Port. Default=0x00, 0x01, 0x02, 0x03, 0x04, 0x05.<br>-**/<br>- UINT8 PhysicalSlotNumber[6];<br>-<br>-/** Offset 0x016A - CTO<br>- Enable/Disable PCI Express Completion Timer TO . 0:Disable(Default), 1:Enable.<br>-**/<br>- UINT8 PcieRpCompletionTimeout[6];<br>-<br>-/** Offset 0x0170 - PTM Support<br>- Enable/Disable PTM Support. 0:Disable(Default), 1:Enable.<br>-**/<br>- UINT8 PtmEnable[6];<br>-<br>-/** Offset 0x0176 - ASPM<br>- PCI Express Active State Power Management settings. 0:Disable, 1:L0s, 2:L1, 3:L0sL1,<br>- 4:Auto(Default).<br>-**/<br>- UINT8 PcieRpAspm[6];<br>-<br>-/** Offset 0x017C - L1 Substates<br>- PCI Express L1 Substates settings. 0:Disable, 1:L1.1, 2:L1.2, 3:L1.1 & L1.2(Default).<br>-**/<br>- UINT8 PcieRpL1Substates[6];<br>-<br>-/** Offset 0x0182 - PCH PCIe LTR<br>- PCH PCIE Latency Reporting Enable/Disable. 0:Disable, 1:Enable(Default).<br>-**/<br>- UINT8 PcieRpLtrEnable[6];<br>-<br>-/** Offset 0x0188 - PCIE LTR Lock<br>- PCIE LTR Configuration Lock. 0:Disable(Default), 1:Enable.<br>-**/<br>- UINT8 PcieRpLtrConfigLock[6];<br>-<br>-/** Offset 0x018E - PME_B0_S5 Disable bit<br>- PME_B0_S5_DIS bit in the General PM Configuration B (GEN_PMCON_B) register. 0:Disable(Default), 1:Enable.<br>- $EN_DIS<br>-**/<br>- UINT8 PmeB0S5Dis;<br>-<br>-/** Offset 0x018F - PCI Clock Run<br>- This member describes whether or not the PCI ClockRun feature of SC should be enabled.<br>- 0:Disable(Default), 1:Enable.<br>- $EN_DIS<br>-**/<br>- UINT8 PciClockRun;<br>-<br>-/** Offset 0x0190 - Enable/Disable Timer 8254 Clock Setting<br>- Enable/Disable Timer 8254 Clock. 0:Disable(Default), 1:Enable.<br>- $EN_DIS<br>-**/<br>- UINT8 Timer8254ClkSetting;<br>-<br>-/** Offset 0x0191 - Chipset SATA<br>- Enables or Disables the Chipset SATA Controller. The Chipset SATA controller supports<br>- the 2 black internal SATA ports (up to 3Gb/s supported per port). 0:Disable, 1:Enable(Default).<br>- $EN_DIS<br>-**/<br>- UINT8 EnableSata;<br>-<br>-/** Offset 0x0192 - SATA Mode Selection<br>- Determines how SATA controller(s) operate. 0:AHCI(Default), 1:RAID.<br>- 0:AHCI, 1:RAID<br>-**/<br>- UINT8 SataMode;<br>-<br>-/** Offset 0x0193 - Aggressive LPM Support<br>- Enable PCH to aggressively enter link power state. 0:Disable, 1:Enable(Default).<br>- $EN_DIS<br>-**/<br>- UINT8 SataSalpSupport;<br>-<br>-/** Offset 0x0194 - SATA Power Optimization<br>- Enable SATA Power Optimizer on SC side. 0:Disable(Default), 1:Enable.<br>- $EN_DIS<br>-**/<br>- UINT8 SataPwrOptEnable;<br>-<br>-/** Offset 0x0195 - eSATA Speed Limit<br>- Enable/Disable eSATA Speed Limit. 0:Disable(Default), 1:Enable.<br>- $EN_DIS<br>-**/<br>- UINT8 eSATASpeedLimit;<br>-<br>-/** Offset 0x0196 - SATA Speed Limit<br>- SATA Speed Limit. 0h:ScSataSpeed(Default), 1h:1.5Gb/s(Gen 1), 2h:3Gb/s(Gen 2), 3h:6Gb/s(Gen 3).<br>- 0:Default, 1: 1.5 Gb/s (Gen 1), 2: 3 Gb/s(Gen 2), 3: 6 Gb/s (Gen 1)<br>-**/<br>- UINT8 SpeedLimit;<br>-<br>-/** Offset 0x0197<br>-**/<br>- UINT8 UnusedUpdSpace2[1];<br>-<br>-/** Offset 0x0198 - SATA Port<br>- Enable or Disable SATA Port. 0:Disable, 1:Enable(Default).<br>-**/<br>- UINT8 SataPortsEnable[2];<br>-<br>-/** Offset 0x019A - SATA Port DevSlp<br>- Enable/Disable SATA Port DevSlp. Board rework for LP needed before enable. 0:Disable(Default), 1:Enable.<br>-**/<br>- UINT8 SataPortsDevSlp[2];<br>-<br>-/** Offset 0x019C - SATA Port HotPlug<br>- Enable/Disable SATA Port Hotplug . 0:Disable(Default), 1:Enable.<br>-**/<br>- UINT8 SataPortsHotPlug[2];<br>-<br>-/** Offset 0x019E - Mechanical Presence Switch<br>- Controls reporting if this port has an Mechanical Presence Switch.\n<br>- Note:Requires hardware support. 0:Disable, 1:Enable(Default).<br>-**/<br>- UINT8 SataPortsInterlockSw[2];<br>-<br>-/** Offset 0x01A0 - External SATA Ports<br>- Enable/Disable External SATA Ports. 0:Disable(Default), 1:Enable.<br>-**/<br>- UINT8 SataPortsExternal[2];<br>-<br>-/** Offset 0x01A2 - Spin Up Device<br>- Enable/Disable device spin up at boot on selected Sata Ports. 0:Disable(Default), 1:Enable.<br>-**/<br>- UINT8 SataPortsSpinUp[2];<br>-<br>-/** Offset 0x01A4 - SATA Solid State<br>- Identify the SATA port is connected to Solid State Drive or Hard Disk Drive. 0:Hard<br>- Disk Drive(Default), 1:Solid State Drive.<br>-**/<br>- UINT8 SataPortsSolidStateDrive[2];<br>-<br>-/** Offset 0x01A6 - DITO Configuration<br>- Enable/Disable DITO Configuration. 0:Disable(Default), 1:Enable.<br>-**/<br>- UINT8 SataPortsEnableDitoConfig[2];<br>-<br>-/** Offset 0x01A8 - DM Value<br>- DM Value. 0:Minimum, 0x0F:Maximum(Default).<br>-**/<br>- UINT8 SataPortsDmVal[2];<br>-<br>-/** Offset 0x01AA<br>-**/<br>- UINT8 UnusedUpdSpace3[2];<br>-<br>-/** Offset 0x01AC - DITO Value<br>- DEVSLP Idle Timeout Value. 0:Minimum, 0x03FF:Maximum, 0x0271(Default).<br>-**/<br>- UINT16 SataPortsDitoVal[2];<br>-<br>-/** Offset 0x01B0 - Subsystem Vendor ID<br>- Subsystem Vendor ID. 0x8086(Default).<br>-**/<br>- UINT16 SubSystemVendorId;<br>-<br>-/** Offset 0x01B2 - Subsystem ID<br>- Subsystem ID. 0x7270(Default).<br>-**/<br>- UINT16 SubSystemId;<br>-<br>-/** Offset 0x01B4 - CRIDSettings<br>- PMC CRID setting. 0:Disable(Default), 1:CRID_1, 2:CRID_2, 3:CRID_3.<br>-**/<br>- UINT8 CRIDSettings;<br>-<br>-/** Offset 0x01B5 - ResetSelect<br>- ResetSelect. 0x6:warm reset(Default), 0xE:cold reset.<br>-**/<br>- UINT8 ResetSelect;<br>-<br>-/** Offset 0x01B6 - SD Card Support (D27:F0)<br>- Enable/Disable SD Card Support. 0:Disable, 1:Enable(Default).<br>- $EN_DIS<br>-**/<br>- UINT8 SdcardEnabled;<br>-<br>-/** Offset 0x01B7 - SeMMC Support (D28:F0)<br>- Enable/Disable eMMC Support. 0:Disable, 1:Enable(Default).<br>- $EN_DIS<br>-**/<br>- UINT8 eMMCEnabled;<br>-<br>-/** Offset 0x01B8 - eMMC Max Speed<br>- Select the eMMC max Speed allowed. 0:HS400(Default), 1:HS200, 2:DDR50.<br>- 0:HS400, 1: HS200, 2:DDR50<br>-**/<br>- UINT8 eMMCHostMaxSpeed;<br>-<br>-/** Offset 0x01B9 - UFS Support (D29:F0)<br>- Enable/Disable SDIO Support. 0:Disable, 1:Enable(Default).<br>- $EN_DIS<br>-**/<br>- UINT8 UfsEnabled;<br>-<br>-/** Offset 0x01BA - SDIO Support (D30:F0)<br>- Enable/Disable SDIO Support. 0:Disable, 1:Enable(Default).<br>- $EN_DIS<br>-**/<br>- UINT8 SdioEnabled;<br>-<br>-/** Offset 0x01BB - GPP Lock Feature<br>- Enable/Disable GPP lock. 0:Disable(Default), 1:Enable.<br>- $EN_DIS<br>-**/<br>- UINT8 GppLock;<br>-<br>-/** Offset 0x01BC - Serial IRQ<br>- Enable/Disable Serial IRQ. 0:Disable, 1:Enable(Default).<br>- $EN_DIS<br>-**/<br>- UINT8 SirqEnable;<br>-<br>-/** Offset 0x01BD - Serial IRQ Mode<br>- Serial IRQ Mode Selection. 0:Quiet mode(Default), 1:Continuous mode.<br>- $EN_DIS<br>-**/<br>- UINT8 SirqMode;<br>-<br>-/** Offset 0x01BE - Start Frame Pulse Width<br>- Start Frame Pulse Width Value. 0:ScSfpw4Clk(Default), 1: ScSfpw6Clk, 2:ScSfpw8Clk.<br>- 0:ScSfpw4Clk, 1:ScSfpw6Clk, 2:ScSfpw8Clk<br>-**/<br>- UINT8 StartFramePulse;<br>-<br>-/** Offset 0x01BF - Enable SMBus<br>- Enable/disable SMBus controller. 0:Disable, 1:Enable(Default).<br>- $EN_DIS<br>-**/<br>- UINT8 SmbusEnable;<br>-<br>-/** Offset 0x01C0 - SMBus ARP Support<br>- Enable/disable SMBus ARP Support. 0:Disable, 1:Enable(Default).<br>- $EN_DIS<br>-**/<br>- UINT8 ArpEnable;<br>-<br>-/** Offset 0x01C1<br>-**/<br>- UINT8 UnusedUpdSpace4;<br>-<br>-/** Offset 0x01C2 - SMBus Table Elements<br>- The number of elements in the Reserved SMBus Address Table. 0x0080(Default).<br>-**/<br>- UINT16 NumRsvdSmbusAddresses;<br>-<br>-/** Offset 0x01C4 - Reserved SMBus Address Table<br>- Array of addresses reserved for non-ARP-capable SMBus devices. 0x00(Default).<br>-**/<br>- UINT8 RsvdSmbusAddressTable[128];<br>-<br>-/** Offset 0x0244 - XHCI Disable Compliance Mode<br>- Options to disable XHCI Link Compliance Mode. Default is FALSE to not disable Compliance<br>- Mode. Set TRUE to disable Compliance Mode. 0:FALSE(Default), 1:True.<br>- $EN_DIS<br>-**/<br>- UINT8 DisableComplianceMode;<br>-<br>-/** Offset 0x0245 - USB Per-Port Control<br>- Control each of the USB ports enable/disable. 0:Disable(Default), 1:Enable.<br>- $EN_DIS<br>-**/<br>- UINT8 UsbPerPortCtl;<br>-<br>-/** Offset 0x0246 - xHCI Mode<br>- Mode of operation of xHCI controller. 0:Disable, 1:Enable, 2:Auto(Default)<br>- 0:Disable, 1:Enable, 2:Auto<br>-**/<br>- UINT8 Usb30Mode;<br>-<br>-/** Offset 0x0247<br>-**/<br>- UINT8 UnusedUpdSpace5[1];<br>-<br>-/** Offset 0x0248 - Enable USB2 ports<br>- Enable/disable per USB2 ports. One byte for each port, byte0 for port0, byte1 for<br>- port1, and so on. 0x01(Default).<br>-**/<br>- UINT8 PortUsb20Enable[8];<br>-<br>-/** Offset 0x0250 - USB20 Over Current Pin<br>- Over Current Pin number of USB 2.0 Port. 0x00(Default).<br>-**/<br>- UINT8 PortUs20bOverCurrentPin[8];<br>-<br>-/** Offset 0x0258 - XDCI Support<br>- Enable/Disable XDCI. 0:Disable, 1:PCI_Mode(Default), 2:ACPI_mode.<br>- 0:Disable, 1:PCI_Mode, 2:ACPI_mode<br>-**/<br>- UINT8 UsbOtg;<br>-<br>-/** Offset 0x0259 - Enable XHCI HSIC Support<br>- Enable/Disable USB HSIC1. 0:Disable(Default), 1:Enable.<br>- $EN_DIS<br>-**/<br>- UINT8 HsicSupportEnable;<br>-<br>-/** Offset 0x025A - Enable USB3 ports<br>- Enable/disable per USB3 ports. One byte for each port, byte0 for port0, byte1 for<br>- port1, and so on. 0x01(Default).<br>-**/<br>- UINT8 PortUsb30Enable[6];<br>-<br>-/** Offset 0x0260 - USB20 Over Current Pin<br>- Over Current Pin number of USB 3.0 Port. 0x01(Default).<br>-**/<br>- UINT8 PortUs30bOverCurrentPin[6];<br>-<br>-/** Offset 0x0266 - Enable XHCI SSIC Support<br>- Enable/disable XHCI SSIC ports. One byte for each port, byte0 for port0, byte1 for<br>- port1. 0x00(Default).<br>-**/<br>- UINT8 SsicPortEnable[2];<br>-<br>-/** Offset 0x0268 - SSIC Dlane PowerGating<br>- Enable/Disable SSIC Data lane Power Gating. 0:Disable, 1:Enable(Default).<br>- $EN_DIS<br>-**/<br>- UINT16 DlanePwrGating;<br>-<br>-/** Offset 0x026A - VT-d<br>- Enable/Disable VT-d. 0:Disable(Default), 1:Enable.<br>- $EN_DIS<br>-**/<br>- UINT8 VtdEnable;<br>-<br>-/** Offset 0x026B - SMI Lock bit<br>- Enable/Disable SMI_LOCK bit to prevent writes to the Global SMI Enable bit. 0:Disable,<br>- 1:Enable(Default).<br>- $EN_DIS<br>-**/<br>- UINT8 LockDownGlobalSmi;<br>-<br>-/** Offset 0x026C - HDAudio Delay Timer<br>- The delay timer after Azalia reset. 0x012C(Default).<br>-**/<br>- UINT16 ResetWaitTimer;<br>-<br>-/** Offset 0x026E - RTC Lock Bits<br>- Enable/Disable RTC Lock Bits. 0:Disable, 1:Enable(Default).<br>- $EN_DIS<br>-**/<br>- UINT8 RtcLock;<br>-<br>-/** Offset 0x026F - SATA Test Mode Selection<br>- Enable/Disable SATA Test Mode. 0:Disable(Default), 1:Enable.<br>- $EN_DIS<br>-**/<br>- UINT8 SataTestMode;<br>-<br>-/** Offset 0x0270 - XHCI SSIC RATE<br>- Set XHCI SSIC1 Rate to A Series or B Series. 1:A Series(Default), 2:B Series.<br>-**/<br>- UINT8 SsicRate[2];<br>-<br>-/** Offset 0x0272 - SMBus Dynamic Power Gating<br>- Enable/Disable SMBus dynamic power gating. 0:Disable(Default), 1:Enable.<br>- $EN_DIS<br>-**/<br>- UINT16 DynamicPowerGating;<br>-<br>-/** Offset 0x0274 - Max Snoop Latency<br>- Latency Tolerance Reporting Max Snoop Latency. 0x0000(Default).<br>-**/<br>- UINT16 PcieRpLtrMaxSnoopLatency[6];<br>-<br>-/** Offset 0x0280 - Snoop Latency Override<br>- Snoop Latency Override for PCH PCIE. \n<br>- Disabled:Disable override.\n<br>- Manual:Manually enter override values.\n<br>- Auto:Maintain default BIOS flow. 0:Disable, 1:Enable, 2:Auto(Default).<br>-**/<br>- UINT8 PcieRpSnoopLatencyOverrideMode[6];<br>-<br>-/** Offset 0x0286<br>-**/<br>- UINT8 UnusedUpdSpace6[2];<br>-<br>-/** Offset 0x0288 - Snoop Latency Value<br>- LTR Snoop Latency value of PCH PCIE. 0:Minimum, 0x03FF:Maximum, 0x003C(Default).<br>-**/<br>- UINT16 PcieRpSnoopLatencyOverrideValue[6];<br>-<br>-/** Offset 0x0294 - Snoop Latency Multiplier<br>- LTR Snoop Latency Multiplier of PCH PCIE. 0:1ns, 1:32ns, 2:1024ns(Default), 3:32768ns,<br>- 4:1048576ns, 5:33554432ns.<br>-**/<br>- UINT8 PcieRpSnoopLatencyOverrideMultiplier[6];<br>-<br>-/** Offset 0x029A - Skip Multi-Processor Initialization<br>- When this is skipped, boot loader must initialize processors before SilicionInit<br>- API. 0: Initialize(Default), <b>1: Skip<br>- $EN_DIS<br>-**/<br>- UINT8 SkipMpInit;<br>-<br>-/** Offset 0x029B - DCI Auto Detect<br>- Enable/disable DCI AUTO mode. Enabled(Default).<br>- $EN_DIS<br>-**/<br>- UINT8 DciAutoDetect;<br>-<br>-/** Offset 0x029C - Max Non-Snoop Latency<br>- Latency Tolerance Reporting, Max Non-Snoop Latency. 0x0000(Default).<br>-**/<br>- UINT16 PcieRpLtrMaxNonSnoopLatency[6];<br>-<br>-/** Offset 0x02A8 - Non Snoop Latency Override<br>- Non Snoop Latency Override for PCH PCIE. \n<br>- Disabled:Disable override.\n<br>- Manual:Manually enter override values.\n<br>- Auto: Maintain default BIOS flow. 0:Disable, 1:Enable, 2:Auto(Default).<br>-**/<br>- UINT8 PcieRpNonSnoopLatencyOverrideMode[6];<br>-<br>-/** Offset 0x02AE - Halt and Lock TCO Timer<br>- Halt and Lock the TCO Timer (Watchdog).<br>- 0:No, 1:Yes (default)<br>-**/<br>- UINT8 TcoTimerHaltLock;<br>-<br>-/** Offset 0x02AF - Power Button Override Period<br>- specifies how long will PMC wait before initiating a global reset. 000b-4s(default),<br>- 001b-6s, 010b-8s, 011b-10s, 100b-12s, 101b-14s.)<br>- 0x0:4s, 0x1:6s, 0x2:8s, 0x3:10s, 0x4:12s, 0x5:14s<br>-**/<br>- UINT8 PwrBtnOverridePeriod;<br>-<br>-/** Offset 0x02B0 - Non Snoop Latency Value<br>- LTR Non Snoop Latency value of PCH PCIE. 0:Minimum, 0x03FF:Maximum, 0x003C(Default).<br>-**/<br>- UINT16 PcieRpNonSnoopLatencyOverrideValue[6];<br>-<br>-/** Offset 0x02BC - Non Snoop Latency Multiplier<br>- LTR Non Snoop Latency Multiplier of PCH PCIE. 0:1ns, 1:32ns, 2:1024ns(Default),<br>- 3:32768ns, 4:1048576ns, 5:33554432ns.<br>-**/<br>- UINT8 PcieRpNonSnoopLatencyOverrideMultiplier[6];<br>-<br>-/** Offset 0x02C2 - PCIE Root Port Slot Power Limit Scale<br>- Specifies scale used for slot power limit value. 0x00(Default).<br>-**/<br>- UINT8 PcieRpSlotPowerLimitScale[6];<br>-<br>-/** Offset 0x02C8 - PCIE Root Port Slot Power Limit Value<br>- Specifies upper limit on power supplie by slot. 0x00(Default).<br>-**/<br>- UINT8 PcieRpSlotPowerLimitValue[6];<br>-<br>-/** Offset 0x02CE - Power Button Native Mode Disable<br>- Disable power button native mode, when 1, this will result in the PMC logic constantly<br>- seeing the power button as de-asserted. 0 (default))<br>- $EN_DIS<br>-**/<br>- UINT8 DisableNativePowerButton;<br>-<br>-/** Offset 0x02CF - Power Button Debounce Mode<br>- Enable interrupt when PWRBTN# is asserted. 0:Disabled, 1:Enabled(default)<br>- $EN_DIS<br>-**/<br>- UINT8 PowerButterDebounceMode;<br>-<br>-/** Offset 0x02D0 - SDIO_TX_CMD_DLL_CNTL<br>- SDIO_TX_CMD_DLL_CNTL. 0x505(Default).<br>-**/<br>- UINT32 SdioTxCmdCntl;<br>-<br>-/** Offset 0x02D4 - SDIO_TX_DATA_DLL_CNTL1<br>- SDIO_TX_DATA_DLL_CNTL1. 0xE(Default).<br>-**/<br>- UINT32 SdioTxDataCntl1;<br>-<br>-/** Offset 0x02D8 - SDIO_TX_DATA_DLL_CNTL2<br>- SDIO_TX_DATA_DLL_CNTL2. 0x22272828(Default).<br>-**/<br>- UINT32 SdioTxDataCntl2;<br>-<br>-/** Offset 0x02DC - SDIO_RX_CMD_DATA_DLL_CNTL1<br>- SDIO_RX_CMD_DATA_DLL_CNTL1. 0x16161616(Default).<br>-**/<br>- UINT32 SdioRxCmdDataCntl1;<br>-<br>-/** Offset 0x02E0 - SDIO_RX_CMD_DATA_DLL_CNTL2<br>- SDIO_RX_CMD_DATA_DLL_CNTL2. 0x10000(Default).<br>-**/<br>- UINT32 SdioRxCmdDataCntl2;<br>-<br>-/** Offset 0x02E4 - SDCARD_TX_CMD_DLL_CNTL<br>- SDCARD_TX_CMD_DLL_CNTL. 0x505(Default).<br>-**/<br>- UINT32 SdcardTxCmdCntl;<br>-<br>-/** Offset 0x02E8 - SDCARD_TX_DATA_DLL_CNTL1<br>- SDCARD_TX_DATA_DLL_CNTL1. 0xA13(Default).<br>-**/<br>- UINT32 SdcardTxDataCntl1;<br>-<br>-/** Offset 0x02EC - SDCARD_TX_DATA_DLL_CNTL2<br>- SDCARD_TX_DATA_DLL_CNTL2. 0x24242828(Default).<br>-**/<br>- UINT32 SdcardTxDataCntl2;<br>-<br>-/** Offset 0x02F0 - SDCARD_RX_CMD_DATA_DLL_CNTL1<br>- SDCARD_RX_CMD_DATA_DLL_CNTL1. 0x73A3637(Default).<br>-**/<br>- UINT32 SdcardRxCmdDataCntl1;<br>-<br>-/** Offset 0x02F4 - SDCARD_RX_STROBE_DLL_CNTL<br>- SDCARD_RX_STROBE_DLL_CNTL. 0x0(Default).<br>-**/<br>- UINT32 SdcardRxStrobeCntl;<br>-<br>-/** Offset 0x02F8 - SDCARD_RX_CMD_DATA_DLL_CNTL2<br>- SDCARD_RX_CMD_DATA_DLL_CNTL2. 0x10000(Default).<br>-**/<br>- UINT32 SdcardRxCmdDataCntl2;<br>-<br>-/** Offset 0x02FC - EMMC_TX_CMD_DLL_CNTL<br>- EMMC_TX_CMD_DLL_CNTL. 0x505(Default).<br>-**/<br>- UINT32 EmmcTxCmdCntl;<br>-<br>-/** Offset 0x0300 - EMMC_TX_DATA_DLL_CNTL1<br>- EMMC_TX_DATA_DLL_CNTL1. 0xC11(Default).<br>-**/<br>- UINT32 EmmcTxDataCntl1;<br>-<br>-/** Offset 0x0304 - EMMC_TX_DATA_DLL_CNTL2<br>- EMMC_TX_DATA_DLL_CNTL2. 0x1C2A2927(Default).<br>-**/<br>- UINT32 EmmcTxDataCntl2;<br>-<br>-/** Offset 0x0308 - EMMC_RX_CMD_DATA_DLL_CNTL1<br>- EMMC_RX_CMD_DATA_DLL_CNTL1. 0x000D162F(Default).<br>-**/<br>- UINT32 EmmcRxCmdDataCntl1;<br>-<br>-/** Offset 0x030C - EMMC_RX_STROBE_DLL_CNTL<br>- EMMC_RX_STROBE_DLL_CNTL. 0x0a0a(Default).<br>-**/<br>- UINT32 EmmcRxStrobeCntl;<br>-<br>-/** Offset 0x0310 - EMMC_RX_CMD_DATA_DLL_CNTL2<br>- EMMC_RX_CMD_DATA_DLL_CNTL2. 0x1003b(Default).<br>-**/<br>- UINT32 EmmcRxCmdDataCntl2;<br>-<br>-/** Offset 0x0314 - EMMC_MASTER_DLL_CNTL<br>- EMMC_MASTER_DLL_CNTL. 0x001(Default).<br>-**/<br>- UINT32 EmmcMasterSwCntl;<br>-<br>-/** Offset 0x0318 - PCIe Selectable De-emphasis<br>- When the Link is operating at 5.0 GT/s speed, this bit selects the level of de-emphasis<br>- for an Upstream component. 1b:-3.5 dB 0b:-6 dB. 0:Disable, 1:Enable(Default).<br>-**/<br>- UINT8 PcieRpSelectableDeemphasis[6];<br>-<br>-/** Offset 0x031E - Monitor Mwait Enable<br>- Enable/Disable Monitor Mwait. For Windows* OS, this should be Enabled. For Linux<br>- based OS, this should be Disabled. 0:Disable, 1:Enable(Default).<br>- $EN_DIS<br>-**/<br>- UINT8 MonitorMwaitEnable;<br>-<br>-/** Offset 0x031F - Universal Audio Architecture compliance for DSP enabled system<br>- 0: Not-UAA Compliant (Intel SST driver supported only), 1: UAA Compliant (HDA Inbox<br>- driver or SST driver supported).<br>- $EN_DIS<br>-**/<br>- UINT8 HdAudioDspUaaCompliance;<br>-<br>-/** Offset 0x0320 - IRQ Interrupt Polarity Control<br>- Set IRQ Interrupt Polarity Control to ITSS.IPC[0]~IPC[3]. 0:Active High, 1:Active Low<br>-**/<br>- UINT32 IPC[4];<br>-<br>-/** Offset 0x0330 - Disable ModPHY dynamic power gate<br>- Disable ModPHY dynamic power gate for the specific SATA port.<br>-**/<br>- UINT8 SataPortsDisableDynamicPg[2];<br>-<br>-/** Offset 0x0332 - Init CPU during S3 resume<br>- 0: Do not initialize CPU during S3 resume. 1: Initialize CPU during S3 resume.<br>- $EN_DIS<br>-**/<br>- UINT8 InitS3Cpu;<br>-<br>-/** Offset 0x0333 - SGX Epoch 0<br>- SGX Epoch 0. 0x0(Default).<br>-**/<br>- UINT64 SgxEpoch0;<br>-<br>-/** Offset 0x033B - SGX Epoch 1<br>- SGX Epoch 1. 0x0(Default).<br>-**/<br>- UINT64 SgxEpoch1;<br>-<br>-/** Offset 0x0343 - Selective enable SGX<br>- Selective enable SGX. 0xFFFF(Default).<br>-**/<br>- UINT16 SelectiveEnableSgx;<br>-<br>-/** Offset 0x0345 - SGX debug mode<br>- Select SGX mode. 0:Disable(default), 1:Enable<br>- 0:Disable(default), 1:Enable<br>-**/<br>- UINT8 SgxDebugMode;<br>-<br>-/** Offset 0x0346 - MicrocodePatchAddress<br>- MicrocodePatchAddress. 0x0(Default).<br>-**/<br>- UINT64 MicrocodePatchAddress;<br>-<br>-/** Offset 0x034E - SGX Launch Control Policy Mode<br>- Select Launch Control Policy Mode. 0:Intel - Default, 1:Per-boot Select mode(default)<br>- 0:Intel - Default, 1:Per-boot Select mode(default)<br>-**/<br>- UINT8 LcpMode;<br>-<br>-/** Offset 0x034F - LE KeyHash0<br>- LE KeyHash0. 0x0(Default).<br>-**/<br>- UINT64 SgxLeKeyHash0;<br>-<br>-/** Offset 0x0357 - LE KeyHash1<br>- LE KeyHash1. 0x0(Default).<br>-**/<br>- UINT64 SgxLeKeyHash1;<br>-<br>-/** Offset 0x035F - LE KeyHash2<br>- LE KeyHash2. 0x0(Default).<br>-**/<br>- UINT64 SgxLeKeyHash2;<br>-<br>-/** Offset 0x0367 - LE KeyHash3<br>- LE KeyHash3. 0x0(Default).<br>-**/<br>- UINT64 SgxLeKeyHash3;<br>-<br>-/** Offset 0x036F - CNVi Mode<br>- Selects CNVi Mode. 0:Disable, 1:Auto(Default).<br>- $EN_DIS<br>-**/<br>- UINT8 CnviMode;<br>-<br>-/** Offset 0x0370 - BT Interface<br>- CNVi BT interface. 0:UART, 1:USB(Default).<br>- $EN_DIS<br>-**/<br>- UINT8 CnviBtInterface;<br>-<br>-/** Offset 0x0371 - Disable Sx Wake<br>- Enables/Disables wake from Sx . 0:No(Default), 1:Yes.<br>- $EN_DIS<br>-**/<br>- UINT8 PowerRailMerge;<br>-<br>-/** Offset 0x0372 - ModifyCrfGpios<br>- Feature to Configure CRF Gpios Conditionally upon platform requirement, configuration<br>- of GNSS and BtOnUart gpios will/will not be done based on this policy<br>- $EN_DIS<br>-**/<br>- UINT8 ModifyCrfGpios;<br>-<br>-/** Offset 0x0373 - dGPU Hold Reset<br>- dGPU Hold Reset GPIO information from GPIO community, Pin and Active<br>-**/<br>- UINT8 HgDgpuHoldRst[8];<br>-<br>-/** Offset 0x037B - dGPU Power Enable<br>- dGPU power enable GPIO information from GPIO community, Pin and Active<br>-**/<br>- UINT8 HgDgpuPwrEnable[8];<br>-<br>-/** Offset 0x0383 - dGPU Delay after power enable<br>- Delay for DGPU after Hold Reset if HG is enable : 0 : Minimum , 1000 : Maximum ,<br>- 300 : Default<br>- 0 : Minimum , 1000 : Maximum , 300 : Default<br>-**/<br>- UINT16 HgDelayAfterPwrEn;<br>-<br>-/** Offset 0x0385 - dGPU Delay after hold reset<br>- Delay for DGPU after Hold Reset if HG is enable : 0 : Minimum , 1000 : Maximum ,<br>- 100 : Default<br>- 0 : Minimum , 1000 : Maximum , 100 : Default<br>-**/<br>- UINT16 HgDelayAfterHoldReset;<br>-<br>-/** Offset 0x0387 - HG Enable<br>- Enables/Disables Hybrid Graphics . 0 : Disable(Default), 1 : Enable<br>- 0x1:Enabled, 0x0:Disabled<br>-**/<br>- UINT8 HgEnabled;<br>-<br>-/** Offset 0x0388 - PAVP ASMF<br>- Enable/Disable PAVP ASMF 0:Disable, 1:Enable(Default).<br>- $EN_DIS<br>-**/<br>- UINT8 PavpAsmf;<br>-<br>-/** Offset 0x0389 - CpuS3ResumeMtrrDataSize<br>- Size of S3 resume MTRR data.<br>-**/<br>- UINT16 CpuS3ResumeMtrrDataSize;<br>-<br>-/** Offset 0x038B - CpuS3ResumeMtrrData<br>- Pointer CPU S3 Resume MTRR Data<br>-**/<br>- UINT32 CpuS3ResumeMtrrData;<br>-<br>-/** Offset 0x038F - PAVP Auto TearDown Grace Period Enable<br>- Enable/Disable PAVP Auto TearDown Grace Period 0:Disable, 1:Enable(Default).<br>- $EN_DIS<br>-**/<br>- UINT8 AutoTearDownGracePeriod;<br>-<br>-/** Offset 0x0390 - SeC EndOfPost EnableDisable<br>- Enable/Disable SeC EOPEnable 0:Disable, 1:Enable(Default).<br>- $EN_DIS<br>-**/<br>- UINT8 EndOfPostEnabled;<br>-<br>-/** Offset 0x0391<br>-**/<br>- UINT8 ReservedFspsUpd[3];<br>-} FSP_S_CONFIG;<br>-<br>-/** Fsp S Test Configuration<br>-**/<br>-typedef struct {<br>-<br>-/** Offset 0x0394<br>-**/<br>- UINT32 Signature;<br>-<br>-/** Offset 0x0398<br>-**/<br>- UINT8 ReservedFspsTestUpd[12];<br>-} FSP_S_TEST_CONFIG;<br>-<br>-/** Fsp S Restricted Configuration<br>-**/<br>-typedef struct {<br>-<br>-/** Offset 0x03A4<br>-**/<br>- UINT32 Signature;<br>-<br>-/** Offset 0x03A8<br>-**/<br>- UINT8 ReservedFspsRestrictedUpd[2];<br>-} FSP_S_RESTRICTED_CONFIG;<br>-<br>-/** Fsp S UPD Configuration<br>-**/<br>-typedef struct {<br>-<br>-/** Offset 0x0000<br>-**/<br>- FSP_UPD_HEADER FspUpdHeader;<br>-<br>-/** Offset 0x0020<br>-**/<br>- FSP_S_CONFIG FspsConfig;<br>-<br>-/** Offset 0x0394<br>-**/<br>- FSP_S_TEST_CONFIG FspsTestConfig;<br>-<br>-/** Offset 0x03A4<br>-**/<br>- FSP_S_RESTRICTED_CONFIG FspsRestrictedConfig;<br>-<br>-/** Offset 0x03AA<br>-**/<br>- UINT16 UpdTerminator;<br>-} FSPS_UPD;<br>-<br>-#pragma pack(pop)<br>-<br>-#endif<br>+/** @file<br>+<br>+Copyright (c) 2017, Intel Corporation. All rights reserved.<BR><br>+<br>+Redistribution and use in source and binary forms, with or without modification,<br>+are permitted provided that the following conditions are met:<br>+<br>+* Redistributions of source code must retain the above copyright notice, this<br>+ list of conditions and the following disclaimer.<br>+* Redistributions in binary form must reproduce the above copyright notice, this<br>+ list of conditions and the following disclaimer in the documentation and/or<br>+ other materials provided with the distribution.<br>+* Neither the name of Intel Corporation nor the names of its contributors may<br>+ be used to endorse or promote products derived from this software without<br>+ specific prior written permission.<br>+<br>+ THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"<br>+ AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE<br>+ IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE<br>+ ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE<br>+ LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR<br>+ CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF<br>+ SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS<br>+ INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN<br>+ CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)<br>+ ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF<br>+ THE POSSIBILITY OF SUCH DAMAGE.<br>+<br>+ This file is automatically generated. Please do NOT modify !!!<br>+<br>+**/<br>+<br>+#ifndef __FSPSUPD_H__<br>+#define __FSPSUPD_H__<br>+<br>+#include <FspUpd.h><br>+<br>+#pragma pack(1)<br>+<br>+<br>+/** Fsp S Configuration<br>+**/<br>+typedef struct {<br>+<br>+/** Offset 0x0020 - ActiveProcessorCores<br>+ Number of active cores. 0:Disable(Default), 1:Enable.<br>+**/<br>+ UINT8 ActiveProcessorCores;<br>+<br>+/** Offset 0x0021 - Disable Core1<br>+ Disable/Enable Core1. 0:Disable, 1:Enable(Default).<br>+ $EN_DIS<br>+**/<br>+ UINT8 DisableCore1;<br>+<br>+/** Offset 0x0022 - Disable Core2<br>+ Disable/Enable Core2. 0:Disable, 1:Enable(Default).<br>+ $EN_DIS<br>+**/<br>+ UINT8 DisableCore2;<br>+<br>+/** Offset 0x0023 - Disable Core3<br>+ Disable/Enable Core3. 0:Disable, 1:Enable(Default).<br>+ $EN_DIS<br>+**/<br>+ UINT8 DisableCore3;<br>+<br>+/** Offset 0x0024 - VMX Enable<br>+ Enable or Disable VMX. 0:Disable, 1:Enable(Default).<br>+ $EN_DIS<br>+**/<br>+ UINT8 VmxEnable;<br>+<br>+/** Offset 0x0025 - Memory region allocation for Processor Trace<br>+ Memory region allocation for Processor Trace, allowed range is from 4K (0x0) to<br>+ 128MB (0xF); <b>0xFF: Disable. 0xFF:Disable(Default)<br>+**/<br>+ UINT8 ProcTraceMemSize;<br>+<br>+/** Offset 0x0026 - Enable Processor Trace<br>+ Enable or Disable Processor Trace feature. 0:Disable(Default), 1:Enable.<br>+ $EN_DIS<br>+**/<br>+ UINT8 ProcTraceEnable;<br>+<br>+/** Offset 0x0027 - Eist<br>+ Enable or Disable Intel SpeedStep Technology. 0:Disable, 1:Enable(Default).<br>+ $EN_DIS<br>+**/<br>+ UINT8 Eist;<br>+<br>+/** Offset 0x0028 - Boot PState<br>+ Boot PState with HFM or LFM. 0:HFM(Default), 1:LFM.<br>+**/<br>+ UINT8 BootPState;<br>+<br>+/** Offset 0x0029 - CPU power states (C-states)<br>+ Enable or Disable CPU power states (C-states). 0:Disable, 1:Enable(Default).<br>+ $EN_DIS<br>+**/<br>+ UINT8 EnableCx;<br>+<br>+/** Offset 0x002A - Enhanced C-states<br>+ Enable or Disable Enhanced C-states. 0:Disable(Default), 1:Enable.<br>+ $EN_DIS<br>+**/<br>+ UINT8 C1e;<br>+<br>+/** Offset 0x002B - Bi-Directional PROCHOT#<br>+ Enable or Disable Bi-Directional PROCHOT#. 0:Disable, 1:Enable(Default).<br>+ $EN_DIS<br>+**/<br>+ UINT8 BiProcHot;<br>+<br>+/** Offset 0x002C - Max Pkg Cstate<br>+ Max Pkg Cstate. 0:PkgC0C1, 1:PkgC2, 2:PkgC3(Default), 3:PkgC6, 4:PkgC7, 5:PkgC7s,<br>+ 6:PkgC8, 7:PkgC9, 8:PkgC10, 9:PkgCMax, 254:PkgCpuDefault, 255:PkgAuto.<br>+**/<br>+ UINT8 PkgCStateLimit;<br>+<br>+/** Offset 0x002D - C-State auto-demotion<br>+ C-State Auto Demotion. 0:Disable(Default) C1 and C3 Auto-demotion, 1:Enable C3/C6/C7<br>+ Auto-demotion to C1, 2:Enable C6/C7 Auto-demotion to C3, 3:Enable C6/C7 Auto-demotion<br>+ to C1 and C3.<br>+**/<br>+ UINT8 CStateAutoDemotion;<br>+<br>+/** Offset 0x002E - C-State un-demotion<br>+ C-State un-demotion. 0:Disable(Default) C1 and C3 Un-demotion, 1:Enable C1 Un-demotion,<br>+ 2:Enable C3 Un-demotion, 3:Enable C1 and C3 Un-demotion.<br>+**/<br>+ UINT8 CStateUnDemotion;<br>+<br>+/** Offset 0x002F - Max Core C-State<br>+ Max Core C-State. 0:Unlimited, 1:C1, 2:C3, 3:C6, 4:C7, 5:C8, 6:C9, 7:C10, 8:CCx(Default).<br>+**/<br>+ UINT8 MaxCoreCState;<br>+<br>+/** Offset 0x0030 - Package C-State Demotion<br>+ Enable or Disable Package Cstate Demotion. 0:Disable(Default), 1:Enable.<br>+ $EN_DIS<br>+**/<br>+ UINT8 PkgCStateDemotion;<br>+<br>+/** Offset 0x0031 - Package C-State Un-demotion<br>+ Enable or Disable Package Cstate UnDemotion. 0:Disable(Default), 1:Enable.<br>+ $EN_DIS<br>+**/<br>+ UINT8 PkgCStateUnDemotion;<br>+<br>+/** Offset 0x0032 - Turbo Mode<br>+ Enable or Disable long duration Turbo Mode. 0:Disable, 1:Enable(Default).<br>+ $EN_DIS<br>+**/<br>+ UINT8 TurboMode;<br>+<br>+/** Offset 0x0033 - SC HDA Verb Table Entry Number<br>+ Number of Entries in Verb Table. 0(Default).<br>+**/<br>+ UINT8 HdaVerbTableEntryNum;<br>+<br>+/** Offset 0x0034 - SC HDA Verb Table Pointer<br>+ Pointer to Array of pointers to Verb Table. 0x00000000(Default).<br>+**/<br>+ UINT32 HdaVerbTablePtr;<br>+<br>+/** Offset 0x0038 - Enable/Disable P2SB device hidden.<br>+ Enable/Disable P2SB device hidden. 0:Disable(Default), 1:Enable.<br>+ $EN_DIS<br>+**/<br>+ UINT8 P2sbUnhide;<br>+<br>+/** Offset 0x0039 - IPU Enable/Disable<br>+ Enable/Disable IPU Device. 0:Disable, 1:Enable(Default).<br>+ $EN_DIS<br>+**/<br>+ UINT8 IpuEn;<br>+<br>+/** Offset 0x003A - IMGU ACPI mode selection<br>+ 0:Auto, 1:IGFX Child device(Default), 2:ACPI device.<br>+ 0:Disable, 1:IGFX Child device, 2:ACPI device<br>+**/<br>+ UINT8 IpuAcpiMode;<br>+<br>+/** Offset 0x003B - Enable ForceWake<br>+ Enable/disable ForceWake Models. 0:Disable(Default), 1:Enable.<br>+ $EN_DIS<br>+**/<br>+ UINT8 ForceWake;<br>+<br>+/** Offset 0x003C - GttMmAdr<br>+ GttMmAdr structure for initialization. 0xBF000000(Default).<br>+**/<br>+ UINT32 GttMmAdr;<br>+<br>+/** Offset 0x0040 - GmAdr<br>+ GmAdr structure for initialization. 0xA0000000(Default).<br>+**/<br>+ UINT32 GmAdr;<br>+<br>+/** Offset 0x0044 - Enable PavpLock<br>+ Enable/disable PavpLock. 0:Disable(Default), 1:Enable.<br>+ $EN_DIS<br>+**/<br>+ UINT8 PavpLock;<br>+<br>+/** Offset 0x0045 - Enable GraphicsFreqModify<br>+ Enable/disable GraphicsFreqModify. 0:Disable(Default), 1:Enable.<br>+ $EN_DIS<br>+**/<br>+ UINT8 GraphicsFreqModify;<br>+<br>+/** Offset 0x0046 - Enable GraphicsFreqReq<br>+ Enable/disable GraphicsFreqReq. 0:Disable(Default), 1:Enable.<br>+ $EN_DIS<br>+**/<br>+ UINT8 GraphicsFreqReq;<br>+<br>+/** Offset 0x0047 - Enable GraphicsVideoFreq<br>+ Enable/disable GraphicsVideoFreq. 0:Disable(Default), 1:Enable.<br>+ $EN_DIS<br>+**/<br>+ UINT8 GraphicsVideoFreq;<br>+<br>+/** Offset 0x0048 - Enable PmLock<br>+ Enable/disable PmLock. 0:Disable(Default), 1:Enable.<br>+ $EN_DIS<br>+**/<br>+ UINT8 PmLock;<br>+<br>+/** Offset 0x0049 - Enable DopClockGating<br>+ Enable/disable DopClockGating. 0:Disable(Default), 1:Enable.<br>+ $EN_DIS<br>+**/<br>+ UINT8 DopClockGating;<br>+<br>+/** Offset 0x004A - Enable UnsolicitedAttackOverride<br>+ Enable/disable UnsolicitedAttackOverride. 0:Disable(Default), 1:Enable.<br>+ $EN_DIS<br>+**/<br>+ UINT8 UnsolicitedAttackOverride;<br>+<br>+/** Offset 0x004B - Enable WOPCMSupport<br>+ Enable/disable WOPCMSupport. 0:Disable(Default), 1:Enable.<br>+ $EN_DIS<br>+**/<br>+ UINT8 WOPCMSupport;<br>+<br>+/** Offset 0x004C - Enable WOPCMSize<br>+ Enable/disable WOPCMSize. 0:Disable(Default), 1:Enable.<br>+ $EN_DIS<br>+**/<br>+ UINT8 WOPCMSize;<br>+<br>+/** Offset 0x004D - Enable PowerGating<br>+ Enable/disable PowerGating. 0:Disable(Default), 1:Enable.<br>+ $EN_DIS<br>+**/<br>+ UINT8 PowerGating;<br>+<br>+/** Offset 0x004E - Enable UnitLevelClockGating<br>+ Enable/disable UnitLevelClockGating. 0:Disable(Default), 1:Enable.<br>+ $EN_DIS<br>+**/<br>+ UINT8 UnitLevelClockGating;<br>+<br>+/** Offset 0x004F - Enable FastBoot<br>+ Enable/disable FastBoot. 0:Disable(Default), 1:Enable.<br>+ $EN_DIS<br>+**/<br>+ UINT8 FastBoot;<br>+<br>+/** Offset 0x0050 - Enable DynSR<br>+ Enable/disable DynSR. 0:Disable(Default), 1:Enable.<br>+ $EN_DIS<br>+**/<br>+ UINT8 DynSR;<br>+<br>+/** Offset 0x0051 - Enable SaIpuEnable<br>+ Enable/disable SaIpuEnable. 0:Disable(Default), 1:Enable.<br>+ $EN_DIS<br>+**/<br>+ UINT8 SaIpuEnable;<br>+<br>+/** Offset 0x0052 - GT PM Support<br>+ Enable/Disable GT power management support. 0:Disable, 1:Enable(Default).<br>+ $EN_DIS<br>+**/<br>+ UINT8 PmSupport;<br>+<br>+/** Offset 0x0053 - RC6(Render Standby)<br>+ Enable/Disable render standby support. 0:Disable, 1:Enable(Default).<br>+ $EN_DIS<br>+**/<br>+ UINT8 EnableRenderStandby;<br>+<br>+/** Offset 0x0054 - BMP Logo Data Size<br>+ BMP logo data buffer size. 0x00000000(Default).<br>+**/<br>+ UINT32 LogoSize;<br>+<br>+/** Offset 0x0058 - BMP Logo Data Pointer<br>+ BMP logo data pointer to a BMP format buffer. 0x00000000(Default).<br>+**/<br>+ UINT32 LogoPtr;<br>+<br>+/** Offset 0x005C - Graphics Configuration Data Pointer<br>+ Graphics configuration data used for initialization. 0x00000000(Default).<br>+**/<br>+ UINT32 GraphicsConfigPtr;<br>+<br>+/** Offset 0x0060 - PAVP Enable<br>+ Enable/Disable Protected Audio Visual Path (PAVP). 0:Disable, 1:Enable(Default).<br>+ $EN_DIS<br>+**/<br>+ UINT8 PavpEnable;<br>+<br>+/** Offset 0x0061 - PAVP PR3<br>+ Enable/Disable PAVP PR3 0:Disable, 1:Enable(Default).<br>+ $EN_DIS<br>+**/<br>+ UINT8 PavpPr3;<br>+<br>+/** Offset 0x0062 - CdClock Frequency selection<br>+ 0:144MHz, 1:288MHz, 2:384MHz, 3:576MHz, 4:624MHz(Default).<br>+ 0: 144 MHz, 1: 288 MHz, 2: 384 MHz, 3: 576 MHz, 4: 624 MHz<br>+**/<br>+ UINT8 CdClock;<br>+<br>+/** Offset 0x0063 - Enable/Disable PeiGraphicsPeimInit<br>+ Enable/Disable PeiGraphicsPeimInit 0:Disable, 1:Enable(Default).<br>+ $EN_DIS<br>+**/<br>+ UINT8 PeiGraphicsPeimInit;<br>+<br>+/** Offset 0x0064 - Write Protection Support<br>+ Enable/disable Write Protection. 0:Disable, 1:Enable(Default).<br>+**/<br>+ UINT8 WriteProtectionEnable[5];<br>+<br>+/** Offset 0x0069 - Read Protection Support<br>+ Enable/disable Read Protection. 0:Disable, 1:Enable(Default).<br>+**/<br>+ UINT8 ReadProtectionEnable[5];<br>+<br>+/** Offset 0x006E - Protected Range Limitation<br>+ The address of the upper limit of protection, 0x0FFFh(Default).<br>+**/<br>+ UINT16 ProtectedRangeLimit[5];<br>+<br>+/** Offset 0x0078 - Protected Range Base<br>+ The base address of the upper limit of protection. 0x0000(Default).<br>+**/<br>+ UINT16 ProtectedRangeBase[5];<br>+<br>+/** Offset 0x0082 - Enable SC Gaussian Mixture Models<br>+ Enable/disable SC Gaussian Mixture Models. 0:Disable, 1:Enable(Default).<br>+ $EN_DIS<br>+**/<br>+ UINT8 Gmm;<br>+<br>+/** Offset 0x0083 - GMM Clock Gating - PGCB Clock Trunk<br>+ Enable/disable PGCB Clock Trunk. 0:Disable, 1:Enable(Default).<br>+ $EN_DIS<br>+**/<br>+ UINT8 ClkGatingPgcbClkTrunk;<br>+<br>+/** Offset 0x0084 - GMM Clock Gating - Sideband<br>+ Enable/disable Sideband. 0:Disable, 1:Enable(Default).<br>+ $EN_DIS<br>+**/<br>+ UINT8 ClkGatingSb;<br>+<br>+/** Offset 0x0085 - GMM Clock Gating - Sideband<br>+ Enable/disable Sideband. 0:Disable, 1:Enable(Default).<br>+ $EN_DIS<br>+**/<br>+ UINT8 ClkGatingSbClkTrunk;<br>+<br>+/** Offset 0x0086 - GMM Clock Gating - Sideband Clock Partition<br>+ Enable/disable Sideband Clock Partition. 0:Disable, 1:Enable(Default).<br>+ $EN_DIS<br>+**/<br>+ UINT8 ClkGatingSbClkPartition;<br>+<br>+/** Offset 0x0087 - GMM Clock Gating - Core<br>+ Enable/disable Core. 0:Disable, 1:Enable(Default).<br>+ $EN_DIS<br>+**/<br>+ UINT8 ClkGatingCore;<br>+<br>+/** Offset 0x0088 - GMM Clock Gating - DMA<br>+ Enable/disable DMA. 0:Disable, 1:Enable(Default).<br>+ $EN_DIS<br>+**/<br>+ UINT8 ClkGatingDma;<br>+<br>+/** Offset 0x0089 - GMM Clock Gating - Register Access<br>+ Enable/disable Register Access. 0:Disable, 1:Enable(Default).<br>+ $EN_DIS<br>+**/<br>+ UINT8 ClkGatingRegAccess;<br>+<br>+/** Offset 0x008A - GMM Clock Gating - Host<br>+ Enable/disable Host. 0:Disable, 1:Enable(Default).<br>+ $EN_DIS<br>+**/<br>+ UINT8 ClkGatingHost;<br>+<br>+/** Offset 0x008B - GMM Clock Gating - Partition<br>+ Enable/disable Partition. 0:Disable, 1:Enable(Default).<br>+ $EN_DIS<br>+**/<br>+ UINT8 ClkGatingPartition;<br>+<br>+/** Offset 0x008C - Clock Gating - Trunk<br>+ Enable/disable Trunk. 0:Disable, 1:Enable(Default).<br>+ $EN_DIS<br>+**/<br>+ UINT8 ClkGatingTrunk;<br>+<br>+/** Offset 0x008D - HD Audio Support<br>+ Enable/disable HDA Audio Feature. 0:Disable, 1:Enable(Default).<br>+ $EN_DIS<br>+**/<br>+ UINT8 HdaEnable;<br>+<br>+/** Offset 0x008E - HD Audio DSP Support<br>+ Enable/disable HDA Audio DSP Feature. 0:Disable, 1:Enable(Default).<br>+ $EN_DIS<br>+**/<br>+ UINT8 DspEnable;<br>+<br>+/** Offset 0x008F - Azalia wake-on-ring<br>+ Enable/disable Azalia wake-on-ring. 0:Disable(Default), 1:Enable.<br>+ $EN_DIS<br>+**/<br>+ UINT8 Pme;<br>+<br>+/** Offset 0x0090 - HD-Audio I/O Buffer Ownership<br>+ Set HD-Audio I/O Buffer Ownership. 0:HD-Audio link owns all the I/O buffers(Default)<br>+ 0:HD-Audio link owns all the I/O buffers, 1:HD-Audio link owns 4 I/O buffers and<br>+ I2S port owns 4 I/O buffers, 3:I2S port owns all the I/O buffers<br>+**/<br>+ UINT8 HdAudioIoBufferOwnership;<br>+<br>+/** Offset 0x0091 - HD-Audio I/O Buffer Voltage<br>+ HD-Audio I/O Buffer Voltage Mode Selectiton . 0:3.3V(Default), 1:1.8V.<br>+ 0: 3.3V, 1: 1.8V<br>+**/<br>+ UINT8 HdAudioIoBufferVoltage;<br>+<br>+/** Offset 0x0092 - HD-Audio Virtual Channel Type<br>+ HD-Audio Virtual Channel Type Selectiton. 0:VC0(Default), 1:VC1.<br>+ 0: VC0, 1: VC1<br>+**/<br>+ UINT8 HdAudioVcType;<br>+<br>+/** Offset 0x0093 - HD-Audio Link Frequency<br>+ HD-Audio Virtual Channel Type Selectiton. 0:6MHz(Default), 1:12MHz, 2:24MHz, 3:48MHz,<br>+ 4:96MHz, 5:Invalid.<br>+ 0: 6MHz, 1: 12MHz, 2: 24MHz, 3: 48MHz, 4: 96MHz, 5: Invalid<br>+**/<br>+ UINT8 HdAudioLinkFrequency;<br>+<br>+/** Offset 0x0094 - HD-Audio iDisp-Link Frequency<br>+ HD-Audio iDisp-Link Frequency Selectiton. 0:6MHz(Default), 1:12MHz, 2:24MHz, 3:48MHz,<br>+ 4:96MHz, 5:Invalid.<br>+ 0: 6MHz, 1: 12MHz, 2: 24MHz, 3: 48MHz, 4: 96MHz, 5: Invalid<br>+**/<br>+ UINT8 HdAudioIDispLinkFrequency;<br>+<br>+/** Offset 0x0095 - HD-Audio iDisp-Link T-Mode<br>+ HD-Audio iDisp-Link T-Mode Selectiton. 0:2T(Default), 1:1T.<br>+ 0: 2T, 1: 1T<br>+**/<br>+ UINT8 HdAudioIDispLinkTmode;<br>+<br>+/** Offset 0x0096 - HD-Audio Disp DMIC<br>+ HD-Audio Disp DMIC Selectiton. 0:Disable, 1:2ch array(Default), 2:4ch array.<br>+ 0: Disable, 1: 2ch array, 2: 4ch array<br>+**/<br>+ UINT8 DspEndpointDmic;<br>+<br>+/** Offset 0x0097 - HD-Audio Bluetooth<br>+ Enable/Disable HD-Audio bluetooth. 0:Disable, 1:Enable(Default).<br>+ $EN_DIS<br>+**/<br>+ UINT8 DspEndpointBluetooth;<br>+<br>+/** Offset 0x0098 - HD-Audio I2S SHK<br>+ Enable/Disable HD-Audio I2S SHK. 0:Disable(Default), 1:Enable.<br>+ $EN_DIS<br>+**/<br>+ UINT8 DspEndpointI2sSkp;<br>+<br>+/** Offset 0x0099 - HD-Audio I2S HP<br>+ Enable/Disable HD-Audio I2S HP. 0:Disable(Default), 1:Enable.<br>+ $EN_DIS<br>+**/<br>+ UINT8 DspEndpointI2sHp;<br>+<br>+/** Offset 0x009A - HD-Audio Controller Power Gating<br>+ Enable/Disable HD-Audio Controller Power Gating. This option is deprecated.<br>+ $EN_DIS<br>+**/<br>+ UINT8 AudioCtlPwrGate;<br>+<br>+/** Offset 0x009B - HD-Audio ADSP Power Gating<br>+ Enable/Disable HD-Audio ADSP Power Gating. This option is deprecated.<br>+ $EN_DIS<br>+**/<br>+ UINT8 AudioDspPwrGate;<br>+<br>+/** Offset 0x009C - HD-Audio CSME Memory Transfers<br>+ Enable/Disable HD-Audio CSME Memory Transfers. 0:VC0(Default), 1:VC2.<br>+ 0: VC0, 1: VC2<br>+**/<br>+ UINT8 Mmt;<br>+<br>+/** Offset 0x009D - HD-Audio Host Memory Transfers<br>+ Enable/Disable HD-Audio Host Memory Transfers. 0:VC0(Default), 1:VC2.<br>+ 0: VC0, 1: VC2<br>+**/<br>+ UINT8 Hmt;<br>+<br>+/** Offset 0x009E - HD-Audio Power Gating<br>+ Enable/Disable HD-Audio BIOS Configuration Lock Down. 0:Disable(Default), 1:Enable.<br>+ $EN_DIS<br>+**/<br>+ UINT8 HDAudioPwrGate;<br>+<br>+/** Offset 0x009F - HD-Audio Clock Gatingn<br>+ Enable/Disable HD-Audio Clock Gating. 0:Disable(Default), 1:Enable.<br>+ $EN_DIS<br>+**/<br>+ UINT8 HDAudioClkGate;<br>+<br>+/** Offset 0x00A0 - Bitmask of DSP Feature<br>+ Set Bitmask of HD-Audio DSP Feature. 0x00000000(Default).<br>+ [BIT0] - WoV, [BIT1] - BT Sideband, [BIT2] - Codec VAD, [BIT5] - BT Intel HFP, [BIT6]<br>+ - BT Intel A2DP, [BIT7] - DSP based speech pre-processing disabled, [BIT8] - 0:<br>+ Intel WoV, 1: Windows Voice Activation<br>+**/<br>+ UINT32 DspFeatureMask;<br>+<br>+/** Offset 0x00A4 - Bitmask of supported DSP Post-Processing Modules<br>+ Set HD-Audio Bitmask of supported DSP Post-Processing Modules. 0x00000000(Default).<br>+ [BIT0] - WoV, [BIT1] - BT Sideband, [BIT2] - Codec VAD, [BIT5] - BT Intel HFP, [BIT6]<br>+ - BT Intel A2DP, [BIT7] - DSP based speech pre-processing disabled, [BIT8] - 0:<br>+ Intel WoV, 1: Windows Voice Activation<br>+**/<br>+ UINT32 DspPpModuleMask;<br>+<br>+/** Offset 0x00A8 - HD-Audio BIOS Configuration Lock Down<br>+ Enable/Disable HD-Audio BIOS Configuration Lock Down. 0:Disable(Default), 1:Enable.<br>+ This option is deprecated<br>+ $EN_DIS<br>+**/<br>+ UINT8 BiosCfgLockDown;<br>+<br>+/** Offset 0x00A9 - Enable High Precision Timer<br>+ Enable/Disable Hpet. 0:Disable, 1:Enable(Default).<br>+ $EN_DIS<br>+**/<br>+ UINT8 Hpet;<br>+<br>+/** Offset 0x00AA - Hpet Valid BDF Value<br>+ Enable/Disable Hpet Valid BDF Value. 0:Disable(Default), 1:Enable.<br>+ $EN_DIS<br>+**/<br>+ UINT8 HpetBdfValid;<br>+<br>+/** Offset 0x00AB - Bus Number of Hpet<br>+ Completer ID of Bus Number of Hpet. Default = 0xFA(Default).<br>+**/<br>+ UINT8 HpetBusNumber;<br>+<br>+/** Offset 0x00AC - Device Number of Hpet<br>+ Completer ID of Device Number of Hpet. 0x1F(Default).<br>+**/<br>+ UINT8 HpetDeviceNumber;<br>+<br>+/** Offset 0x00AD - Function Number of Hpet<br>+ Completer ID of Function Number of Hpet. 0x00(Default).<br>+**/<br>+ UINT8 HpetFunctionNumber;<br>+<br>+/** Offset 0x00AE - IoApic Valid BDF Value<br>+ Enable/Disable IoApic Valid BDF Value. 0:Disable(Default), 1:Enable.<br>+ $EN_DIS<br>+**/<br>+ UINT8 IoApicBdfValid;<br>+<br>+/** Offset 0x00AF - Bus Number of IoApic<br>+ Completer ID of Bus Number of IoApic. 0xFA(Default).<br>+**/<br>+ UINT8 IoApicBusNumber;<br>+<br>+/** Offset 0x00B0 - Device Number of IoApic<br>+ Completer ID of Device Number of IoApic. 0x0F(Default).<br>+**/<br>+ UINT8 IoApicDeviceNumber;<br>+<br>+/** Offset 0x00B1 - Function Number of IoApic<br>+ Completer ID of Function Number of IoApic. 0x00(Default).<br>+**/<br>+ UINT8 IoApicFunctionNumber;<br>+<br>+/** Offset 0x00B2 - IOAPIC Entry 24-119<br>+ Enable/Disable IOAPIC Entry 24-119. 0:Disable, 1:Enable(Default).<br>+ $EN_DIS<br>+**/<br>+ UINT8 IoApicEntry24_119;<br>+<br>+/** Offset 0x00B3 - IO APIC ID<br>+ This member determines IOAPIC ID. 0x01(Default).<br>+**/<br>+ UINT8 IoApicId;<br>+<br>+/** Offset 0x00B4 - IoApic Range<br>+ Define address bits 19:12 for the IOxAPIC range. 0x00(Default).<br>+**/<br>+ UINT8 IoApicRangeSelect;<br>+<br>+/** Offset 0x00B5 - ISH Controller<br>+ Enable/Disable ISH Controller. 0:Disable, 1:Enable(Default).<br>+ $EN_DIS<br>+**/<br>+ UINT8 IshEnable;<br>+<br>+/** Offset 0x00B6 - BIOS Interface Lock Down<br>+ Enable/Disable BIOS Interface Lock Down bit to prevent writes to the Backup Control<br>+ Register. 0:Disable, 1:Enable(Default).<br>+ $EN_DIS<br>+**/<br>+ UINT8 BiosInterface;<br>+<br>+/** Offset 0x00B7 - Bios LockDown Enable<br>+ Enable the BIOS Lock Enable (BLE) feature and set EISS bit. 0:Disable(Default), 1:Enable.<br>+ $EN_DIS<br>+**/<br>+ UINT8 BiosLock;<br>+<br>+/** Offset 0x00B8 - SPI EISS Status<br>+ Enable/Disable InSMM.STS (EISS) in SPI. 0:Disable, 1:Enable(Default).<br>+ $EN_DIS<br>+**/<br>+ UINT8 SpiEiss;<br>+<br>+/** Offset 0x00B9 - BiosLock SWSMI Number<br>+ This member describes the SwSmi value for Bios Lock. 0xA9(Default).<br>+**/<br>+ UINT8 BiosLockSwSmiNumber;<br>+<br>+/** Offset 0x00BA - LPSS IOSF PMCTL S0ix Enable<br>+ Enable/Disable LPSS IOSF Bridge PMCTL Register S0ix Bits. 0:Disable(Default), 1:Enable.<br>+ $EN_DIS<br>+**/<br>+ UINT8 LPSS_S0ixEnable;<br>+<br>+/** Offset 0x00BB<br>+**/<br>+ UINT8 UnusedUpdSpace0[1];<br>+<br>+/** Offset 0x00BC - LPSS I2C Clock Gating Configuration<br>+ Enable/Disable LPSS I2C Clock Gating. 0:Disable, 1:Enable(Default).<br>+**/<br>+ UINT8 I2cClkGateCfg[8];<br>+<br>+/** Offset 0x00C4 - PSS HSUART Clock Gating Configuration<br>+ Enable/Disable LPSS HSUART Clock Gating. 0:Disable, 1:Enable(Default).<br>+**/<br>+ UINT8 HsuartClkGateCfg[4];<br>+<br>+/** Offset 0x00C8 - LPSS SPI Clock Gating Configuration<br>+ Enable/Disable LPSS SPI Clock Gating. 0:Disable, 1:Enable(Default).<br>+**/<br>+ UINT8 SpiClkGateCfg[3];<br>+<br>+/** Offset 0x00CB - I2C Device 0<br>+ Enable/Disable I2C Device 0. 0:Disabled, 1:PCI Mode(Default), 2:ACPI Mode.<br>+ 0: Disabled, 1: PCI Mode, 2: ACPI Mode<br>+**/<br>+ UINT8 I2c0Enable;<br>+<br>+/** Offset 0x00CC - I2C Device 1<br>+ Enable/Disable I2C Device 1. 0:Disabled, 1:PCI Mode(Default), 2:ACPI Mode.<br>+ 0: Disabled, 1: PCI Mode, 2: ACPI Mode<br>+**/<br>+ UINT8 I2c1Enable;<br>+<br>+/** Offset 0x00CD - I2C Device 2<br>+ Enable/Disable I2C Device 2. 0:Disabled, 1:PCI Mode(Default), 2:ACPI Mode.<br>+ 0: Disabled, 1: PCI Mode, 2: ACPI Mode<br>+**/<br>+ UINT8 I2c2Enable;<br>+<br>+/** Offset 0x00CE - I2C Device 3<br>+ Enable/Disable I2C Device 3. 0:Disabled, 1:PCI Mode(Default), 2:ACPI Mode.<br>+ 0: Disabled, 1: PCI Mode, 2: ACPI Mode<br>+**/<br>+ UINT8 I2c3Enable;<br>+<br>+/** Offset 0x00CF - I2C Device 4<br>+ Enable/Disable I2C Device 4. 0:Disabled, 1:PCI Mode(Default), 2:ACPI Mode.<br>+ 0: Disabled, 1: PCI Mode, 2: ACPI Mode<br>+**/<br>+ UINT8 I2c4Enable;<br>+<br>+/** Offset 0x00D0 - I2C Device 5<br>+ Enable/Disable I2C Device 5. 0:Disabled, 1:PCI Mode(Default), 2:ACPI Mode.<br>+ 0: Disabled, 1: PCI Mode, 2: ACPI Mode<br>+**/<br>+ UINT8 I2c5Enable;<br>+<br>+/** Offset 0x00D1 - I2C Device 6<br>+ Enable/Disable I2C Device 6. 0:Disabled, 1:PCI Mode(Default), 2:ACPI Mode.<br>+ 0: Disabled, 1: PCI Mode, 2: ACPI Mode<br>+**/<br>+ UINT8 I2c6Enable;<br>+<br>+/** Offset 0x00D2 - I2C Device 7<br>+ Enable/Disable I2C Device 7. 0:Disabled, 1:PCI Mode(Default), 2:ACPI Mode.<br>+ 0: Disabled, 1: PCI Mode, 2: ACPI Mode<br>+**/<br>+ UINT8 I2c7Enable;<br>+<br>+/** Offset 0x00D3 - UART Device 0<br>+ Enable/Disable UART Device 0. 0:Disabled, 1:PCI Mode(Default), 2:ACPI Mode.<br>+ 0: Disabled, 1: PCI Mode, 2: ACPI Mode<br>+**/<br>+ UINT8 Hsuart0Enable;<br>+<br>+/** Offset 0x00D4 - UART Device 1<br>+ Enable/Disable UART Device 1. 0:Disabled, 1:PCI Mode(Default), 2:ACPI Mode.<br>+ 0: Disabled, 1: PCI Mode, 2: ACPI Mode<br>+**/<br>+ UINT8 Hsuart1Enable;<br>+<br>+/** Offset 0x00D5 - UART Device 2<br>+ Enable/Disable UART Device 2. 0:Disabled, 1:PCI Mode(Default), 2:ACPI Mode.<br>+ 0: Disabled, 1: PCI Mode, 2: ACPI Mode<br>+**/<br>+ UINT8 Hsuart2Enable;<br>+<br>+/** Offset 0x00D6 - UART Device 3<br>+ Enable/Disable UART Device 3. 0:Disabled, 1:PCI Mode(Default), 2:ACPI Mode.<br>+ 0: Disabled, 1: PCI Mode, 2: ACPI Mode<br>+**/<br>+ UINT8 Hsuart3Enable;<br>+<br>+/** Offset 0x00D7 - SPI UART Device 0<br>+ Enable/Disable SPI Device 0. 0:Disabled, 1:PCI Mode(Default), 2:ACPI Mode.<br>+ 0: Disabled, 1: PCI Mode, 2: ACPI Mode<br>+**/<br>+ UINT8 Spi0Enable;<br>+<br>+/** Offset 0x00D8 - SPI UART Device 1<br>+ Enable/Disable SPI Device 1. 0:Disabled, 1:PCI Mode(Default), 2:ACPI Mode.<br>+ 0: Disabled, 1: PCI Mode, 2: ACPI Mode<br>+**/<br>+ UINT8 Spi1Enable;<br>+<br>+/** Offset 0x00D9 - SPI UART Device 2<br>+ Enable/Disable SPI Device 2. 0:Disabled, 1:PCI Mode(Default), 2:ACPI Mode.<br>+ 0: Disabled, 1: PCI Mode, 2: ACPI Mode<br>+**/<br>+ UINT8 Spi2Enable;<br>+<br>+/** Offset 0x00DA - OS Debug Feature<br>+ Enable/Disable OS Debug Feature. 0:Disable(Default), 1: Enable.<br>+ $EN_DIS<br>+**/<br>+ UINT8 OsDbgEnable;<br>+<br>+/** Offset 0x00DB - DCI Feature<br>+ Enable/Disable DCI Feature. 0:Disable(Default), 1: Enable.<br>+ $EN_DIS<br>+**/<br>+ UINT8 DciEn;<br>+<br>+/** Offset 0x00DC - UART Debug Base Address<br>+ UART Debug Base Address. 0x00000000(Default).<br>+**/<br>+ UINT32 Uart2KernelDebugBaseAddress;<br>+<br>+/** Offset 0x00E0 - Enable PCIE Clock Gating<br>+ Enable/disable PCIE Clock Gating. 0:Enable, 1:Disable(Default).<br>+ 0:Enable, 1:Disable<br>+**/<br>+ UINT8 PcieClockGatingDisabled;<br>+<br>+/** Offset 0x00E1 - Enable PCIE Root Port 8xh Decode<br>+ Enable/disable PCIE Root Port 8xh Decode. 0:Disable, 1:Enable(Default).<br>+ $EN_DIS<br>+**/<br>+ UINT8 PcieRootPort8xhDecode;<br>+<br>+/** Offset 0x00E2 - PCIE 8xh Decode Port Index<br>+ PCIE 8xh Decode Port Index. 0x00(Default).<br>+**/<br>+ UINT8 Pcie8xhDecodePortIndex;<br>+<br>+/** Offset 0x00E3 - Enable PCIE Root Port Peer Memory Write<br>+ Enable/disable PCIE root port peer memory write. 0:Disable(Default), 1:Enable.<br>+ $EN_DIS<br>+**/<br>+ UINT8 PcieRootPortPeerMemoryWriteEnable;<br>+<br>+/** Offset 0x00E4 - PCIE SWSMI Number<br>+ This member describes the SwSmi value for override PCIe ASPM table. 0xAA(Default).<br>+**/<br>+ UINT8 PcieAspmSwSmiNumber;<br>+<br>+/** Offset 0x00E5<br>+**/<br>+ UINT8 UnusedUpdSpace1[1];<br>+<br>+/** Offset 0x00E6 - PCI Express Root Port<br>+ Control the PCI Express Root Port . 0:Disable, 1:Enable(Default).<br>+**/<br>+ UINT8 PcieRootPortEn[6];<br>+<br>+/** Offset 0x00EC - Hide PCIE Root Port Configuration Space<br>+ Enable/disable Hide PCIE Root Port Configuration Space. 0:Disable(Default), 1:Enable.<br>+**/<br>+ UINT8 PcieRpHide[6];<br>+<br>+/** Offset 0x00F2 - PCIE Root Port Slot Implement<br>+ Enable/disable PCIE Root Port Slot Implement. 0:Disable, 1:Enable(Default).<br>+**/<br>+ UINT8 PcieRpSlotImplemented[6];<br>+<br>+/** Offset 0x00F8 - Hot Plug<br>+ PCI Express Hot Plug Enable/Disable. 0:Disable, 1:Enable(Default).<br>+**/<br>+ UINT8 PcieRpHotPlug[6];<br>+<br>+/** Offset 0x00FE - PCIE PM SCI<br>+ Enable/Disable PCI Express PME SCI. 0:Disable(Default), 1:Enable.<br>+**/<br>+ UINT8 PcieRpPmSci[6];<br>+<br>+/** Offset 0x0104 - PCIE Root Port Extended Sync<br>+ Enable/Disable PCIE Root Port Extended Sync. 0:Disable, 1:Enable(Default).<br>+**/<br>+ UINT8 PcieRpExtSync[6];<br>+<br>+/** Offset 0x010A - Transmitter Half Swing<br>+ Transmitter Half Swing Enable/Disable. 0:Disable, 1:Enable(Default).<br>+**/<br>+ UINT8 PcieRpTransmitterHalfSwing[6];<br>+<br>+/** Offset 0x0110 - ACS<br>+ Enable/Disable Access Control Services Extended Capability. 0:Disable, 1:Enable(Default).<br>+**/<br>+ UINT8 PcieRpAcsEnabled[6];<br>+<br>+/** Offset 0x0116 - Clock Request Support<br>+ Enable/Disable CLKREQ# Support. 0:Disable, 1:Enable(Default).<br>+**/<br>+ UINT8 PcieRpClkReqSupported[6];<br>+<br>+/** Offset 0x011C - Configure CLKREQ Number<br>+ Configure Root Port CLKREQ Number if CLKREQ is supported. Default=0x04, 0x05, 0x00,<br>+ 0x01, 0x02, 0x03.<br>+**/<br>+ UINT8 PcieRpClkReqNumber[6];<br>+<br>+/** Offset 0x0122 - CLKREQ# Detection<br>+ Enable/Disable CLKREQ# Detection Probe. 0: Disable(Default), 1: Enable.<br>+**/<br>+ UINT8 PcieRpClkReqDetect[6];<br>+<br>+/** Offset 0x0128 - Advanced Error Reporting<br>+ Enable/Disable Advanced Error Reporting. 0: Disable(Default), 1: Enable.<br>+**/<br>+ UINT8 AdvancedErrorReporting[6];<br>+<br>+/** Offset 0x012E - PME Interrupt<br>+ Enable/Disable PME Interrupt. 0: Disable(Default), 1: Enable.<br>+**/<br>+ UINT8 PmeInterrupt[6];<br>+<br>+/** Offset 0x0134 - URR<br>+ PCI Express Unsupported Request Reporting Enable/Disable. 0:Disable(Default), 1:Enable.<br>+**/<br>+ UINT8 UnsupportedRequestReport[6];<br>+<br>+/** Offset 0x013A - FER<br>+ PCI Express Device Fatal Error Reporting Enable/Disable. 0:Disable(Default), 1:Enable.<br>+**/<br>+ UINT8 FatalErrorReport[6];<br>+<br>+/** Offset 0x0140 - NFER<br>+ PCI Express Device Non-Fatal Error Reporting Enable/Disable. 0:Disable(Default), 1:Enable.<br>+**/<br>+ UINT8 NoFatalErrorReport[6];<br>+<br>+/** Offset 0x0146 - CER<br>+ PCI Express Device Correctable Error Reporting Enable/Disable. 0:Disable(Default), 1:Enable.<br>+**/<br>+ UINT8 CorrectableErrorReport[6];<br>+<br>+/** Offset 0x014C - SEFE<br>+ Root PCI Express System Error on Fatal Error Enable/Disable. 0:Disable(Default), 1:Enable.<br>+**/<br>+ UINT8 SystemErrorOnFatalError[6];<br>+<br>+/** Offset 0x0152 - SENFE<br>+ Root PCI Express System Error on Non-Fatal Error Enable/Disable. 0:Disable(Default), 1:Enable.<br>+**/<br>+ UINT8 SystemErrorOnNonFatalError[6];<br>+<br>+/** Offset 0x0158 - SECE<br>+ Root PCI Express System Error on Correctable Error Enable/Disable. 0:Disable(Default), 1:Enable.<br>+**/<br>+ UINT8 SystemErrorOnCorrectableError[6];<br>+<br>+/** Offset 0x015E - PCIe Speed<br>+ Configure PCIe Speed. 0:Auto(Default), 1:Gen1, 2:Gen2, 3:Gen3.<br>+**/<br>+ UINT8 PcieRpSpeed[6];<br>+<br>+/** Offset 0x0164 - Physical Slot Number<br>+ Physical Slot Number for PCIE Root Port. Default=0x00, 0x01, 0x02, 0x03, 0x04, 0x05.<br>+**/<br>+ UINT8 PhysicalSlotNumber[6];<br>+<br>+/** Offset 0x016A - CTO<br>+ Enable/Disable PCI Express Completion Timer TO . 0:Disable(Default), 1:Enable.<br>+**/<br>+ UINT8 PcieRpCompletionTimeout[6];<br>+<br>+/** Offset 0x0170 - PTM Support<br>+ Enable/Disable PTM Support. 0:Disable(Default), 1:Enable.<br>+**/<br>+ UINT8 PtmEnable[6];<br>+<br>+/** Offset 0x0176 - ASPM<br>+ PCI Express Active State Power Management settings. 0:Disable, 1:L0s, 2:L1, 3:L0sL1,<br>+ 4:Auto(Default).<br>+**/<br>+ UINT8 PcieRpAspm[6];<br>+<br>+/** Offset 0x017C - L1 Substates<br>+ PCI Express L1 Substates settings. 0:Disable, 1:L1.1, 2:L1.2, 3:L1.1 & L1.2(Default).<br>+**/<br>+ UINT8 PcieRpL1Substates[6];<br>+<br>+/** Offset 0x0182 - PCH PCIe LTR<br>+ PCH PCIE Latency Reporting Enable/Disable. 0:Disable, 1:Enable(Default).<br>+**/<br>+ UINT8 PcieRpLtrEnable[6];<br>+<br>+/** Offset 0x0188 - PCIE LTR Lock<br>+ PCIE LTR Configuration Lock. 0:Disable(Default), 1:Enable.<br>+**/<br>+ UINT8 PcieRpLtrConfigLock[6];<br>+<br>+/** Offset 0x018E - PME_B0_S5 Disable bit<br>+ PME_B0_S5_DIS bit in the General PM Configuration B (GEN_PMCON_B) register. 0:Disable(Default), 1:Enable.<br>+ $EN_DIS<br>+**/<br>+ UINT8 PmeB0S5Dis;<br>+<br>+/** Offset 0x018F - PCI Clock Run<br>+ This member describes whether or not the PCI ClockRun feature of SC should be enabled.<br>+ 0:Disable(Default), 1:Enable.<br>+ $EN_DIS<br>+**/<br>+ UINT8 PciClockRun;<br>+<br>+/** Offset 0x0190 - Enable/Disable Timer 8254 Clock Setting<br>+ Enable/Disable Timer 8254 Clock. 0:Disable(Default), 1:Enable.<br>+ $EN_DIS<br>+**/<br>+ UINT8 Timer8254ClkSetting;<br>+<br>+/** Offset 0x0191 - Chipset SATA<br>+ Enables or Disables the Chipset SATA Controller. The Chipset SATA controller supports<br>+ the 2 black internal SATA ports (up to 3Gb/s supported per port). 0:Disable, 1:Enable(Default).<br>+ $EN_DIS<br>+**/<br>+ UINT8 EnableSata;<br>+<br>+/** Offset 0x0192 - SATA Mode Selection<br>+ Determines how SATA controller(s) operate. 0:AHCI(Default), 1:RAID.<br>+ 0:AHCI, 1:RAID<br>+**/<br>+ UINT8 SataMode;<br>+<br>+/** Offset 0x0193 - Aggressive LPM Support<br>+ Enable PCH to aggressively enter link power state. 0:Disable, 1:Enable(Default).<br>+ $EN_DIS<br>+**/<br>+ UINT8 SataSalpSupport;<br>+<br>+/** Offset 0x0194 - SATA Power Optimization<br>+ Enable SATA Power Optimizer on SC side. 0:Disable(Default), 1:Enable.<br>+ $EN_DIS<br>+**/<br>+ UINT8 SataPwrOptEnable;<br>+<br>+/** Offset 0x0195 - eSATA Speed Limit<br>+ Enable/Disable eSATA Speed Limit. 0:Disable(Default), 1:Enable.<br>+ $EN_DIS<br>+**/<br>+ UINT8 eSATASpeedLimit;<br>+<br>+/** Offset 0x0196 - SATA Speed Limit<br>+ SATA Speed Limit. 0h:ScSataSpeed(Default), 1h:1.5Gb/s(Gen 1), 2h:3Gb/s(Gen 2), 3h:6Gb/s(Gen 3).<br>+ 0:Default, 1: 1.5 Gb/s (Gen 1), 2: 3 Gb/s(Gen 2), 3: 6 Gb/s (Gen 1)<br>+**/<br>+ UINT8 SpeedLimit;<br>+<br>+/** Offset 0x0197<br>+**/<br>+ UINT8 UnusedUpdSpace2[1];<br>+<br>+/** Offset 0x0198 - SATA Port<br>+ Enable or Disable SATA Port. 0:Disable, 1:Enable(Default).<br>+**/<br>+ UINT8 SataPortsEnable[2];<br>+<br>+/** Offset 0x019A - SATA Port DevSlp<br>+ Enable/Disable SATA Port DevSlp. Board rework for LP needed before enable. 0:Disable(Default), 1:Enable.<br>+**/<br>+ UINT8 SataPortsDevSlp[2];<br>+<br>+/** Offset 0x019C - SATA Port HotPlug<br>+ Enable/Disable SATA Port Hotplug . 0:Disable(Default), 1:Enable.<br>+**/<br>+ UINT8 SataPortsHotPlug[2];<br>+<br>+/** Offset 0x019E - Mechanical Presence Switch<br>+ Controls reporting if this port has an Mechanical Presence Switch.\n<br>+ Note:Requires hardware support. 0:Disable, 1:Enable(Default).<br>+**/<br>+ UINT8 SataPortsInterlockSw[2];<br>+<br>+/** Offset 0x01A0 - External SATA Ports<br>+ Enable/Disable External SATA Ports. 0:Disable(Default), 1:Enable.<br>+**/<br>+ UINT8 SataPortsExternal[2];<br>+<br>+/** Offset 0x01A2 - Spin Up Device<br>+ Enable/Disable device spin up at boot on selected Sata Ports. 0:Disable(Default), 1:Enable.<br>+**/<br>+ UINT8 SataPortsSpinUp[2];<br>+<br>+/** Offset 0x01A4 - SATA Solid State<br>+ Identify the SATA port is connected to Solid State Drive or Hard Disk Drive. 0:Hard<br>+ Disk Drive(Default), 1:Solid State Drive.<br>+**/<br>+ UINT8 SataPortsSolidStateDrive[2];<br>+<br>+/** Offset 0x01A6 - DITO Configuration<br>+ Enable/Disable DITO Configuration. 0:Disable(Default), 1:Enable.<br>+**/<br>+ UINT8 SataPortsEnableDitoConfig[2];<br>+<br>+/** Offset 0x01A8 - DM Value<br>+ DM Value. 0:Minimum, 0x0F:Maximum(Default).<br>+**/<br>+ UINT8 SataPortsDmVal[2];<br>+<br>+/** Offset 0x01AA<br>+**/<br>+ UINT8 UnusedUpdSpace3[2];<br>+<br>+/** Offset 0x01AC - DITO Value<br>+ DEVSLP Idle Timeout Value. 0:Minimum, 0x03FF:Maximum, 0x0271(Default).<br>+**/<br>+ UINT16 SataPortsDitoVal[2];<br>+<br>+/** Offset 0x01B0 - Subsystem Vendor ID<br>+ Subsystem Vendor ID. 0x8086(Default).<br>+**/<br>+ UINT16 SubSystemVendorId;<br>+<br>+/** Offset 0x01B2 - Subsystem ID<br>+ Subsystem ID. 0x7270(Default).<br>+**/<br>+ UINT16 SubSystemId;<br>+<br>+/** Offset 0x01B4 - CRIDSettings<br>+ PMC CRID setting. 0:Disable(Default), 1:CRID_1, 2:CRID_2, 3:CRID_3.<br>+**/<br>+ UINT8 CRIDSettings;<br>+<br>+/** Offset 0x01B5 - ResetSelect<br>+ ResetSelect. 0x6:warm reset(Default), 0xE:cold reset.<br>+**/<br>+ UINT8 ResetSelect;<br>+<br>+/** Offset 0x01B6 - SD Card Support (D27:F0)<br>+ Enable/Disable SD Card Support. 0:Disable, 1:Enable(Default).<br>+ $EN_DIS<br>+**/<br>+ UINT8 SdcardEnabled;<br>+<br>+/** Offset 0x01B7 - SeMMC Support (D28:F0)<br>+ Enable/Disable eMMC Support. 0:Disable, 1:Enable(Default).<br>+ $EN_DIS<br>+**/<br>+ UINT8 eMMCEnabled;<br>+<br>+/** Offset 0x01B8 - eMMC Max Speed<br>+ Select the eMMC max Speed allowed. 0:HS400(Default), 1:HS200, 2:DDR50.<br>+ 0:HS400, 1: HS200, 2:DDR50<br>+**/<br>+ UINT8 eMMCHostMaxSpeed;<br>+<br>+/** Offset 0x01B9 - UFS Support (D29:F0)<br>+ Enable/Disable SDIO Support. 0:Disable, 1:Enable(Default).<br>+ $EN_DIS<br>+**/<br>+ UINT8 UfsEnabled;<br>+<br>+/** Offset 0x01BA - SDIO Support (D30:F0)<br>+ Enable/Disable SDIO Support. 0:Disable, 1:Enable(Default).<br>+ $EN_DIS<br>+**/<br>+ UINT8 SdioEnabled;<br>+<br>+/** Offset 0x01BB - GPP Lock Feature<br>+ Enable/Disable GPP lock. 0:Disable(Default), 1:Enable.<br>+ $EN_DIS<br>+**/<br>+ UINT8 GppLock;<br>+<br>+/** Offset 0x01BC - Serial IRQ<br>+ Enable/Disable Serial IRQ. 0:Disable, 1:Enable(Default).<br>+ $EN_DIS<br>+**/<br>+ UINT8 SirqEnable;<br>+<br>+/** Offset 0x01BD - Serial IRQ Mode<br>+ Serial IRQ Mode Selection. 0:Quiet mode(Default), 1:Continuous mode.<br>+ $EN_DIS<br>+**/<br>+ UINT8 SirqMode;<br>+<br>+/** Offset 0x01BE - Start Frame Pulse Width<br>+ Start Frame Pulse Width Value. 0:ScSfpw4Clk(Default), 1: ScSfpw6Clk, 2:ScSfpw8Clk.<br>+ 0:ScSfpw4Clk, 1:ScSfpw6Clk, 2:ScSfpw8Clk<br>+**/<br>+ UINT8 StartFramePulse;<br>+<br>+/** Offset 0x01BF - Enable SMBus<br>+ Enable/disable SMBus controller. 0:Disable, 1:Enable(Default).<br>+ $EN_DIS<br>+**/<br>+ UINT8 SmbusEnable;<br>+<br>+/** Offset 0x01C0 - SMBus ARP Support<br>+ Enable/disable SMBus ARP Support. 0:Disable, 1:Enable(Default).<br>+ $EN_DIS<br>+**/<br>+ UINT8 ArpEnable;<br>+<br>+/** Offset 0x01C1<br>+**/<br>+ UINT8 UnusedUpdSpace4;<br>+<br>+/** Offset 0x01C2 - SMBus Table Elements<br>+ The number of elements in the Reserved SMBus Address Table. 0x0080(Default).<br>+**/<br>+ UINT16 NumRsvdSmbusAddresses;<br>+<br>+/** Offset 0x01C4 - Reserved SMBus Address Table<br>+ Array of addresses reserved for non-ARP-capable SMBus devices. 0x00(Default).<br>+**/<br>+ UINT8 RsvdSmbusAddressTable[128];<br>+<br>+/** Offset 0x0244 - XHCI Disable Compliance Mode<br>+ Options to disable XHCI Link Compliance Mode. Default is FALSE to not disable Compliance<br>+ Mode. Set TRUE to disable Compliance Mode. 0:FALSE(Default), 1:True.<br>+ $EN_DIS<br>+**/<br>+ UINT8 DisableComplianceMode;<br>+<br>+/** Offset 0x0245 - USB Per-Port Control<br>+ Control each of the USB ports enable/disable. 0:Disable(Default), 1:Enable.<br>+ $EN_DIS<br>+**/<br>+ UINT8 UsbPerPortCtl;<br>+<br>+/** Offset 0x0246 - xHCI Mode<br>+ Mode of operation of xHCI controller. 0:Disable, 1:Enable, 2:Auto(Default)<br>+ 0:Disable, 1:Enable, 2:Auto<br>+**/<br>+ UINT8 Usb30Mode;<br>+<br>+/** Offset 0x0247<br>+**/<br>+ UINT8 UnusedUpdSpace5[1];<br>+<br>+/** Offset 0x0248 - Enable USB2 ports<br>+ Enable/disable per USB2 ports. One byte for each port, byte0 for port0, byte1 for<br>+ port1, and so on. 0x01(Default).<br>+**/<br>+ UINT8 PortUsb20Enable[8];<br>+<br>+/** Offset 0x0250 - USB20 Over Current Pin<br>+ Over Current Pin number of USB 2.0 Port. 0x00(Default).<br>+**/<br>+ UINT8 PortUs20bOverCurrentPin[8];<br>+<br>+/** Offset 0x0258 - XDCI Support<br>+ Enable/Disable XDCI. 0:Disable, 1:PCI_Mode(Default), 2:ACPI_mode.<br>+ 0:Disable, 1:PCI_Mode, 2:ACPI_mode<br>+**/<br>+ UINT8 UsbOtg;<br>+<br>+/** Offset 0x0259 - Enable XHCI HSIC Support<br>+ Enable/Disable USB HSIC1. 0:Disable(Default), 1:Enable.<br>+ $EN_DIS<br>+**/<br>+ UINT8 HsicSupportEnable;<br>+<br>+/** Offset 0x025A - Enable USB3 ports<br>+ Enable/disable per USB3 ports. One byte for each port, byte0 for port0, byte1 for<br>+ port1, and so on. 0x01(Default).<br>+**/<br>+ UINT8 PortUsb30Enable[6];<br>+<br>+/** Offset 0x0260 - USB20 Over Current Pin<br>+ Over Current Pin number of USB 3.0 Port. 0x01(Default).<br>+**/<br>+ UINT8 PortUs30bOverCurrentPin[6];<br>+<br>+/** Offset 0x0266 - Enable XHCI SSIC Support<br>+ Enable/disable XHCI SSIC ports. One byte for each port, byte0 for port0, byte1 for<br>+ port1. 0x00(Default).<br>+**/<br>+ UINT8 SsicPortEnable[2];<br>+<br>+/** Offset 0x0268 - SSIC Dlane PowerGating<br>+ Enable/Disable SSIC Data lane Power Gating. 0:Disable, 1:Enable(Default).<br>+ $EN_DIS<br>+**/<br>+ UINT16 DlanePwrGating;<br>+<br>+/** Offset 0x026A - VT-d<br>+ Enable/Disable VT-d. 0:Disable(Default), 1:Enable.<br>+ $EN_DIS<br>+**/<br>+ UINT8 VtdEnable;<br>+<br>+/** Offset 0x026B - SMI Lock bit<br>+ Enable/Disable SMI_LOCK bit to prevent writes to the Global SMI Enable bit. 0:Disable,<br>+ 1:Enable(Default).<br>+ $EN_DIS<br>+**/<br>+ UINT8 LockDownGlobalSmi;<br>+<br>+/** Offset 0x026C - HDAudio Delay Timer<br>+ The delay timer after Azalia reset. 0x012C(Default).<br>+**/<br>+ UINT16 ResetWaitTimer;<br>+<br>+/** Offset 0x026E - RTC Lock Bits<br>+ Enable/Disable RTC Lock Bits. 0:Disable, 1:Enable(Default).<br>+ $EN_DIS<br>+**/<br>+ UINT8 RtcLock;<br>+<br>+/** Offset 0x026F - SATA Test Mode Selection<br>+ Enable/Disable SATA Test Mode. 0:Disable(Default), 1:Enable.<br>+ $EN_DIS<br>+**/<br>+ UINT8 SataTestMode;<br>+<br>+/** Offset 0x0270 - XHCI SSIC RATE<br>+ Set XHCI SSIC1 Rate to A Series or B Series. 1:A Series(Default), 2:B Series.<br>+**/<br>+ UINT8 SsicRate[2];<br>+<br>+/** Offset 0x0272 - SMBus Dynamic Power Gating<br>+ Enable/Disable SMBus dynamic power gating. 0:Disable(Default), 1:Enable.<br>+ $EN_DIS<br>+**/<br>+ UINT16 DynamicPowerGating;<br>+<br>+/** Offset 0x0274 - Max Snoop Latency<br>+ Latency Tolerance Reporting Max Snoop Latency. 0x0000(Default).<br>+**/<br>+ UINT16 PcieRpLtrMaxSnoopLatency[6];<br>+<br>+/** Offset 0x0280 - Snoop Latency Override<br>+ Snoop Latency Override for PCH PCIE. \n<br>+ Disabled:Disable override.\n<br>+ Manual:Manually enter override values.\n<br>+ Auto:Maintain default BIOS flow. 0:Disable, 1:Enable, 2:Auto(Default).<br>+**/<br>+ UINT8 PcieRpSnoopLatencyOverrideMode[6];<br>+<br>+/** Offset 0x0286<br>+**/<br>+ UINT8 UnusedUpdSpace6[2];<br>+<br>+/** Offset 0x0288 - Snoop Latency Value<br>+ LTR Snoop Latency value of PCH PCIE. 0:Minimum, 0x03FF:Maximum, 0x003C(Default).<br>+**/<br>+ UINT16 PcieRpSnoopLatencyOverrideValue[6];<br>+<br>+/** Offset 0x0294 - Snoop Latency Multiplier<br>+ LTR Snoop Latency Multiplier of PCH PCIE. 0:1ns, 1:32ns, 2:1024ns(Default), 3:32768ns,<br>+ 4:1048576ns, 5:33554432ns.<br>+**/<br>+ UINT8 PcieRpSnoopLatencyOverrideMultiplier[6];<br>+<br>+/** Offset 0x029A - Skip Multi-Processor Initialization<br>+ When this is skipped, boot loader must initialize processors before SilicionInit<br>+ API. 0: Initialize(Default), <b>1: Skip<br>+ $EN_DIS<br>+**/<br>+ UINT8 SkipMpInit;<br>+<br>+/** Offset 0x029B - DCI Auto Detect<br>+ Enable/disable DCI AUTO mode. Enabled(Default).<br>+ $EN_DIS<br>+**/<br>+ UINT8 DciAutoDetect;<br>+<br>+/** Offset 0x029C - Max Non-Snoop Latency<br>+ Latency Tolerance Reporting, Max Non-Snoop Latency. 0x0000(Default).<br>+**/<br>+ UINT16 PcieRpLtrMaxNonSnoopLatency[6];<br>+<br>+/** Offset 0x02A8 - Non Snoop Latency Override<br>+ Non Snoop Latency Override for PCH PCIE. \n<br>+ Disabled:Disable override.\n<br>+ Manual:Manually enter override values.\n<br>+ Auto: Maintain default BIOS flow. 0:Disable, 1:Enable, 2:Auto(Default).<br>+**/<br>+ UINT8 PcieRpNonSnoopLatencyOverrideMode[6];<br>+<br>+/** Offset 0x02AE - Halt and Lock TCO Timer<br>+ Halt and Lock the TCO Timer (Watchdog).<br>+ 0:No, 1:Yes (default)<br>+**/<br>+ UINT8 TcoTimerHaltLock;<br>+<br>+/** Offset 0x02AF - Power Button Override Period<br>+ specifies how long will PMC wait before initiating a global reset. 000b-4s(default),<br>+ 001b-6s, 010b-8s, 011b-10s, 100b-12s, 101b-14s.)<br>+ 0x0:4s, 0x1:6s, 0x2:8s, 0x3:10s, 0x4:12s, 0x5:14s<br>+**/<br>+ UINT8 PwrBtnOverridePeriod;<br>+<br>+/** Offset 0x02B0 - Non Snoop Latency Value<br>+ LTR Non Snoop Latency value of PCH PCIE. 0:Minimum, 0x03FF:Maximum, 0x003C(Default).<br>+**/<br>+ UINT16 PcieRpNonSnoopLatencyOverrideValue[6];<br>+<br>+/** Offset 0x02BC - Non Snoop Latency Multiplier<br>+ LTR Non Snoop Latency Multiplier of PCH PCIE. 0:1ns, 1:32ns, 2:1024ns(Default),<br>+ 3:32768ns, 4:1048576ns, 5:33554432ns.<br>+**/<br>+ UINT8 PcieRpNonSnoopLatencyOverrideMultiplier[6];<br>+<br>+/** Offset 0x02C2 - PCIE Root Port Slot Power Limit Scale<br>+ Specifies scale used for slot power limit value. 0x00(Default).<br>+**/<br>+ UINT8 PcieRpSlotPowerLimitScale[6];<br>+<br>+/** Offset 0x02C8 - PCIE Root Port Slot Power Limit Value<br>+ Specifies upper limit on power supplie by slot. 0x00(Default).<br>+**/<br>+ UINT8 PcieRpSlotPowerLimitValue[6];<br>+<br>+/** Offset 0x02CE - Power Button Native Mode Disable<br>+ Disable power button native mode, when 1, this will result in the PMC logic constantly<br>+ seeing the power button as de-asserted. 0 (default))<br>+ $EN_DIS<br>+**/<br>+ UINT8 DisableNativePowerButton;<br>+<br>+/** Offset 0x02CF - Power Button Debounce Mode<br>+ Enable interrupt when PWRBTN# is asserted. 0:Disabled, 1:Enabled(default)<br>+ $EN_DIS<br>+**/<br>+ UINT8 PowerButterDebounceMode;<br>+<br>+/** Offset 0x02D0 - SDIO_TX_CMD_DLL_CNTL<br>+ SDIO_TX_CMD_DLL_CNTL. 0x505(Default).<br>+**/<br>+ UINT32 SdioTxCmdCntl;<br>+<br>+/** Offset 0x02D4 - SDIO_TX_DATA_DLL_CNTL1<br>+ SDIO_TX_DATA_DLL_CNTL1. 0xE(Default).<br>+**/<br>+ UINT32 SdioTxDataCntl1;<br>+<br>+/** Offset 0x02D8 - SDIO_TX_DATA_DLL_CNTL2<br>+ SDIO_TX_DATA_DLL_CNTL2. 0x22272828(Default).<br>+**/<br>+ UINT32 SdioTxDataCntl2;<br>+<br>+/** Offset 0x02DC - SDIO_RX_CMD_DATA_DLL_CNTL1<br>+ SDIO_RX_CMD_DATA_DLL_CNTL1. 0x16161616(Default).<br>+**/<br>+ UINT32 SdioRxCmdDataCntl1;<br>+<br>+/** Offset 0x02E0 - SDIO_RX_CMD_DATA_DLL_CNTL2<br>+ SDIO_RX_CMD_DATA_DLL_CNTL2. 0x10000(Default).<br>+**/<br>+ UINT32 SdioRxCmdDataCntl2;<br>+<br>+/** Offset 0x02E4 - SDCARD_TX_CMD_DLL_CNTL<br>+ SDCARD_TX_CMD_DLL_CNTL. 0x505(Default).<br>+**/<br>+ UINT32 SdcardTxCmdCntl;<br>+<br>+/** Offset 0x02E8 - SDCARD_TX_DATA_DLL_CNTL1<br>+ SDCARD_TX_DATA_DLL_CNTL1. 0xA13(Default).<br>+**/<br>+ UINT32 SdcardTxDataCntl1;<br>+<br>+/** Offset 0x02EC - SDCARD_TX_DATA_DLL_CNTL2<br>+ SDCARD_TX_DATA_DLL_CNTL2. 0x24242828(Default).<br>+**/<br>+ UINT32 SdcardTxDataCntl2;<br>+<br>+/** Offset 0x02F0 - SDCARD_RX_CMD_DATA_DLL_CNTL1<br>+ SDCARD_RX_CMD_DATA_DLL_CNTL1. 0x73A3637(Default).<br>+**/<br>+ UINT32 SdcardRxCmdDataCntl1;<br>+<br>+/** Offset 0x02F4 - SDCARD_RX_STROBE_DLL_CNTL<br>+ SDCARD_RX_STROBE_DLL_CNTL. 0x0(Default).<br>+**/<br>+ UINT32 SdcardRxStrobeCntl;<br>+<br>+/** Offset 0x02F8 - SDCARD_RX_CMD_DATA_DLL_CNTL2<br>+ SDCARD_RX_CMD_DATA_DLL_CNTL2. 0x10000(Default).<br>+**/<br>+ UINT32 SdcardRxCmdDataCntl2;<br>+<br>+/** Offset 0x02FC - EMMC_TX_CMD_DLL_CNTL<br>+ EMMC_TX_CMD_DLL_CNTL. 0x505(Default).<br>+**/<br>+ UINT32 EmmcTxCmdCntl;<br>+<br>+/** Offset 0x0300 - EMMC_TX_DATA_DLL_CNTL1<br>+ EMMC_TX_DATA_DLL_CNTL1. 0xC11(Default).<br>+**/<br>+ UINT32 EmmcTxDataCntl1;<br>+<br>+/** Offset 0x0304 - EMMC_TX_DATA_DLL_CNTL2<br>+ EMMC_TX_DATA_DLL_CNTL2. 0x1C2A2927(Default).<br>+**/<br>+ UINT32 EmmcTxDataCntl2;<br>+<br>+/** Offset 0x0308 - EMMC_RX_CMD_DATA_DLL_CNTL1<br>+ EMMC_RX_CMD_DATA_DLL_CNTL1. 0x000D162F(Default).<br>+**/<br>+ UINT32 EmmcRxCmdDataCntl1;<br>+<br>+/** Offset 0x030C - EMMC_RX_STROBE_DLL_CNTL<br>+ EMMC_RX_STROBE_DLL_CNTL. 0x0a0a(Default).<br>+**/<br>+ UINT32 EmmcRxStrobeCntl;<br>+<br>+/** Offset 0x0310 - EMMC_RX_CMD_DATA_DLL_CNTL2<br>+ EMMC_RX_CMD_DATA_DLL_CNTL2. 0x1003b(Default).<br>+**/<br>+ UINT32 EmmcRxCmdDataCntl2;<br>+<br>+/** Offset 0x0314 - EMMC_MASTER_DLL_CNTL<br>+ EMMC_MASTER_DLL_CNTL. 0x001(Default).<br>+**/<br>+ UINT32 EmmcMasterSwCntl;<br>+<br>+/** Offset 0x0318 - PCIe Selectable De-emphasis<br>+ When the Link is operating at 5.0 GT/s speed, this bit selects the level of de-emphasis<br>+ for an Upstream component. 1b:-3.5 dB 0b:-6 dB. 0:Disable, 1:Enable(Default).<br>+**/<br>+ UINT8 PcieRpSelectableDeemphasis[6];<br>+<br>+/** Offset 0x031E - Monitor Mwait Enable<br>+ Enable/Disable Monitor Mwait. For Windows* OS, this should be Enabled. For Linux<br>+ based OS, this should be Disabled. 0:Disable, 1:Enable(Default).<br>+ $EN_DIS<br>+**/<br>+ UINT8 MonitorMwaitEnable;<br>+<br>+/** Offset 0x031F - Universal Audio Architecture compliance for DSP enabled system<br>+ 0: Not-UAA Compliant (Intel SST driver supported only), 1: UAA Compliant (HDA Inbox<br>+ driver or SST driver supported).<br>+ $EN_DIS<br>+**/<br>+ UINT8 HdAudioDspUaaCompliance;<br>+<br>+/** Offset 0x0320 - IRQ Interrupt Polarity Control<br>+ Set IRQ Interrupt Polarity Control to ITSS.IPC[0]~IPC[3]. 0:Active High, 1:Active Low<br>+**/<br>+ UINT32 IPC[4];<br>+<br>+/** Offset 0x0330 - Disable ModPHY dynamic power gate<br>+ Disable ModPHY dynamic power gate for the specific SATA port.<br>+**/<br>+ UINT8 SataPortsDisableDynamicPg[2];<br>+<br>+/** Offset 0x0332 - Init CPU during S3 resume<br>+ 0: Do not initialize CPU during S3 resume. 1: Initialize CPU during S3 resume.<br>+ $EN_DIS<br>+**/<br>+ UINT8 InitS3Cpu;<br>+<br>+/** Offset 0x0333 - SGX Epoch 0<br>+ SGX Epoch 0. 0x0(Default).<br>+**/<br>+ UINT64 SgxEpoch0;<br>+<br>+/** Offset 0x033B - SGX Epoch 1<br>+ SGX Epoch 1. 0x0(Default).<br>+**/<br>+ UINT64 SgxEpoch1;<br>+<br>+/** Offset 0x0343 - MicrocodePatchAddress<br>+ MicrocodePatchAddress. 0x0(Default).<br>+**/<br>+ UINT64 MicrocodePatchAddress;<br>+<br>+/** Offset 0x034B - CNVi Mode<br>+ Selects CNVi Mode. 0:Disable, 1:Auto(Default).<br>+ $EN_DIS<br>+**/<br>+ UINT8 CnviMode;<br>+<br>+/** Offset 0x034C - BT Interface<br>+ CNVi BT interface. 0:UART, 1:USB(Default).<br>+ $EN_DIS<br>+**/<br>+ UINT8 CnviBtInterface;<br>+<br>+/** Offset 0x034D - Disable Sx Wake<br>+ Enables/Disables wake from Sx . 0:No(Default), 1:Yes.<br>+ $EN_DIS<br>+**/<br>+ UINT8 DisableSxWake;<br>+<br>+/** Offset 0x034E - ModifyCrfGpios<br>+ Feature to Configure CRF Gpios Conditionally upon platform requirement, configuration<br>+ of GNSS and BtOnUart gpios will/will not be done based on this policy<br>+ $EN_DIS<br>+**/<br>+ UINT8 ModifyCrfGpios;<br>+<br>+/** Offset 0x034F - dGPU Hold Reset<br>+ dGPU Hold Reset GPIO information from GPIO community, Pin and Active<br>+**/<br>+ UINT8 HgDgpuHoldRst[8];<br>+<br>+/** Offset 0x0357 - dGPU Power Enable<br>+ dGPU power enable GPIO information from GPIO community, Pin and Active<br>+**/<br>+ UINT8 HgDgpuPwrEnable[8];<br>+<br>+/** Offset 0x035F - dGPU Delay after power enable<br>+ Delay for DGPU after Hold Reset if HG is enable : 0 : Minimum , 1000 : Maximum ,<br>+ 300 : Default<br>+ 0 : Minimum , 1000 : Maximum , 300 : Default<br>+**/<br>+ UINT16 HgDelayAfterPwrEn;<br>+<br>+/** Offset 0x0361 - dGPU Delay after hold reset<br>+ Delay for DGPU after Hold Reset if HG is enable : 0 : Minimum , 1000 : Maximum ,<br>+ 100 : Default<br>+ 0 : Minimum , 1000 : Maximum , 100 : Default<br>+**/<br>+ UINT16 HgDelayAfterHoldReset;<br>+<br>+/** Offset 0x0363 - HG Enable<br>+ Enables/Disables Hybrid Graphics . 0 : Disable(Default), 1 : Enable<br>+ 0x1:Enabled, 0x0:Disabled<br>+**/<br>+ UINT8 HgEnabled;<br>+<br>+/** Offset 0x0364 - PAVP ASMF<br>+ Enable/Disable PAVP ASMF 0:Disable, 1:Enable(Default).<br>+ $EN_DIS<br>+**/<br>+ UINT8 PavpAsmf;<br>+<br>+/** Offset 0x0365 - CpuS3ResumeMtrrDataSize<br>+ Size of S3 resume MTRR data.<br>+**/<br>+ UINT16 CpuS3ResumeMtrrDataSize;<br>+<br>+/** Offset 0x0367 - CpuS3ResumeMtrrData<br>+ Pointer CPU S3 Resume MTRR Data<br>+**/<br>+ UINT32 CpuS3ResumeMtrrData;<br>+<br>+/** Offset 0x036B - PAVP Auto TearDown Grace Period Enable<br>+ Enable/Disable PAVP Auto TearDown Grace Period 0:Disable, 1:Enable(Default).<br>+ $EN_DIS<br>+**/<br>+ UINT8 AutoTearDownGracePeriod;<br>+<br>+/** Offset 0x036C - SeC EndOfPost EnableDisable<br>+ Enable/Disable SeC EOPEnable 0:Disable, 1:Enable(Default).<br>+ $EN_DIS<br>+**/<br>+ UINT8 EndOfPostEnabled;<br>+<br>+/** Offset 0x036D - EnableDigitalThermalSensor EnableDisable<br>+ Enable/Disable EnableDigitalThermalSensor 0:Disable(Default), 1:Enable.<br>+ $EN_DIS<br>+**/<br>+ UINT8 EnableDigitalThermalSensor;<br>+<br>+/** Offset 0x036E - PNP Mode<br>+ Select PNP Mode. 0:Disable,1:Power,2:Performance,3:Power&Performance<br>+ 0:Disable,1:Power,2:Performance,3:Power&Performance(default)<br>+**/<br>+ UINT8 PnpSettings;<br>+<br>+/** Offset 0x036F - OsBoot EnableDisable<br>+ Select OsBoot. 1:EMMC boot, 0:HardDisk boot<br>+ 1:EMMC boot, 1:HardDisk boot<br>+**/<br>+ UINT8 OsBoot;<br>+<br>+/** Offset 0x0370 - AP threads Idle Manner<br>+ AP threads Idle Manner for waiting signal to run 1:HALT loop 2:MWAIT loop 3:RUN lOOP<br>+ $EN_DIS<br>+**/<br>+ UINT8 ApIdleManner;<br>+<br>+/** Offset 0x0371<br>+**/<br>+ UINT8 ReservedFspsUpd[3];<br>+} FSP_S_CONFIG;<br>+<br>+/** Fsp S Test Configuration<br>+**/<br>+typedef struct {<br>+<br>+/** Offset 0x0374<br>+**/<br>+ UINT32 Signature;<br>+<br>+/** Offset 0x0378<br>+**/<br>+ UINT8 ReservedFspsTestUpd[12];<br>+} FSP_S_TEST_CONFIG;<br>+<br>+/** Fsp S Restricted Configuration<br>+**/<br>+typedef struct {<br>+<br>+/** Offset 0x0384<br>+**/<br>+ UINT32 Signature;<br>+<br>+/** Offset 0x0388 - Selective enable SGX<br>+ Selective enable SGX. 0xFFFF(Default).<br>+**/<br>+ UINT16 SelectiveEnableSgx;<br>+<br>+/** Offset 0x038A - SGX debug mode<br>+ Select SGX mode. 0:Disable(default), 1:Enable<br>+ 0:Disable(default), 1:Enable<br>+**/<br>+ UINT8 SgxDebugMode;<br>+<br>+/** Offset 0x038B - SGX Launch Control Policy Mode<br>+ Select Launch Control Policy Mode. 0:Intel - Default, 1:Per-boot Select mode(default)<br>+ 0:Intel locked , 1:Unlocked mode(default) , 2: Locked mode<br>+**/<br>+ UINT8 SgxLcp;<br>+<br>+/** Offset 0x038C - LE KeyHash0<br>+ LE KeyHash0. 0x0(Default).<br>+**/<br>+ UINT64 SgxLePubKeyHash0;<br>+<br>+/** Offset 0x0394 - LE KeyHash1<br>+ LE KeyHash1. 0x0(Default).<br>+**/<br>+ UINT64 SgxLePubKeyHash1;<br>+<br>+/** Offset 0x039C - LE KeyHash2<br>+ LE KeyHash2. 0x0(Default).<br>+**/<br>+ UINT64 SgxLePubKeyHash2;<br>+<br>+/** Offset 0x03A4 - LE KeyHash3<br>+ LE KeyHash3. 0x0(Default).<br>+**/<br>+ UINT64 SgxLePubKeyHash3;<br>+<br>+/** Offset 0x03AC<br>+**/<br>+ UINT8 ReservedFspsRestrictedUpd[2];<br>+} FSP_S_RESTRICTED_CONFIG;<br>+<br>+/** Fsp S UPD Configuration<br>+**/<br>+typedef struct {<br>+<br>+/** Offset 0x0000<br>+**/<br>+ FSP_UPD_HEADER FspUpdHeader;<br>+<br>+/** Offset 0x0020<br>+**/<br>+ FSP_S_CONFIG FspsConfig;<br>+<br>+/** Offset 0x0374<br>+**/<br>+ FSP_S_TEST_CONFIG FspsTestConfig;<br>+<br>+/** Offset 0x0384<br>+**/<br>+ FSP_S_RESTRICTED_CONFIG FspsRestrictedConfig;<br>+<br>+/** Offset 0x03AE<br>+**/<br>+ UINT16 UpdTerminator;<br>+} FSPS_UPD;<br>+<br>+#pragma pack()<br>+<br>+#endif<br></pre><p>To view, visit <a href="https://review.coreboot.org/20673">change 20673</a>. To unsubscribe, visit <a href="https://review.coreboot.org/settings">settings</a>.</p><div itemscope itemtype="http://schema.org/EmailMessage"><div itemscope itemprop="action" itemtype="http://schema.org/ViewAction"><link itemprop="url" href="https://review.coreboot.org/20673"/><meta itemprop="name" content="View Change"/></div></div>
<div style="display:none"> Gerrit-Project: coreboot </div>
<div style="display:none"> Gerrit-Branch: master </div>
<div style="display:none"> Gerrit-MessageType: newchange </div>
<div style="display:none"> Gerrit-Change-Id: I8e313a2b854e60b1ad8a5c6e080641e323de56a8 </div>
<div style="display:none"> Gerrit-Change-Number: 20673 </div>
<div style="display:none"> Gerrit-PatchSet: 1 </div>
<div style="display:none"> Gerrit-Owner: Ravishankar Sarawadi <ravishankar.sarawadi@intel.com> </div>