<p>V Sowmya has uploaded this change for <strong>review</strong>.</p><p><a href="https://review.coreboot.org/20663">View Change</a></p><pre style="font-family: monospace,monospace; white-space: pre-wrap;">mb/google/kblrvp: Add camera devices power sequencing through ACPI power resources<br><br>This patch controls the camera devices power through ACPI power resource.<br>* Add Opregions for PMIC1 and PMIC2,<br> * TI_PMIC_POWER_OPREGION<br> * TI_PMIC_VR_VAL_OPREGION<br> * TI_PMIC_CLK_OPREGION<br> * TI_PMIC_CLK_FREQ_OPREGION<br>* Add power resources for sensors and VCM,<br> * OVTH for CAM0<br> * OVFI for CAM1<br> * VCMP for VCM<br>* Implement _ON and _OFF methods for sensor and VCM module's power on<br>and power off sequences.<br><br>BUG=none<br>BRANCH=none<br>TEST=Build and boot kblrvp. Dump and verify that the generated DSDT table<br>has the required entries. Verified that sensor probe is successfull.<br><br>Change-Id: I02c4784ab3f4d6e1f0e657ad50b727ff11da8b9c<br>Signed-off-by: V Sowmya <v.sowmya@intel.com><br>---<br>M src/mainboard/intel/kblrvp/acpi/mipi_camera.asl<br>1 file changed, 696 insertions(+), 0 deletions(-)<br><br></pre><pre style="font-family: monospace,monospace; white-space: pre-wrap;">git pull ssh://review.coreboot.org:29418/coreboot refs/changes/63/20663/1</pre><pre style="font-family: monospace,monospace; white-space: pre-wrap;">diff --git a/src/mainboard/intel/kblrvp/acpi/mipi_camera.asl b/src/mainboard/intel/kblrvp/acpi/mipi_camera.asl<br>index d7534fe..7ec58bd 100644<br>--- a/src/mainboard/intel/kblrvp/acpi/mipi_camera.asl<br>+++ b/src/mainboard/intel/kblrvp/acpi/mipi_camera.asl<br>@@ -27,13 +27,358 @@<br> Return (0x0F)<br> }<br> <br>+ /* Marks the availability of all the operation regions */<br>+ Name (AVP1, Zero)<br>+ Name (AVGP, Zero)<br>+ Name (AVB0, Zero)<br>+ Name (AVB1, Zero)<br>+ Name (AVB2, Zero)<br>+ Name (AVB3, Zero)<br>+ Method (_REG, 2, NotSerialized)<br>+ {<br>+ If (LEqual (Arg0, 0x08))<br>+ {<br>+ /* Marks the availability of GeneralPurposeIO<br>+ * 0x08: opregion space for GeneralPurposeIO<br>+ */<br>+ Store (Arg1, AVGP)<br>+ }<br>+ If (LEqual (Arg0, 0xB0))<br>+ {<br>+ /* Marks the availability of<br>+ * TI_PMIC_POWER_OPREGION_ID */<br>+ Store (Arg1, AVB0)<br>+ }<br>+ If (LEqual (Arg0, 0xB1))<br>+ {<br>+ /* Marks the availability of<br>+ * TI_PMIC_VR_VAL_OPREGION_ID */<br>+ Store (Arg1, AVB1)<br>+ }<br>+ If (LEqual (Arg0, 0xB2))<br>+ {<br>+ /* Marks the availability of<br>+ * TI_PMIC_CLK_OPREGION_ID */<br>+ Store (Arg1, AVB2)<br>+ }<br>+ If (LEqual (Arg0, 0xB3))<br>+ {<br>+ /* Marks the availability of<br>+ * TI_PMIC_CLK_FREQ_OPREGION_ID */<br>+ Store (Arg1, AVB3)<br>+ }<br>+ If (LAnd (AVGP, LAnd (LAnd (AVB0, AVB1),<br>+ LAnd(AVB2, AVB3))))<br>+ {<br>+ /* Marks the availability of all opregions */<br>+ Store (1, AVP1)<br>+ }<br>+ Else<br>+ {<br>+ Store (0, AVP1)<br>+ }<br>+ }<br>+<br>+ OperationRegion (GPOP, GeneralPurposeIo, 0, 0x2)<br> Name (_CRS, ResourceTemplate ()<br> {<br> I2cSerialBus (0x004D, ControllerInitiated, 0x00061A80,<br> AddressingMode7Bit, "\\_SB.PCI0.I2C2",<br> 0x00, ResourceConsumer, ,<br> )<br>+ /* GPIO.9 is XSHUTDOWN pin for world facing camera */<br>+ GpioIo (Exclusive, PullDefault, 0x0000, 0x0000,<br>+ IoRestrictionOutputOnly, "\\_SB.PCI0.I2C2.PMIC",<br>+ 0x00, ResourceConsumer,,)<br>+ {<br>+ 9<br>+ }<br> })<br>+<br>+ /* PMIC operation regions */<br>+ /* 0xB0: TI_PMIC_POWER_OPREGION_ID<br>+ * VSIO: Sensor IO LDO output<br>+ * VCMC: VCM LDO output<br>+ * VAX1: Auxiliary LDO1 output<br>+ * VAX2: Auxiliary LDO2 output<br>+ * VACT: Analog LDO output<br>+ * VDCT: Core buck output<br>+ */<br>+ OperationRegion (PWR1, 0xB0, Zero, 0x0100)<br>+ Field (PWR1, DWordAcc, NoLock, Preserve)<br>+ {<br>+ VSIO, 32,<br>+ VCMC, 32,<br>+ VAX1, 32,<br>+ VAX2, 32,<br>+ VACT, 32,<br>+ VDCT, 32,<br>+ }<br>+<br>+ /* 0xB1: TI_PMIC_VR_VAL_OPREGION_ID<br>+ * SIOV: VSIO VR voltage value<br>+ * IOVA: VIO VR voltage value<br>+ * VCMV: VCM VR voltage value<br>+ * AX1V: Auxiliary LDO1 VR voltage value<br>+ * AX2V: Auxiliary LDO2 VR voltage value<br>+ * ACVA: Analog LDO VR voltage<br>+ * DCVA: Core buck VR volatage<br>+ */<br>+ OperationRegion (PWR2, 0xB1, Zero, 0x0100)<br>+ Field (PWR2, DWordAcc, NoLock, Preserve)<br>+ {<br>+ SIOV, 32,<br>+ IOVA, 32,<br>+ VCMV, 32,<br>+ AX1V, 32,<br>+ AX2V, 32,<br>+ ACVA, 32,<br>+ DCVA, 32,<br>+ }<br>+<br>+ /* 0xB2: TI_PMIC_CLK_OPREGION_ID<br>+ * PCTL: PLL control register<br>+ * PCT2: PLL control 2 register<br>+ * CFG1: Clock configuration 1 register<br>+ * CFG2: Clock configuration 2 register<br>+ */<br>+ OperationRegion (CLKC, 0xB2, Zero, 0x0100)<br>+ Field (CLKC, DWordAcc, NoLock, Preserve)<br>+ {<br>+ PCTL, 32,<br>+ PCT2, 32,<br>+ CFG1, 32,<br>+ CFG2, 32,<br>+ }<br>+<br>+ /* 0xB3: TI_PMIC_CLK_FREQ_OPREGION_ID<br>+ * PDV2: PLL output divider for HCLK_B<br>+ * BODI: PLL output divider for boost clock<br>+ * BUDI: PLL output divider for buck clock<br>+ * PSWR: PLL reference clock setting<br>+ * XTDV: Reference crystal divider<br>+ * PLDV: PLL feedback divider<br>+ * PODV: PLL output divider for HCLK_A<br>+ */<br>+ OperationRegion (CLKF, 0xB3, Zero, 0x0100)<br>+ Field (CLKF, DWordAcc, NoLock, Preserve)<br>+ {<br>+ PDV2, 32,<br>+ BODI, 32,<br>+ BUDI, 32,<br>+ PSWR, 32,<br>+ XTDV, 32,<br>+ PLDV, 32,<br>+ PODV, 32,<br>+ }<br>+<br>+ Mutex (MUTC, 0)<br>+ Method (CLKE, 0, Serialized) {<br>+ /* save Acquire result so we can check for<br>+ Mutex acquired */<br>+ Store (Acquire (MUTC, 1000), Local0)<br>+ /* check for Mutex acquired */<br>+ If (LEqual (Local0, Zero)) {<br>+ /* Set boost clock divider */<br>+ BODI = 3<br>+ /* Set buck clock divider */<br>+ BUDI = 2<br>+ /* Set the PLL_REF_CLK cyles */<br>+ PSWR = 19<br>+ /* Set the reference crystal divider */<br>+ XTDV = 170<br>+ /* Set PLL feedback divider */<br>+ PLDV = 32<br>+ /* Set PLL output divider for HCLK_A */<br>+ PODV = 1<br>+ /* Enable HCLK_A clock.<br>+ * CFG1: output selection for HCLK_A.<br>+ * CFG2: set drive strength for HCLK_A.<br>+ */<br>+ CFG2 = 1<br>+ CFG1 = 2<br>+ /* Enable PLL output, crystal oscillator<br>+ * input capacitance control and set<br>+ * Xtal oscillator as clock source.<br>+ */<br>+ PCTL = 209<br>+ Sleep(1)<br>+ Release (MUTC)<br>+ }<br>+ }<br>+<br>+ Method (CLKD, 0, Serialized) {<br>+ /* save Acquire result so we can check for<br>+ Mutex acquired */<br>+ Store (Acquire (MUTC, 1000), Local0)<br>+ /* check for Mutex acquired */<br>+ If (LEqual (Local0, Zero)) {<br>+ BODI = 0<br>+ BUDI = 0<br>+ PSWR = 0<br>+ XTDV = 0<br>+ PLDV = 0<br>+ PODV = 0<br>+ /* Disable HCLK_A clock */<br>+ CFG2 = 0<br>+ CFG1 = 0<br>+ PCTL = 0<br>+ Release (MUTC)<br>+ }<br>+ }<br>+<br>+ /* Reference count for VSIO */<br>+ Mutex (MUTV, 0)<br>+ Name (VSIC, 0)<br>+ Method (DOVD, 1, Serialized) {<br>+ /* Save Acquire result so we can check for<br>+ Mutex acquired */<br>+ Store (Acquire (MUTV, 1000), Local0)<br>+ /* Check for Mutex acquired */<br>+ If (LEqual (Local0, Zero)) {<br>+ /* Turn off VSIO */<br>+ If (LEqual (Arg0, Zero)) {<br>+ /* Decrement only if VSIC > 0 */<br>+ if (LGreater (VSIC, 0)) {<br>+ Decrement (VSIC)<br>+ If (LEqual (VSIC, Zero)) {<br>+ VSIO = 0<br>+ }<br>+ }<br>+ } ElseIf (LEqual (Arg0, 1)) {<br>+ /* Increment only if VSIC < 2 */<br>+ If (LLess (VSIC, 2)) {<br>+ /* Turn on VSIO */<br>+ If (LEqual (VSIC, Zero)) {<br>+ VSIO = 3<br>+ }<br>+ Increment (VSIC)<br>+ }<br>+ }<br>+<br>+ Release (MUTV)<br>+ }<br>+ }<br>+<br>+ /* Power resource methods for CAM0 */<br>+ PowerResource (OVTH, 0, 0) {<br>+ Name (STA, 0)<br>+ Method (_ON, 0, Serialized) {<br>+ If (LEqual (AVP1, 1)) {<br>+ If (LEqual (STA, 0)) {<br>+ /* Enable VSIO regulator +<br>+ daisy chain */<br>+ DOVD(1)<br>+<br>+ if (LNotEqual (IOVA, 52)) {<br>+ /* Set VSIO value as<br>+ 1.8006 V */<br>+ IOVA = 52<br>+ }<br>+ if (LNotEqual (SIOV, 52)) {<br>+ /* Set VSIO value as<br>+ 1.8006 V */<br>+ SIOV = 52<br>+ }<br>+ Sleep(3)<br>+<br>+ VACT = 1<br>+ if (LNotEqual (ACVA, 109)) {<br>+ /* Set ANA at 2.8152V */<br>+ ACVA = 109<br>+ }<br>+ Sleep(3)<br>+<br>+ \_SB.PCI0.I2C2.PMIC.CLKE()<br>+<br>+ VDCT = 1<br>+ if (LNotEqual (DCVA, 12)) {<br>+ /* Set CORE at 1.2V */<br>+ DCVA = 12<br>+ }<br>+ Sleep(3)<br>+ \_SB.PCI0.I2C2.CAM0.CRST(1)<br>+ Sleep(5)<br>+<br>+ STA = 1<br>+ }<br>+ }<br>+ }<br>+<br>+ Method (_OFF, 0, Serialized) {<br>+ If (LEqual (AVP1, 1)) {<br>+ If (LEqual (STA, 1)) {<br>+ Sleep(2)<br>+ \_SB.PCI0.I2C2.PMIC.CLKD()<br>+ Sleep(2)<br>+ \_SB.PCI0.I2C2.CAM0.CRST(0)<br>+ Sleep(3)<br>+ VDCT = 0<br>+ Sleep(3)<br>+ VACT = 0<br>+ Sleep(1)<br>+ DOVD(0)<br>+ Sleep(1)<br>+ }<br>+ }<br>+ STA = 0<br>+ }<br>+ Method (_STA, 0, NotSerialized) {<br>+ Return (STA)<br>+ }<br>+ }<br>+<br>+ /* Power resource methods for VCM */<br>+ PowerResource (VCMP, 0, 0) {<br>+ Name (STA, 0)<br>+ Method (_ON, 0, Serialized) {<br>+ If (LEqual (AVP1, 1)) {<br>+ If (LEqual (STA, 0)) {<br>+ /* Enable VSIO regulator +<br>+ daisy chain */<br>+ DOVD(1)<br>+ if (LNotEqual (IOVA, 52)) {<br>+ /* Set VSIO value as<br>+ 1.8006 V */<br>+ IOVA = 52<br>+ }<br>+ if (LNotEqual (SIOV, 52)) {<br>+ /* Set VSIO value as<br>+ 1.8006 V */<br>+ SIOV = 52<br>+ }<br>+ Sleep(3)<br>+<br>+ /* Enable VCM regulator */<br>+ VCMC = 1<br>+ if (LNotEqual (VCMV, 109)) {<br>+ /* Set VCM value at<br>+ 2.8152 V */<br>+ VCMV = 109<br>+ }<br>+ Sleep(3)<br>+<br>+ STA = 1<br>+ }<br>+ }<br>+ }<br>+<br>+ Method (_OFF, 0, Serialized) {<br>+ If (LEqual (AVP1, 1)) {<br>+ If (LEqual (STA, 1)) {<br>+ VCMC = 0 /* Disable regulator */<br>+ Sleep(1)<br>+ DOVD(0) /* Disable regulator */<br>+ Sleep(1)<br>+ STA = 0<br>+ }<br>+ }<br>+ }<br>+<br>+ Method (_STA, 0, NotSerialized) {<br>+ Return (STA)<br>+ }<br>+ }<br> }<br> <br> Device (CAM0)<br>@@ -57,6 +402,30 @@<br> 0x00, ResourceConsumer, ,<br> )<br> })<br>+<br>+ Field (\_SB.PCI0.I2C2.PMIC.GPOP, ByteAcc, NoLock, Preserve)<br>+ {<br>+ Connection<br>+ (<br>+ GpioIo (Exclusive, PullDefault, 0x0000, 0x0000,<br>+ IoRestrictionOutputOnly,<br>+ "\\_SB.PCI0.I2C2.PMIC", 0x00,<br>+ ResourceConsumer,,)<br>+ {<br>+ 9<br>+ }<br>+ ),<br>+ GRST, 1,<br>+ }<br>+<br>+ /* Set or clear GRST GPIO */<br>+ Method (CRST, 1, Serialized)<br>+ {<br>+ GRST = Arg0<br>+ }<br>+<br>+ Name (_PR0, Package () { ^^I2C2.PMIC.OVTH })<br>+ Name (_PR3, Package () { ^^I2C2.PMIC.OVTH })<br> <br> /* Port0 of CAM0 is connected to port0 of CIO2 device */<br> Name (_DSD, Package () {<br>@@ -138,6 +507,9 @@<br> 0x00, ResourceConsumer, ,<br> )<br> })<br>+<br>+ Name (_PR0, Package () { ^PMIC.VCMP })<br>+ Name (_PR3, Package () { ^PMIC.VCMP })<br> }<br> }<br> <br>@@ -155,13 +527,296 @@<br> Return (0x0F)<br> }<br> <br>+ /* Marks the availability of all the operation regions */<br>+ Name (AVP2, Zero)<br>+ Name (AVGP, Zero)<br>+ Name (AVB0, Zero)<br>+ Name (AVB1, Zero)<br>+ Name (AVB2, Zero)<br>+ Name (AVB3, Zero)<br>+ Method (_REG, 2, NotSerialized)<br>+ {<br>+ If (LEqual (Arg0, 0x08))<br>+ {<br>+ /* Marks the availability of GeneralPurposeIO<br>+ * 0x08: opregion space for GeneralPurposeIO<br>+ */<br>+ Store (Arg1, AVGP)<br>+ }<br>+ If (LEqual (Arg0, 0xB0))<br>+ {<br>+ /* Marks the availability of<br>+ * TI_PMIC_POWER_OPREGION_ID */<br>+ Store (Arg1, AVB0)<br>+ }<br>+ If (LEqual (Arg0, 0xB1))<br>+ {<br>+ /* Marks the availability of<br>+ * TI_PMIC_VR_VAL_OPREGION_ID */<br>+ Store (Arg1, AVB1)<br>+ }<br>+ If (LEqual (Arg0, 0xB2))<br>+ {<br>+ /* Marks the availability of<br>+ * TI_PMIC_CLK_OPREGION_ID */<br>+ Store (Arg1, AVB2)<br>+ }<br>+ If (LEqual (Arg0, 0xB3))<br>+ {<br>+ /* Marks the availability of<br>+ * TI_PMIC_CLK_FREQ_OPREGION_ID */<br>+ Store (Arg1, AVB3)<br>+ }<br>+ If (LAnd (AVGP, LAnd (LAnd (AVB0, AVB1),<br>+ LAnd(AVB2, AVB3))))<br>+ {<br>+ /* Marks the availability of all opregions */<br>+ Store (1, AVP2)<br>+ }<br>+ Else<br>+ {<br>+ Store (0, AVP2)<br>+ }<br>+ }<br>+<br>+ OperationRegion (GPOP, GeneralPurposeIo, 0, 0x2)<br> Name (_CRS, ResourceTemplate ()<br> {<br> I2cSerialBus (0x0049, ControllerInitiated, 0x00061A80,<br> AddressingMode7Bit, "\\_SB.PCI0.I2C3",<br> 0x00, ResourceConsumer, ,<br> )<br>+ /* GPIO.4 is AVDD pin for user facing camera */<br>+ GpioIo (Exclusive, PullDefault, 0x0000, 0x0000,<br>+ IoRestrictionOutputOnly, "\\_SB.PCI0.I2C3.PMIC",<br>+ 0x00, ResourceConsumer,,)<br>+ {<br>+ 4<br>+ }<br>+ /* GPIO.5 is XSHUTDOWN pin for user facing camera */<br>+ GpioIo (Exclusive, PullDefault, 0x0000, 0x0000,<br>+ IoRestrictionOutputOnly, "\\_SB.PCI0.I2C3.PMIC",<br>+ 0x00, ResourceConsumer,,)<br>+ {<br>+ 5<br>+ }<br> })<br>+<br>+ /* PMIC operation regions */<br>+ /* 0xB0: TI_PMIC_POWER_OPREGION_ID<br>+ * VSIO: Sensor IO LDO output<br>+ * VCMC: VCM LDO output<br>+ * VAX1: Auxiliary LDO1 output<br>+ * VAX2: Auxiliary LDO2 output<br>+ * VACT: Analog LDO output<br>+ * VDCT: Core buck output<br>+ */<br>+ OperationRegion (PWR1, 0xB0, Zero, 0x0100)<br>+ Field (PWR1, DWordAcc, NoLock, Preserve)<br>+ {<br>+ VSIO, 32,<br>+ VCMC, 32,<br>+ VAX1, 32,<br>+ VAX2, 32,<br>+ VACT, 32,<br>+ VDCT, 32,<br>+ }<br>+<br>+ /* 0xB1: TI_PMIC_VR_VAL_OPREGION_ID<br>+ * SIOV: VSIO VR voltage value<br>+ * IOVA: VIO VR voltage value<br>+ * VCMV: VCM VR voltage value<br>+ * AX1V: Auxiliary LDO1 VR voltage value<br>+ * AX2V: Auxiliary LDO2 VR voltage value<br>+ * ACVA: Analog LDO VR voltage<br>+ * DCVA: Core buck VR volatage<br>+ */<br>+ OperationRegion (PWR2, 0xB1, Zero, 0x0100)<br>+ Field (PWR2, DWordAcc, NoLock, Preserve)<br>+ {<br>+ SIOV, 32,<br>+ IOVA, 32,<br>+ VCMV, 32,<br>+ AX1V, 32,<br>+ AX2V, 32,<br>+ ACVA, 32,<br>+ DCVA, 32,<br>+ }<br>+<br>+ /* 0xB2: TI_PMIC_CLK_OPREGION_ID<br>+ * PCTL: PLL control register<br>+ * PCT2: PLL control 2 register<br>+ * CFG1: Clock configuration 1 register<br>+ * CFG2: Clock configuration 2 register<br>+ */<br>+ OperationRegion (CLKC, 0xB2, Zero, 0x0100)<br>+ Field (CLKC, DWordAcc, NoLock, Preserve)<br>+ {<br>+ PCTL, 32,<br>+ PCT2, 32,<br>+ CFG1, 32,<br>+ CFG2, 32,<br>+ }<br>+<br>+ /* 0xB3: TI_PMIC_CLK_FREQ_OPREGION_ID<br>+ * PDV2: PLL output divider for HCLK_B<br>+ * BODI: PLL output divider for boost clock<br>+ * BUDI: PLL output divider for buck clock<br>+ * PSWR: PLL reference clock setting<br>+ * XTDV: Reference crystal divider<br>+ * PLDV: PLL feedback divider<br>+ * PODV: PLL output divider for HCLK_A<br>+ */<br>+ OperationRegion (CLKF, 0xB3, Zero, 0x0100)<br>+ Field (CLKF, DWordAcc, NoLock, Preserve)<br>+ {<br>+ PDV2, 32,<br>+ BODI, 32,<br>+ BUDI, 32,<br>+ PSWR, 32,<br>+ XTDV, 32,<br>+ PLDV, 32,<br>+ PODV, 32,<br>+ }<br>+<br>+ Mutex (MUTC, 0)<br>+ Method (CLKE, 0, Serialized) {<br>+ /* save Acquire result so we can check for<br>+ Mutex acquired */<br>+ Store (Acquire (MUTC, 1000), Local0)<br>+ /* check for Mutex acquired */<br>+ If (LEqual (Local0, Zero)) {<br>+ /* Set boost clock divider */<br>+ BODI = 3<br>+ /* Set buck clock divider */<br>+ BUDI = 2<br>+ /* Set the PLL_REF_CLK cyles */<br>+ PSWR = 19<br>+ /* Set the reference crystal divider */<br>+ XTDV = 170<br>+ /* Set PLL feedback divider */<br>+ PLDV = 32<br>+ /* Set PLL output divider for HCLK_A */<br>+ PODV = 1<br>+ /* Enable HCLK_A clock.<br>+ * CFG1: output selection for HCLK_A.<br>+ * CFG2: set drive strength for HCLK_A.<br>+ */<br>+ CFG2 = 1<br>+ CFG1 = 2<br>+ /* Enable PLL output, crystal oscillator<br>+ * input capacitance control and set<br>+ * Xtal oscillator as clock source.<br>+ */<br>+ PCTL = 209<br>+ Sleep(1)<br>+ Release (MUTC)<br>+ }<br>+ }<br>+<br>+ Method (CLKD, 0, Serialized) {<br>+ /* save Acquire result so we can check for<br>+ Mutex acquired */<br>+ Store (Acquire (MUTC, 1000), Local0)<br>+ /* check for Mutex acquired */<br>+ If (LEqual (Local0, Zero)) {<br>+ BODI = 0<br>+ BUDI = 0<br>+ PSWR = 0<br>+ XTDV = 0<br>+ PLDV = 0<br>+ PODV = 0<br>+ /* Disable HCLK_A clock */<br>+ CFG2 = 0<br>+ CFG1 = 0<br>+ PCTL = 0<br>+ Release (MUTC)<br>+ }<br>+ }<br>+<br>+ /* Reference count for VSIO */<br>+ Mutex (MUTV, 0)<br>+ Name (VSIC, 0)<br>+ Method (DOVD, 1, Serialized) {<br>+ /* Save Acquire result so we can check for<br>+ Mutex acquired */<br>+ Store (Acquire (MUTV, 1000), Local0)<br>+ /* Check for Mutex acquired */<br>+ If (LEqual (Local0, Zero)) {<br>+ /* Turn off VSIO */<br>+ If (LEqual (Arg0, Zero)) {<br>+ VSIO = 0<br>+ } ElseIf (LEqual (Arg0, 1)) {<br>+ VSIO = 3<br>+ }<br>+ Release (MUTV)<br>+ }<br>+ }<br>+<br>+ /* Power resource methods for CAM1 */<br>+ PowerResource (OVFI, 0, 0) {<br>+ Name (STA, 0)<br>+ Method (_ON, 0, Serialized) {<br>+ If (LEqual (AVBL, 1)) {<br>+ If (LEqual (STA, 0)) {<br>+ /* Enable VSIO regulator +<br>+ daisy chain */<br>+ DOVD(1)<br>+<br>+ VAX2 = 1 /* Enable VAUX2 */<br>+<br>+ if (LNotEqual (AX2V, 52)) {<br>+ /* Set VAUX2 as<br>+ 1.8006 V */<br>+ AX2V = 52<br>+ }<br>+ Sleep(1)<br>+<br>+ \_SB.PCI0.I2C3.PMIC.CLKE()<br>+<br>+ VAX1 = 1 /* Enable VAUX1 */<br>+ if (LNotEqual (AX1V, 19)) {<br>+ /* Set VAUX1 as 1.2132V */<br>+ AX1V = 19<br>+ }<br>+ Sleep(3)<br>+<br>+ \_SB.PCI0.I2C3.CAM1.CGP4(1)<br>+ Sleep(3)<br>+<br>+ \_SB.PCI0.I2C3.CAM1.CGP5(1)<br>+ Sleep(5)<br>+ STA = 1<br>+ }<br>+ }<br>+ }<br>+<br>+ Method (_OFF, 0, Serialized) {<br>+ If (LEqual (AVBL, 1)) {<br>+ If (LEqual (STA, 1)) {<br>+ Sleep(2)<br>+ \_SB.PCI0.I2C3.PMIC.CLKD()<br>+ Sleep(2)<br>+ \_SB.PCI0.I2C3.CAM1.CGP5(0)<br>+ Sleep(3)<br>+ VAX1 = 0<br>+ Sleep(1)<br>+ \_SB.PCI0.I2C3.CAM1.CGP4(0)<br>+ Sleep(1)<br>+ VAX2 = 0<br>+ Sleep(1)<br>+ DOVD(0)<br>+ Sleep(1)<br>+<br>+ }<br>+ STA = 0<br>+ }<br>+ }<br>+<br>+ Method (_STA, 0, NotSerialized) {<br>+ Return (STA)<br>+ }<br>+ }<br> }<br> <br> Device (CAM1)<br>@@ -185,6 +840,47 @@<br> )<br> })<br> <br>+ Field (\_SB.PCI0.I2C3.PMIC.GPOP, ByteAcc, NoLock, Preserve)<br>+ {<br>+ Connection<br>+ (<br>+ GpioIo (Exclusive, PullDefault, 0x0000, 0x0000,<br>+ IoRestrictionOutputOnly,<br>+ "\\_SB.PCI0.I2C3.PMIC", 0x00,<br>+ ResourceConsumer,,)<br>+ {<br>+ 4<br>+ }<br>+ ),<br>+ GPO4, 1,<br>+ Connection<br>+ (<br>+ GpioIo (Exclusive, PullDefault, 0x0000, 0x0000,<br>+ IoRestrictionOutputOnly,<br>+ "\\_SB.PCI0.I2C3.PMIC", 0x00,<br>+ ResourceConsumer,,)<br>+ {<br>+ 5<br>+ }<br>+ ),<br>+ GPO5, 1,<br>+ }<br>+<br>+ /* Set or clear GPO4 GPIO */<br>+ Method (CGP4, 1, Serialized)<br>+ {<br>+ GPO4 = Arg0<br>+ }<br>+<br>+ /* Set or clear GPO5 GPIO */<br>+ Method (CGP5, 1, Serialized)<br>+ {<br>+ GPO5 = Arg0<br>+ }<br>+<br>+ Name (_PR0, Package () { ^^I2C3.PMIC.OVFI })<br>+ Name (_PR3, Package () { ^^I2C3.PMIC.OVFI })<br>+<br> /* Port0 of CAM1 is connected to port1 of CIO2 device */<br> Name (_DSD, Package () {<br> ToUUID ("dbb8e3e6-5886-4ba6-8795-1319f52a966b"),<br></pre><p>To view, visit <a href="https://review.coreboot.org/20663">change 20663</a>. To unsubscribe, visit <a href="https://review.coreboot.org/settings">settings</a>.</p><div itemscope itemtype="http://schema.org/EmailMessage"><div itemscope itemprop="action" itemtype="http://schema.org/ViewAction"><link itemprop="url" href="https://review.coreboot.org/20663"/><meta itemprop="name" content="View Change"/></div></div>
<div style="display:none"> Gerrit-Project: coreboot </div>
<div style="display:none"> Gerrit-Branch: master </div>
<div style="display:none"> Gerrit-MessageType: newchange </div>
<div style="display:none"> Gerrit-Change-Id: I02c4784ab3f4d6e1f0e657ad50b727ff11da8b9c </div>
<div style="display:none"> Gerrit-Change-Number: 20663 </div>
<div style="display:none"> Gerrit-PatchSet: 1 </div>
<div style="display:none"> Gerrit-Owner: V Sowmya <v.sowmya@intel.com> </div>