<p>Furquan Shaikh has uploaded this change for <strong>review</strong>.</p><p><a href="https://review.coreboot.org/20671">View Change</a></p><pre style="font-family: monospace,monospace; white-space: pre-wrap;">mainboard/google/poppy/variants/soraka: Define separate gpio tables<br><br>Now that soraka is starting to deviate from the baseboard w.r.t. gpio<br>settings, make a new copy of gpio table before we make any<br>variant-specific changes in it.<br><br>BUG=b:62240755,b:62322846<br>BRANCH=None<br>TEST=Verified with gpio_debug=1 in skylake/gpio.c that the gpio<br>configuration before and after this change remains same.<br><br>Change-Id: I448d18f18b63e9bfb739c518d599de3b9b602dc2<br>Signed-off-by: Furquan Shaikh <furquan@chromium.org><br>---<br>M src/mainboard/google/poppy/variants/soraka/Makefile.inc<br>A src/mainboard/google/poppy/variants/soraka/gpio.c<br>2 files changed, 432 insertions(+), 0 deletions(-)<br><br></pre><pre style="font-family: monospace,monospace; white-space: pre-wrap;">git pull ssh://review.coreboot.org:29418/coreboot refs/changes/71/20671/1</pre><pre style="font-family: monospace,monospace; white-space: pre-wrap;">diff --git a/src/mainboard/google/poppy/variants/soraka/Makefile.inc b/src/mainboard/google/poppy/variants/soraka/Makefile.inc<br>index 3a5a58d..d93e94b 100644<br>--- a/src/mainboard/google/poppy/variants/soraka/Makefile.inc<br>+++ b/src/mainboard/google/poppy/variants/soraka/Makefile.inc<br>@@ -9,3 +9,5 @@<br> SPD_SOURCES += samsung_dimm_K3QF3F30BM-AGCF # 0b0111<br> SPD_SOURCES += samsung_dimm_K3QF4F40BM-AGCF # 0b1000<br> SPD_SOURCES += samsung_dimm_K3QFAFA0CM-AGCF # 0b1001<br>+<br>+ramstage-y += gpio.c<br>diff --git a/src/mainboard/google/poppy/variants/soraka/gpio.c b/src/mainboard/google/poppy/variants/soraka/gpio.c<br>new file mode 100644<br>index 0000000..9d87e61<br>--- /dev/null<br>+++ b/src/mainboard/google/poppy/variants/soraka/gpio.c<br>@@ -0,0 +1,430 @@<br>+/*<br>+ * This file is part of the coreboot project.<br>+ *<br>+ * Copyright 2017 Google Inc.<br>+ *<br>+ * This program is free software; you can redistribute it and/or modify<br>+ * it under the terms of the GNU General Public License as published by<br>+ * the Free Software Foundation; version 2 of the License.<br>+ *<br>+ * This program is distributed in the hope that it will be useful,<br>+ * but WITHOUT ANY WARRANTY; without even the implied warranty of<br>+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the<br>+ * GNU General Public License for more details.<br>+ */<br>+<br>+#include <console/console.h><br>+#include <baseboard/gpio.h><br>+#include <baseboard/variants.h><br>+#include <commonlib/helpers.h><br>+<br>+/* Pad configuration in ramstage */<br>+/* Leave eSPI pins untouched from default settings */<br>+static const struct pad_config gpio_table[] = {<br>+ /* A0 : RCIN# ==> NC(TP41) */<br>+ PAD_CFG_NC(GPP_A0),<br>+ /* A1 : ESPI_IO0 */<br>+ /* A2 : ESPI_IO1 */<br>+ /* A3 : ESPI_IO2 */<br>+ /* A4 : ESPI_IO3 */<br>+ /* A5 : ESPI_CS# */<br>+ /* A6 : SERIRQ ==> NC(TP44) */<br>+ PAD_CFG_NC(GPP_A6),<br>+ /* A7 : PIRQA# ==> NC(TP29) */<br>+ PAD_CFG_NC(GPP_A7),<br>+ /* A8 : CLKRUN# ==> NC(TP45) */<br>+ PAD_CFG_NC(GPP_A8),<br>+ /* A9 : ESPI_CLK */<br>+ /* A10 : CLKOUT_LPC1 ==> NC */<br>+ PAD_CFG_NC(GPP_A10),<br>+ /* A11 : PME# ==> NC(TP67) */<br>+ PAD_CFG_NC(GPP_A11),<br>+ /* A12 : BM_BUSY# ==> NC */<br>+ PAD_CFG_NC(GPP_A12),<br>+ /* A13 : SUSWARN# ==> SUSWARN_L */<br>+ PAD_CFG_NF(GPP_A13, NONE, DEEP, NF1),<br>+ /* A14 : ESPI_RESET# */<br>+ /* A15 : SUSACK# ==> SUSACK_L */<br>+ PAD_CFG_NF(GPP_A15, NONE, DEEP, NF1),<br>+ /* A16 : SD_1P8_SEL ==> SD_PWR_1800_SEL */<br>+ PAD_CFG_NF(GPP_A16, NONE, DEEP, NF1),<br>+ /* A17 : SD_PWR_EN# ==> EN_SD_SOCKET_PWR_L */<br>+ PAD_CFG_NF(GPP_A17, NONE, DEEP, NF1),<br>+ /* A18 : ISH_GP0 ==> NC */<br>+ PAD_CFG_NC(GPP_A18),<br>+ /* A19 : ISH_GP1 ==> NC */<br>+ PAD_CFG_NC(GPP_A19),<br>+ /* A20 : ISH_GP2 ==> ACCEL_GYRO_INT_L */<br>+ PAD_CFG_GPI_APIC(GPP_A20, NONE, PLTRST),<br>+ /* A21 : ISH_GP3 ==> NC */<br>+ PAD_CFG_NC(GPP_A21),<br>+ /* A22 : ISH_GP4 ==> NC */<br>+ PAD_CFG_NC(GPP_A22),<br>+ /* A23 : ISH_GP5 ==> NC */<br>+ PAD_CFG_NC(GPP_A23),<br>+<br>+ /* B0 : CORE_VID0 ==> NC(TP42) */<br>+ PAD_CFG_NC(GPP_B0),<br>+ /* B1 : CORE_VID1 ==> NC(TP43) */<br>+ PAD_CFG_NC(GPP_B1),<br>+ /* B2 : VRALERT# ==> NC */<br>+ PAD_CFG_NC(GPP_B2),<br>+ /* B3 : CPU_GP2 ==> NC */<br>+ PAD_CFG_NC(GPP_B3),<br>+ /* B4 : CPU_GP3 ==> NC */<br>+ PAD_CFG_NC(GPP_B4),<br>+ /* B5 : SRCCLKREQ0# ==> NC */<br>+ PAD_CFG_NC(GPP_B5),<br>+ /* B6 : SRCCLKREQ1# ==> WLAN_PCIE_CLKREQ_L */<br>+ PAD_CFG_NF(GPP_B6, NONE, DEEP, NF1),<br>+ /* B7 : SRCCLKREQ2# ==> WWAN_PCIE_CLKREQ_L */<br>+ PAD_CFG_NF(GPP_B7, NONE, DEEP, NF1),<br>+ /* B8 : SRCCLKREQ3# ==> NC */<br>+ PAD_CFG_NC(GPP_B8),<br>+ /* B9 : SRCCLKREQ4# ==> NC */<br>+ PAD_CFG_NC(GPP_B9),<br>+ /* B10 : SRCCLKREQ5# ==> NC */<br>+ PAD_CFG_NC(GPP_B10),<br>+ /* B11 : EXT_PWR_GATE# ==> NC */<br>+ PAD_CFG_NC(GPP_B11),<br>+ /* B12 : SLP_S0# ==> SLP_S0_L_G */<br>+ PAD_CFG_NF(GPP_B12, NONE, DEEP, NF1),<br>+ /* B13 : PLTRST# ==> PLT_RST_L */<br>+ PAD_CFG_NF(GPP_B13, NONE, DEEP, NF1),<br>+ /* B14 : SPKR ==> NC */<br>+ PAD_CFG_NC(GPP_B14),<br>+#if IS_ENABLED(CONFIG_POPPY_USE_SPI_TPM)<br>+ /* B15 : GSPI0_CS# ==> PCH_SPI_H1_3V3_CS_L */<br>+ PAD_CFG_NF(GPP_B15, NONE, DEEP, NF1),<br>+ /* B16 : GSPI0_CLK ==> PCH_SPI_H1_3V3_CLK */<br>+ PAD_CFG_NF(GPP_B16, NONE, DEEP, NF1),<br>+ /* B17 : GSPI0_MISO ==> PCH_SPI_H1_3V3_MISO */<br>+ PAD_CFG_NF(GPP_B17, NONE, DEEP, NF1),<br>+ /* B18 : GSPI0_MOSI ==> PCH_SPI_H1_3V3_MOSI */<br>+ PAD_CFG_NF(GPP_B18, NONE, DEEP, NF1),<br>+#else<br>+ /* B15 : GSPI0_CS# ==> NC */<br>+ PAD_CFG_NC(GPP_B15),<br>+ /* B16 : GSPI0_CLK ==> NC */<br>+ PAD_CFG_NC(GPP_B16),<br>+ /* B17 : GSPI0_MISO ==> NC */<br>+ PAD_CFG_NC(GPP_B17),<br>+ /* B18 : GSPI0_MOSI ==> NC */<br>+ PAD_CFG_NC(GPP_B18),<br>+#endif<br>+ /* B19 : GSPI1_CS# ==> NC */<br>+ PAD_CFG_NC(GPP_B19),<br>+ /* B20 : GSPI1_CLK ==> NC */<br>+ PAD_CFG_NC(GPP_B20),<br>+ /* B21 : GSPI1_MISO ==> NC */<br>+ PAD_CFG_NC(GPP_B21),<br>+ /* B22 : GSPI1_MOSI ==> NC */<br>+ PAD_CFG_NC(GPP_B22),<br>+ /* B23 : SM1ALERT# ==> NC */<br>+ PAD_CFG_NC(GPP_B23),<br>+<br>+ /* C0 : SMBCLK ==> NC */<br>+ PAD_CFG_NC(GPP_C0),<br>+ /* C1 : SMBDATA ==> NC */<br>+ PAD_CFG_NC(GPP_C1),<br>+ /* C2 : SMBALERT# ==> NC */<br>+ PAD_CFG_NC(GPP_C2),<br>+ /* C3 : SML0CLK ==> NC */<br>+ PAD_CFG_NC(GPP_C3),<br>+ /* C4 : SML0DATA ==> NC */<br>+ PAD_CFG_NC(GPP_C4),<br>+ /* C5 : SML0ALERT# ==> NC */<br>+ PAD_CFG_NC(GPP_C5),<br>+ /* C6 : SM1CLK ==> EC_IN_RW_OD */<br>+ PAD_CFG_GPI(GPP_C6, 20K_PU, DEEP),<br>+ /* C7 : SM1DATA ==> NC */<br>+ PAD_CFG_NC(GPP_C7),<br>+ /* C8 : UART0_RXD ==> FP_INT */<br>+ PAD_CFG_GPI_APIC(GPP_C8, NONE, PLTRST),<br>+ /* C9 : UART0_TXD ==> FP_RST_ODL */<br>+ PAD_CFG_GPO(GPP_C9, 0, DEEP),<br>+ /* C10 : UART0_RTS# ==> EC_CAM_PMIC_RST_L */<br>+ PAD_CFG_GPO(GPP_C10, 1, DEEP),<br>+ /* C11 : UART0_CTS# ==> EN_PP3300_DX_CAM */<br>+ PAD_CFG_GPO(GPP_C11, 1, DEEP),<br>+ /* C12 : UART1_RXD ==> PCH_MEM_CONFIG[0] */<br>+ PAD_CFG_GPI(GPP_C12, NONE, DEEP),<br>+ /* C13 : UART1_TXD ==> PCH_MEM_CONFIG[1] */<br>+ PAD_CFG_GPI(GPP_C13, NONE, DEEP),<br>+ /* C14 : UART1_RTS# ==> PCH_MEM_CONFIG[2] */<br>+ PAD_CFG_GPI(GPP_C14, NONE, DEEP),<br>+ /* C15 : UART1_CTS# ==> PCH_MEM_CONFIG[3] */<br>+ PAD_CFG_GPI(GPP_C15, NONE, DEEP),<br>+ /* C16 : I2C0_SDA ==> PCH_I2C0_TOUCHSCREEN_3V3_SDA */<br>+ PAD_CFG_NF(GPP_C16, NONE, DEEP, NF1),<br>+ /* C17 : I2C0_SCL ==> PCH_I2C0_TOUCHSCREEN_3V3_SCL */<br>+ PAD_CFG_NF(GPP_C17, NONE, DEEP, NF1),<br>+#if IS_ENABLED(CONFIG_POPPY_USE_I2C_TPM)<br>+ /* C18 : I2C1_SDA ==> PCH_I2C1_H1_3V3_SDA */<br>+ PAD_CFG_NF(GPP_C18, NONE, DEEP, NF1),<br>+ /* C19 : I2C1_SCL ==> PCH_I2C1_H1_3V3_SCL */<br>+ PAD_CFG_NF(GPP_C19, NONE, DEEP, NF1),<br>+#else<br>+ /* C18 : I2C1_SDA ==> NC */<br>+ PAD_CFG_NC(GPP_C18),<br>+ /* C19 : I2C1_SCL ==> NC */<br>+ PAD_CFG_NC(GPP_C19),<br>+#endif<br>+ /* C20 : UART2_RXD ==> PCHRX_SERVOTX_UART */<br>+ PAD_CFG_NF(GPP_C20, NONE, DEEP, NF1),<br>+ /* C21 : UART2_TXD ==> PCHTX_SERVORX_UART */<br>+ PAD_CFG_NF(GPP_C21, NONE, DEEP, NF1),<br>+ /* C22 : UART2_RTS# ==> EN_PP3300_DX_TOUCHSCREEN */<br>+ PAD_CFG_GPO(GPP_C22, 0, DEEP),<br>+ /* C23 : UART2_CTS# ==> PCH_WP */<br>+ PAD_CFG_GPI(GPP_C23, 20K_PU, DEEP),<br>+<br>+ /* D0 : SPI1_CS# ==> NC */<br>+ PAD_CFG_NC(GPP_D0),<br>+ /* D1 : SPI1_CLK ==> PEN_IRQ_L */<br>+ PAD_CFG_GPI_APIC(GPP_D1, NONE, PLTRST),<br>+ /* D2 : SPI1_MISO ==> PEN_PDCT_L */<br>+ PAD_CFG_GPI(GPP_D2, NONE, DEEP),<br>+ /* D3 : SPI1_MOSI ==> NC */<br>+ PAD_CFG_NC(GPP_D3),<br>+ /* D4 : FASHTRIG ==> NC */<br>+ PAD_CFG_NC(GPP_D4),<br>+ /* D5 : ISH_I2C0_SDA ==> ISH_I2C_SENSOR_1V8_SDA */<br>+ PAD_CFG_NF_1V8(GPP_D5, NONE, DEEP, NF1),<br>+ /* D6 : ISH_I2C0_SCL ==> ISH_I2C_SENSOR_1V8_SCL */<br>+ PAD_CFG_NF_1V8(GPP_D6, NONE, DEEP, NF1),<br>+ /* D7 : ISH_I2C1_SDA ==> NC */<br>+ PAD_CFG_NC(GPP_D7),<br>+ /* D8 : ISH_I2C1_SCL ==> NC */<br>+ PAD_CFG_NC(GPP_D8),<br>+ /* D9 : ISH_SPI_CS# ==> HP_IRQ_GPIO */<br>+ PAD_CFG_GPI(GPP_D9, NONE, PLTRST),<br>+ /* D10 : ISH_SPI_CLK ==> SPKR_RST_L */<br>+ PAD_CFG_GPO(GPP_D10, 1, DEEP),<br>+ /* D11 : ISH_SPI_MISO ==> SPKR_INT_L */<br>+ PAD_CFG_GPI_APIC(GPP_D11, NONE, PLTRST),<br>+ /* D12 : ISH_SPI_MOSI ==> NC */<br>+ PAD_CFG_NC(GPP_D12),<br>+ /* D13 : ISH_UART0_RXD ==> NC */<br>+ PAD_CFG_NC(GPP_D13),<br>+ /* D14 : ISH_UART0_TXD ==> NC */<br>+ PAD_CFG_NC(GPP_D14),<br>+ /* D15 : ISH_UART0_RTS# ==> NC */<br>+ PAD_CFG_NC(GPP_D15),<br>+ /* D16 : ISH_UART0_CTS# ==> NC */<br>+ PAD_CFG_NC(GPP_D16),<br>+ /* D17 : DMIC_CLK1 */<br>+ PAD_CFG_NF(GPP_D17, NONE, DEEP, NF1),<br>+ /* D18 : DMIC_DATA1 */<br>+ PAD_CFG_NF(GPP_D18, NONE, DEEP, NF1),<br>+ /* D19 : DMIC_CLK0 */<br>+ PAD_CFG_NF(GPP_D19, NONE, DEEP, NF1),<br>+ /* D20 : DMIC_DATA0 */<br>+ PAD_CFG_NF(GPP_D20, NONE, DEEP, NF1),<br>+ /* D21 : SPI1_IO2 ==> NC */<br>+ PAD_CFG_NC(GPP_D21),<br>+ /* D22 : SPI1_IO3 ==> BOOT_BEEP_OVERRIDE */<br>+ PAD_CFG_GPO(GPP_D22, 1, DEEP),<br>+ /* D23 : I2S_MCLK ==> I2S_MCLK_R */<br>+ PAD_CFG_NF(GPP_D23, NONE, DEEP, NF1),<br>+<br>+ /* E0 : SATAXPCI0 ==> H1_PCH_INT_ODL */<br>+ PAD_CFG_GPI_APIC_INVERT(GPP_E0, NONE, PLTRST),<br>+ /* E1 : SATAXPCIE1 ==> NC */<br>+ PAD_CFG_NC(GPP_E1),<br>+ /* E2 : SATAXPCIE2 ==> NC */<br>+ PAD_CFG_NC(GPP_E2),<br>+ /* E3 : CPU_GP0 ==> TOUCHSCREEN_RST_L */<br>+ PAD_CFG_GPO(GPP_E3, 0, DEEP),<br>+ /* E4 : SATA_DEVSLP0 ==> NC */<br>+ PAD_CFG_NC(GPP_E4),<br>+ /* E5 : SATA_DEVSLP1 ==> NC */<br>+ PAD_CFG_NC(GPP_E5),<br>+ /* E6 : SATA_DEVSLP2 ==> NC */<br>+ PAD_CFG_NC(GPP_E6),<br>+ /* E7 : CPU_GP1 ==> TOUCHSCREEN_INT_L */<br>+ PAD_CFG_GPI_APIC(GPP_E7, NONE, PLTRST),<br>+ /* E8 : SATALED# ==> NC */<br>+ PAD_CFG_NC(GPP_E8),<br>+ /* E9 : USB2_OCO# ==> USB_C0_OC_ODL */<br>+ PAD_CFG_NF(GPP_E9, NONE, DEEP, NF1),<br>+ /* E10 : USB2_OC1# ==> USB_C1_OC_ODL */<br>+ PAD_CFG_NF(GPP_E10, NONE, DEEP, NF1),<br>+ /* E11 : USB2_OC2# ==> TOUCHSCREEN_RESET_L */<br>+ PAD_CFG_GPO(GPP_E11, 0, DEEP),<br>+ /* E12 : USB2_OC3# ==> USB2_OC3_L */<br>+ PAD_CFG_NF(GPP_E12, NONE, DEEP, NF1),<br>+ /* E13 : DDPB_HPD0 ==> USB_C0_DP_HPD */<br>+ PAD_CFG_NF(GPP_E13, 20K_PD, DEEP, NF1),<br>+ /* E14 : DDPC_HPD1 ==> USB_C1_DP_HPD */<br>+ PAD_CFG_NF(GPP_E14, 20K_PD, DEEP, NF1),<br>+ /* E15 : DDPD_HPD2 ==> SD_CD# */<br>+ PAD_CFG_GPI(GPP_E15, 20K_PU, DEEP),<br>+ /* E16 : DDPE_HPD3 ==> NC(TP244) */<br>+ PAD_CFG_NC(GPP_E16),<br>+ /* E17 : EDP_HPD */<br>+ PAD_CFG_NF(GPP_E17, NONE, DEEP, NF1),<br>+ /* E18 : DDPB_CTRLCLK ==> NC */<br>+ PAD_CFG_NC(GPP_E18),<br>+ /* E19 : DDPB_CTRLDATA ==> NC */<br>+ PAD_CFG_NC(GPP_E19),<br>+ /* E20 : DDPC_CTRLCLK ==> NC */<br>+ PAD_CFG_NC(GPP_E20),<br>+ /* E21 : DDPC_CTRLDATA ==> NC */<br>+ PAD_CFG_NC(GPP_E21),<br>+ /* E22 : DDPD_CTRLCLK ==> NC */<br>+ PAD_CFG_NC(GPP_E22),<br>+ /* E23 : DDPD_CTRLDATA ==> NC */<br>+ PAD_CFG_NC(GPP_E23),<br>+<br>+ /* The next 4 pads are for bit banging the amplifiers, default to I2S */<br>+ /* F0 : I2S2_SCLK ==> I2S2_SCLK_SPKR_R */<br>+ PAD_CFG_GPI(GPP_F0, NONE, DEEP),<br>+ /* F1 : I2S2_SFRM ==> I2S2_SFRM_SPKR_R */<br>+ PAD_CFG_GPI(GPP_F1, NONE, DEEP),<br>+ /* F2 : I2S2_TXD ==> I2S2_PCH_TX_SPKR_RX_R */<br>+ PAD_CFG_GPI(GPP_F2, NONE, DEEP),<br>+ /* F3 : I2S2_RXD */<br>+ PAD_CFG_GPI(GPP_F3, NONE, DEEP),<br>+ /* F4 : I2C2_SDA ==> PCH_I2C2_CAM_PMIC_1V8_SDA */<br>+ PAD_CFG_NF_1V8(GPP_F4, NONE, DEEP, NF1),<br>+ /* F5 : I2C2_SCL ==> PCH_I2C2_CAM_PMIC_1V8_SCL */<br>+ PAD_CFG_NF_1V8(GPP_F5, NONE, DEEP, NF1),<br>+ /* F6 : I2C3_SDA ==> PCH_I2C3_PEN_1V8_SDA */<br>+ PAD_CFG_NF_1V8(GPP_F6, NONE, DEEP, NF1),<br>+ /* F7 : I2C3_SCL ==> PCH_I2C3_PEN_1V8_SCL */<br>+ PAD_CFG_NF_1V8(GPP_F7, NONE, DEEP, NF1),<br>+ /* F8 : I2C4_SDA ==> PCH_I2C4_UFCAM_1V8_SDA */<br>+ PAD_CFG_NF_1V8(GPP_F8, NONE, DEEP, NF1),<br>+ /* F9 : I2C4_SCL ==> PCH_I2C4_UFCAM_1V8_SCL */<br>+ PAD_CFG_NF_1V8(GPP_F9, NONE, DEEP, NF1),<br>+ /* F10 : I2C5_SDA ==> PCH_I2C5_AUDIO_1V8_SDA */<br>+ PAD_CFG_NF_1V8(GPP_F10, NONE, DEEP, NF1),<br>+ /* F11 : I2C5_SCL ==> PCH_I2C5_AUDIO_1V8_SCL */<br>+ PAD_CFG_NF_1V8(GPP_F11, NONE, DEEP, NF1),<br>+ /* F12 : EMMC_CMD */<br>+ PAD_CFG_NF(GPP_F12, NONE, DEEP, NF1),<br>+ /* F13 : EMMC_DATA0 */<br>+ PAD_CFG_NF(GPP_F13, NONE, DEEP, NF1),<br>+ /* F14 : EMMC_DATA1 */<br>+ PAD_CFG_NF(GPP_F14, NONE, DEEP, NF1),<br>+ /* F15 : EMMC_DATA2 */<br>+ PAD_CFG_NF(GPP_F15, NONE, DEEP, NF1),<br>+ /* F16 : EMMC_DATA3 */<br>+ PAD_CFG_NF(GPP_F16, NONE, DEEP, NF1),<br>+ /* F17 : EMMC_DATA4 */<br>+ PAD_CFG_NF(GPP_F17, NONE, DEEP, NF1),<br>+ /* F18 : EMMC_DATA5 */<br>+ PAD_CFG_NF(GPP_F18, NONE, DEEP, NF1),<br>+ /* F19 : EMMC_DATA6 */<br>+ PAD_CFG_NF(GPP_F19, NONE, DEEP, NF1),<br>+ /* F20 : EMMC_DATA7 */<br>+ PAD_CFG_NF(GPP_F20, NONE, DEEP, NF1),<br>+ /* F21 : EMMC_RCLK */<br>+ PAD_CFG_NF(GPP_F21, NONE, DEEP, NF1),<br>+ /* F22 : EMMC_CLK */<br>+ PAD_CFG_NF(GPP_F22, NONE, DEEP, NF1),<br>+ /* F23 : RSVD ==> NC */<br>+ PAD_CFG_NC(GPP_F23),<br>+<br>+ /* G0 : SD_CMD */<br>+ PAD_CFG_NF(GPP_G0, NONE, DEEP, NF1),<br>+ /* G1 : SD_DATA0 */<br>+ PAD_CFG_NF(GPP_G1, NONE, DEEP, NF1),<br>+ /* G2 : SD_DATA1 */<br>+ PAD_CFG_NF(GPP_G2, NONE, DEEP, NF1),<br>+ /* G3 : SD_DATA2 */<br>+ PAD_CFG_NF(GPP_G3, NONE, DEEP, NF1),<br>+ /* G4 : SD_DATA3 */<br>+ PAD_CFG_NF(GPP_G4, NONE, DEEP, NF1),<br>+ /* G5 : SD_CD# */<br>+ PAD_CFG_NF(GPP_G5, NONE, DEEP, NF1),<br>+ /* G6 : SD_CLK */<br>+ PAD_CFG_NF(GPP_G6, NONE, DEEP, NF1),<br>+ /* G7 : SD_WP */<br>+ PAD_CFG_NF(GPP_G7, 20K_PD, DEEP, NF1),<br>+<br>+ /* GPD0: BATLOW# ==> PCH_BATLOW_L */<br>+ PAD_CFG_NF(GPD0, NONE, DEEP, NF1),<br>+ /* GPD1: ACPRESENT ==> EC_PCH_ACPRESENT */<br>+ PAD_CFG_NF(GPD1, NONE, DEEP, NF1),<br>+ /* GPD2: LAN_WAKE# ==> EC_PCH_WAKE_R_L */<br>+ PAD_CFG_NF(GPD2, NONE, DEEP, NF1),<br>+ /* GPD3: PWRBTN# ==> PCH_PWR_BTN_L */<br>+ PAD_CFG_NF(GPD3, 20K_PU, DEEP, NF1),<br>+ /* GPD4: SLP_S3# ==> SLP_S3_L */<br>+ PAD_CFG_NF(GPD4, NONE, DEEP, NF1),<br>+ /* GPD5: SLP_S4# ==> SLP_S4_L */<br>+ PAD_CFG_NF(GPD5, NONE, DEEP, NF1),<br>+ /* GPD6: SLP_A# ==> NC(TP26) */<br>+ PAD_CFG_NC(GPD6),<br>+ /* GPD7: RSVD ==> NC */<br>+ PAD_CFG_NC(GPD7),<br>+ /* GPD8: SUSCLK ==> PCH_SUSCLK */<br>+ PAD_CFG_NF(GPD8, NONE, DEEP, NF1),<br>+ /* GPD9: SLP_WLAN# ==> NC(TP25) */<br>+ PAD_CFG_NC(GPD9),<br>+ /* GPD10: SLP_S5# ==> NC(TP15) */<br>+ PAD_CFG_NC(GPD10),<br>+ /* GPD11: LANPHYC ==> NC */<br>+ PAD_CFG_NC(GPD11),<br>+};<br>+<br>+/* Early pad configuration in bootblock */<br>+static const struct pad_config early_gpio_table[] = {<br>+#if IS_ENABLED(CONFIG_POPPY_USE_SPI_TPM)<br>+ /* B15 : GSPI0_CS# ==> PCH_SPI_H1_3V3_CS_L */<br>+ PAD_CFG_NF(GPP_B15, NONE, DEEP, NF1),<br>+ /* B16 : GSPI0_CLK ==> PCH_SPI_H1_3V3_CLK */<br>+ PAD_CFG_NF(GPP_B16, NONE, DEEP, NF1),<br>+ /* B17 : GSPI0_MISO ==> PCH_SPI_H1_3V3_MISO */<br>+ PAD_CFG_NF(GPP_B17, NONE, DEEP, NF1),<br>+ /* B18 : GSPI0_MOSI ==> PCH_SPI_H1_3V3_MOSI */<br>+ PAD_CFG_NF(GPP_B18, NONE, DEEP, NF1),<br>+#endif<br>+<br>+#if IS_ENABLED(CONFIG_POPPY_USE_I2C_TPM)<br>+ /* C18 : I2C1_SDA ==> PCH_I2C1_H1_3V3_SDA */<br>+ PAD_CFG_NF(GPP_C18, NONE, DEEP, NF1),<br>+ /* C19 : I2C1_SCL ==> PCH_I2C1_H1_3V3_SCL */<br>+ PAD_CFG_NF(GPP_C19, NONE, DEEP, NF1),<br>+#endif<br>+<br>+ /* Ensure UART pins are in native mode for H1. */<br>+ /* C20 : UART2_RXD ==> PCHRX_SERVOTX_UART */<br>+ PAD_CFG_NF(GPP_C20, NONE, DEEP, NF1),<br>+ /* C21 : UART2_TXD ==> PCHTX_SERVORX_UART */<br>+ PAD_CFG_NF(GPP_C21, NONE, DEEP, NF1),<br>+<br>+ /* C23 : UART2_CTS# ==> PCH_WP */<br>+ PAD_CFG_GPI(GPP_C23, 20K_PU, DEEP),<br>+<br>+ /* E0 : SATAXPCI0 ==> H1_PCH_INT_ODL */<br>+ PAD_CFG_GPI_APIC_INVERT(GPP_E0, NONE, PLTRST),<br>+};<br>+<br>+const struct pad_config *variant_gpio_table(size_t *num)<br>+{<br>+ printk(BIOS_ERR, "FUR: %s\n", __func__);<br>+ *num = ARRAY_SIZE(gpio_table);<br>+ return gpio_table;<br>+}<br>+<br>+const struct pad_config *variant_early_gpio_table(size_t *num)<br>+{<br>+ printk(BIOS_ERR, "FUR: %s\n", __func__);<br>+ *num = ARRAY_SIZE(early_gpio_table);<br>+ return early_gpio_table;<br>+}<br>+<br>+static const struct cros_gpio cros_gpios[] = {<br>+ CROS_GPIO_REC_AL(CROS_GPIO_VIRTUAL, CROS_GPIO_DEVICE_NAME),<br>+ CROS_GPIO_WP_AH(GPIO_PCH_WP, CROS_GPIO_DEVICE_NAME),<br>+};<br>+<br>+const struct cros_gpio *variant_cros_gpios(size_t *num)<br>+{<br>+ printk(BIOS_ERR, "FUR: %s\n", __func__);<br>+ *num = ARRAY_SIZE(cros_gpios);<br>+ return cros_gpios;<br>+}<br></pre><p>To view, visit <a href="https://review.coreboot.org/20671">change 20671</a>. To unsubscribe, visit <a href="https://review.coreboot.org/settings">settings</a>.</p><div itemscope itemtype="http://schema.org/EmailMessage"><div itemscope itemprop="action" itemtype="http://schema.org/ViewAction"><link itemprop="url" href="https://review.coreboot.org/20671"/><meta itemprop="name" content="View Change"/></div></div>
<div style="display:none"> Gerrit-Project: coreboot </div>
<div style="display:none"> Gerrit-Branch: master </div>
<div style="display:none"> Gerrit-MessageType: newchange </div>
<div style="display:none"> Gerrit-Change-Id: I448d18f18b63e9bfb739c518d599de3b9b602dc2 </div>
<div style="display:none"> Gerrit-Change-Number: 20671 </div>
<div style="display:none"> Gerrit-PatchSet: 1 </div>
<div style="display:none"> Gerrit-Owner: Furquan Shaikh <furquan@google.com> </div>