<p>Martin Roth has uploaded this change for <strong>review</strong>.</p><p><a href="https://review.coreboot.org/20607">View Change</a></p><pre style="font-family: monospace,monospace; white-space: pre-wrap;">sb/amd/cs5536: Remove includes of C files<br><br>The romstage for CS5536 platforms were including early_smbus.c and<br>early_setup.c.  Build these into romstage from the makefile, and remove<br>the #includes.<br><br>Add a Kconfig option for platforms that do not use the<br>early smbus code.<br><br>Change-Id: I2e6a9cd859292b4dd4720b547d1ff0bbb6c319cf<br>Signed-off-by: Martin Roth <martinroth@google.com><br>---<br>M src/mainboard/aaeon/pfm-540i_revb/romstage.c<br>M src/mainboard/amd/db800/romstage.c<br>M src/mainboard/amd/f2950/romstage.c<br>M src/mainboard/amd/norwich/romstage.c<br>M src/mainboard/amd/rumba/romstage.c<br>M src/mainboard/artecgroup/dbe61/romstage.c<br>M src/mainboard/bachmann/ot200/romstage.c<br>M src/mainboard/digitallogic/msm800sev/romstage.c<br>M src/mainboard/iei/pcisa-lx-800-r10/romstage.c<br>M src/mainboard/iei/pm-lx-800-r11/romstage.c<br>M src/mainboard/iei/pm-lx2-800-r10/romstage.c<br>M src/mainboard/lippert/hurricane-lx/romstage.c<br>M src/mainboard/lippert/literunner-lx/romstage.c<br>M src/mainboard/lippert/roadrunner-lx/romstage.c<br>M src/mainboard/lippert/spacerunner-lx/romstage.c<br>M src/mainboard/pcengines/alix1c/Kconfig<br>M src/mainboard/pcengines/alix1c/romstage.c<br>M src/mainboard/pcengines/alix2d/Kconfig<br>M src/mainboard/pcengines/alix2d/romstage.c<br>M src/mainboard/traverse/geos/romstage.c<br>M src/mainboard/winent/pl6064/romstage.c<br>M src/mainboard/wyse/s50/romstage.c<br>M src/southbridge/amd/cs5536/Kconfig<br>M src/southbridge/amd/cs5536/Makefile.inc<br>M src/southbridge/amd/cs5536/cs5536.h<br>M src/southbridge/amd/cs5536/early_setup.c<br>M src/southbridge/amd/cs5536/early_smbus.c<br>27 files changed, 36 insertions(+), 48 deletions(-)<br><br></pre><pre style="font-family: monospace,monospace; white-space: pre-wrap;">git pull ssh://review.coreboot.org:29418/coreboot refs/changes/07/20607/1</pre><pre style="font-family: monospace,monospace; white-space: pre-wrap;">diff --git a/src/mainboard/aaeon/pfm-540i_revb/romstage.c b/src/mainboard/aaeon/pfm-540i_revb/romstage.c<br>index c35a68d..7efd988 100644<br>--- a/src/mainboard/aaeon/pfm-540i_revb/romstage.c<br>+++ b/src/mainboard/aaeon/pfm-540i_revb/romstage.c<br>@@ -28,8 +28,6 @@<br> #include <cpu/amd/lxdef.h><br> #include <southbridge/amd/cs5536/cs5536.h><br> #include <spd.h><br>-#include "southbridge/amd/cs5536/early_smbus.c"<br>-#include "southbridge/amd/cs5536/early_setup.c"<br> #include <superio/smsc/smscsuperio/smscsuperio.h><br> #include <northbridge/amd/lx/raminit.h><br> <br>diff --git a/src/mainboard/amd/db800/romstage.c b/src/mainboard/amd/db800/romstage.c<br>index f9b682a..5ebc76d 100644<br>--- a/src/mainboard/amd/db800/romstage.c<br>+++ b/src/mainboard/amd/db800/romstage.c<br>@@ -25,8 +25,6 @@<br> #include <cpu/amd/lxdef.h><br> #include <southbridge/amd/cs5536/cs5536.h><br> #include <spd.h><br>-#include "southbridge/amd/cs5536/early_smbus.c"<br>-#include "southbridge/amd/cs5536/early_setup.c"<br> #include <superio/winbond/common/winbond.h><br> #include <superio/winbond/w83627hf/w83627hf.h><br> #include <northbridge/amd/lx/raminit.h><br>diff --git a/src/mainboard/amd/f2950/romstage.c b/src/mainboard/amd/f2950/romstage.c<br>index 6d59995..341a8ea 100644<br>--- a/src/mainboard/amd/f2950/romstage.c<br>+++ b/src/mainboard/amd/f2950/romstage.c<br>@@ -25,8 +25,6 @@<br> #include <cpu/amd/lxdef.h><br> #include <southbridge/amd/cs5536/cs5536.h><br> #include <spd.h><br>-#include "southbridge/amd/cs5536/early_smbus.c"<br>-#include "southbridge/amd/cs5536/early_setup.c"<br> #include <superio/winbond/common/winbond.h><br> #include <superio/winbond/w83627hf/w83627hf.h><br> #include <northbridge/amd/lx/raminit.h><br>diff --git a/src/mainboard/amd/norwich/romstage.c b/src/mainboard/amd/norwich/romstage.c<br>index 52df856..288a647 100644<br>--- a/src/mainboard/amd/norwich/romstage.c<br>+++ b/src/mainboard/amd/norwich/romstage.c<br>@@ -25,8 +25,6 @@<br> #include <cpu/amd/lxdef.h><br> #include <southbridge/amd/cs5536/cs5536.h><br> #include <spd.h><br>-#include "southbridge/amd/cs5536/early_smbus.c"<br>-#include "southbridge/amd/cs5536/early_setup.c"<br> #include <northbridge/amd/lx/raminit.h><br> <br> int spd_read_byte(unsigned int device, unsigned int address)<br>diff --git a/src/mainboard/amd/rumba/romstage.c b/src/mainboard/amd/rumba/romstage.c<br>index 2568a92..4d9600a 100644<br>--- a/src/mainboard/amd/rumba/romstage.c<br>+++ b/src/mainboard/amd/rumba/romstage.c<br>@@ -22,8 +22,7 @@<br> #include <cpu/x86/msr.h><br> #include <cpu/amd/gx2def.h><br> #include <spd.h><br>-#include "southbridge/amd/cs5536/early_smbus.c"<br>-#include "southbridge/amd/cs5536/early_setup.c"<br>+#include <southbridge/amd/cs5536/cs5536.h><br> <br> #define SERIAL_DEV PNP_DEV(0x2e, W83627HF_SP1)<br> <br>diff --git a/src/mainboard/artecgroup/dbe61/romstage.c b/src/mainboard/artecgroup/dbe61/romstage.c<br>index 1e7d680..215d0d9 100644<br>--- a/src/mainboard/artecgroup/dbe61/romstage.c<br>+++ b/src/mainboard/artecgroup/dbe61/romstage.c<br>@@ -26,8 +26,6 @@<br> #include <southbridge/amd/cs5536/cs5536.h><br> #include "spd_table.h"<br> #include <spd.h><br>-#include "southbridge/amd/cs5536/early_smbus.c"<br>-#include "southbridge/amd/cs5536/early_setup.c"<br> #include <northbridge/amd/lx/raminit.h><br> <br> int spd_read_byte(unsigned int device, unsigned int address)<br>diff --git a/src/mainboard/bachmann/ot200/romstage.c b/src/mainboard/bachmann/ot200/romstage.c<br>index f0e502d..a40f759 100644<br>--- a/src/mainboard/bachmann/ot200/romstage.c<br>+++ b/src/mainboard/bachmann/ot200/romstage.c<br>@@ -27,8 +27,6 @@<br> #include <cpu/amd/car.h><br> #include <cpu/amd/lxdef.h><br> #include <southbridge/amd/cs5536/cs5536.h><br>-#include "southbridge/amd/cs5536/early_smbus.c"<br>-#include "southbridge/amd/cs5536/early_setup.c"<br> #include <northbridge/amd/lx/raminit.h><br> <br> int spd_read_byte(unsigned int device, unsigned int address)<br>diff --git a/src/mainboard/digitallogic/msm800sev/romstage.c b/src/mainboard/digitallogic/msm800sev/romstage.c<br>index dee326d..81975cf 100644<br>--- a/src/mainboard/digitallogic/msm800sev/romstage.c<br>+++ b/src/mainboard/digitallogic/msm800sev/romstage.c<br>@@ -23,8 +23,6 @@<br> #include <cpu/amd/lxdef.h><br> #include <southbridge/amd/cs5536/cs5536.h><br> #include <spd.h><br>-#include "southbridge/amd/cs5536/early_smbus.c"<br>-#include "southbridge/amd/cs5536/early_setup.c"<br> #include <superio/winbond/common/winbond.h><br> #include <superio/winbond/w83627hf/w83627hf.h><br> #include <northbridge/amd/lx/raminit.h><br>diff --git a/src/mainboard/iei/pcisa-lx-800-r10/romstage.c b/src/mainboard/iei/pcisa-lx-800-r10/romstage.c<br>index 6b8c73c..f5d5de4 100644<br>--- a/src/mainboard/iei/pcisa-lx-800-r10/romstage.c<br>+++ b/src/mainboard/iei/pcisa-lx-800-r10/romstage.c<br>@@ -26,8 +26,6 @@<br> #include <cpu/amd/lxdef.h><br> #include <southbridge/amd/cs5536/cs5536.h><br> #include <spd.h><br>-#include "southbridge/amd/cs5536/early_smbus.c"<br>-#include "southbridge/amd/cs5536/early_setup.c"<br> #include <superio/winbond/common/winbond.h><br> #include <superio/winbond/w83627hf/w83627hf.h><br> #include <northbridge/amd/lx/raminit.h><br>diff --git a/src/mainboard/iei/pm-lx-800-r11/romstage.c b/src/mainboard/iei/pm-lx-800-r11/romstage.c<br>index e6cf98a..52936ad 100644<br>--- a/src/mainboard/iei/pm-lx-800-r11/romstage.c<br>+++ b/src/mainboard/iei/pm-lx-800-r11/romstage.c<br>@@ -25,8 +25,6 @@<br> #include <cpu/x86/msr.h><br> #include <cpu/amd/lxdef.h><br> #include <southbridge/amd/cs5536/cs5536.h><br>-#include <southbridge/amd/cs5536/early_smbus.c><br>-#include <southbridge/amd/cs5536/early_setup.c><br> #include <superio/winbond/common/winbond.h><br> #include <superio/winbond/w83627ehg/w83627ehg.h><br> #include <northbridge/amd/lx/raminit.h><br>diff --git a/src/mainboard/iei/pm-lx2-800-r10/romstage.c b/src/mainboard/iei/pm-lx2-800-r10/romstage.c<br>index b0f9d33..3ea6013 100644<br>--- a/src/mainboard/iei/pm-lx2-800-r10/romstage.c<br>+++ b/src/mainboard/iei/pm-lx2-800-r10/romstage.c<br>@@ -27,8 +27,6 @@<br> #include <cpu/amd/car.h><br> #include <cpu/amd/lxdef.h><br> #include <southbridge/amd/cs5536/cs5536.h><br>-#include <southbridge/amd/cs5536/early_smbus.c><br>-#include <southbridge/amd/cs5536/early_setup.c><br> #include <superio/smsc/smscsuperio/smscsuperio.h><br> #include <northbridge/amd/lx/raminit.h><br> <br>diff --git a/src/mainboard/lippert/hurricane-lx/romstage.c b/src/mainboard/lippert/hurricane-lx/romstage.c<br>index 9d7b565..2647ec8 100644<br>--- a/src/mainboard/lippert/hurricane-lx/romstage.c<br>+++ b/src/mainboard/lippert/hurricane-lx/romstage.c<br>@@ -27,9 +27,8 @@<br> #include <cpu/x86/msr.h><br> #include <cpu/amd/lxdef.h><br> #include <southbridge/amd/cs5536/cs5536.h><br>+#include <southbridge/amd/cs5536/smbus.h><br> #include <spd.h><br>-#include "southbridge/amd/cs5536/early_smbus.c"<br>-#include "southbridge/amd/cs5536/early_setup.c"<br> #include <superio/ite/common/ite.h><br> #include <superio/ite/it8712f/it8712f.h><br> #include <northbridge/amd/lx/raminit.h><br>diff --git a/src/mainboard/lippert/literunner-lx/romstage.c b/src/mainboard/lippert/literunner-lx/romstage.c<br>index 1474ecd..e36d4ca 100644<br>--- a/src/mainboard/lippert/literunner-lx/romstage.c<br>+++ b/src/mainboard/lippert/literunner-lx/romstage.c<br>@@ -28,8 +28,7 @@<br> #include <cpu/x86/msr.h><br> #include <cpu/amd/lxdef.h><br> #include <southbridge/amd/cs5536/cs5536.h><br>-#include "southbridge/amd/cs5536/early_smbus.c"<br>-#include "southbridge/amd/cs5536/early_setup.c"<br>+#include <southbridge/amd/cs5536/smbus.h><br> #include <superio/ite/common/ite.h><br> #include <superio/ite/it8712f/it8712f.h><br> #include <northbridge/amd/lx/raminit.h><br>diff --git a/src/mainboard/lippert/roadrunner-lx/romstage.c b/src/mainboard/lippert/roadrunner-lx/romstage.c<br>index 8341178..65ddcb7 100644<br>--- a/src/mainboard/lippert/roadrunner-lx/romstage.c<br>+++ b/src/mainboard/lippert/roadrunner-lx/romstage.c<br>@@ -28,8 +28,6 @@<br> #include <cpu/amd/lxdef.h><br> #include <southbridge/amd/cs5536/cs5536.h><br> #include <spd.h><br>-#include "southbridge/amd/cs5536/early_smbus.c"<br>-#include "southbridge/amd/cs5536/early_setup.c"<br> #include <superio/ite/common/ite.h><br> #include <superio/ite/it8712f/it8712f.h><br> #include <northbridge/amd/lx/raminit.h><br>diff --git a/src/mainboard/lippert/spacerunner-lx/romstage.c b/src/mainboard/lippert/spacerunner-lx/romstage.c<br>index a73276e..897de07 100644<br>--- a/src/mainboard/lippert/spacerunner-lx/romstage.c<br>+++ b/src/mainboard/lippert/spacerunner-lx/romstage.c<br>@@ -28,8 +28,7 @@<br> #include <cpu/x86/msr.h><br> #include <cpu/amd/lxdef.h><br> #include <southbridge/amd/cs5536/cs5536.h><br>-#include "southbridge/amd/cs5536/early_smbus.c"<br>-#include "southbridge/amd/cs5536/early_setup.c"<br>+#include <southbridge/amd/cs5536/smbus.h><br> #include <superio/ite/common/ite.h><br> #include <superio/ite/it8712f/it8712f.h><br> #include <northbridge/amd/lx/raminit.h><br>diff --git a/src/mainboard/pcengines/alix1c/Kconfig b/src/mainboard/pcengines/alix1c/Kconfig<br>index bbd78a3..75b3d07 100644<br>--- a/src/mainboard/pcengines/alix1c/Kconfig<br>+++ b/src/mainboard/pcengines/alix1c/Kconfig<br>@@ -13,6 +13,7 @@<br>        select POWER_BUTTON_DEFAULT_DISABLE<br>   select HAVE_OPTION_TABLE<br>      select HAVE_CMOS_DEFAULT<br>+     select NO_EARLY_SMBUS<br> <br> config MAINBOARD_DIR<br>       string<br>diff --git a/src/mainboard/pcengines/alix1c/romstage.c b/src/mainboard/pcengines/alix1c/romstage.c<br>index 1d43069..962e15d 100644<br>--- a/src/mainboard/pcengines/alix1c/romstage.c<br>+++ b/src/mainboard/pcengines/alix1c/romstage.c<br>@@ -30,10 +30,6 @@<br> <br> #define SERIAL_DEV PNP_DEV(0x2e, W83627HF_SP1)<br> <br>-/* The ALIX1.C has no SMBus; the setup is hard-wired. */<br>-static void cs5536_enable_smbus(void) { }<br>-<br>-#include "southbridge/amd/cs5536/early_setup.c"<br> #include <superio/winbond/common/winbond.h><br> #include <superio/winbond/w83627hf/w83627hf.h><br> <br>diff --git a/src/mainboard/pcengines/alix2d/Kconfig b/src/mainboard/pcengines/alix2d/Kconfig<br>index a350e11..95a68aa 100644<br>--- a/src/mainboard/pcengines/alix2d/Kconfig<br>+++ b/src/mainboard/pcengines/alix2d/Kconfig<br>@@ -10,6 +10,7 @@<br>        select UDELAY_TSC<br>     select BOARD_ROMSIZE_KB_512<br>   select POWER_BUTTON_FORCE_DISABLE<br>+    select NO_EARLY_SMBUS<br> <br> config MAINBOARD_DIR<br>       string<br>diff --git a/src/mainboard/pcengines/alix2d/romstage.c b/src/mainboard/pcengines/alix2d/romstage.c<br>index c7bf9ef..750f755 100644<br>--- a/src/mainboard/pcengines/alix2d/romstage.c<br>+++ b/src/mainboard/pcengines/alix2d/romstage.c<br>@@ -30,11 +30,6 @@<br> <br> #define SERIAL_DEV PNP_DEV(0x2e, W83627HF_SP1)<br> <br>-/* The ALIX.2D has no SMBus; the setup is hard-wired. */<br>-static void cs5536_enable_smbus(void) { }<br>-<br>-#include "southbridge/amd/cs5536/early_setup.c"<br>-<br> /* The part is a Hynix hy5du121622ctp-d43.<br>  *<br>  * HY 5D U 12 16 2 2 C <blank> T <blank> P D43<br>diff --git a/src/mainboard/traverse/geos/romstage.c b/src/mainboard/traverse/geos/romstage.c<br>index abf2ec9..a0c1e17 100644<br>--- a/src/mainboard/traverse/geos/romstage.c<br>+++ b/src/mainboard/traverse/geos/romstage.c<br>@@ -26,8 +26,6 @@<br> #include <cpu/amd/lxdef.h><br> #include <southbridge/amd/cs5536/cs5536.h><br> #include <spd.h><br>-#include "southbridge/amd/cs5536/early_smbus.c"<br>-#include "southbridge/amd/cs5536/early_setup.c"<br> #include <northbridge/amd/lx/raminit.h><br> <br> int spd_read_byte(unsigned int device, unsigned int address)<br>diff --git a/src/mainboard/winent/pl6064/romstage.c b/src/mainboard/winent/pl6064/romstage.c<br>index 3399fc3..624163b 100644<br>--- a/src/mainboard/winent/pl6064/romstage.c<br>+++ b/src/mainboard/winent/pl6064/romstage.c<br>@@ -27,8 +27,6 @@<br> #include <cpu/amd/lxdef.h><br> #include <southbridge/amd/cs5536/cs5536.h><br> #include <spd.h><br>-#include "southbridge/amd/cs5536/early_smbus.c"<br>-#include "southbridge/amd/cs5536/early_setup.c"<br> #include <superio/winbond/common/winbond.h><br> #include <superio/winbond/w83627hf/w83627hf.h><br> #include <northbridge/amd/lx/raminit.h><br>diff --git a/src/mainboard/wyse/s50/romstage.c b/src/mainboard/wyse/s50/romstage.c<br>index 3ebd406..8fc797c 100644<br>--- a/src/mainboard/wyse/s50/romstage.c<br>+++ b/src/mainboard/wyse/s50/romstage.c<br>@@ -24,8 +24,7 @@<br> #include <cpu/x86/msr.h><br> #include <cpu/amd/gx2def.h><br> #include <spd.h><br>-#include "southbridge/amd/cs5536/early_smbus.c"<br>-#include "southbridge/amd/cs5536/early_setup.c"<br>+#include <southbridge/amd/cs5536/cs5536.h><br> <br> static inline int spd_read_byte(unsigned int device, unsigned int address)<br> {<br>diff --git a/src/southbridge/amd/cs5536/Kconfig b/src/southbridge/amd/cs5536/Kconfig<br>index 93e9787..6b06c33 100644<br>--- a/src/southbridge/amd/cs5536/Kconfig<br>+++ b/src/southbridge/amd/cs5536/Kconfig<br>@@ -16,3 +16,12 @@<br> config SOUTHBRIDGE_AMD_CS5536<br>   bool<br>  select UDELAY_TSC<br>+<br>+if SOUTHBRIDGE_AMD_CS5536<br>+<br>+config NO_EARLY_SMBUS<br>+  def_bool n<br>+   help<br>+   Skip the CS5536 early SMBUS initialization.<br>+<br>+endif<br>diff --git a/src/southbridge/amd/cs5536/Makefile.inc b/src/southbridge/amd/cs5536/Makefile.inc<br>index a274fe5..4bd88ac 100644<br>--- a/src/southbridge/amd/cs5536/Makefile.inc<br>+++ b/src/southbridge/amd/cs5536/Makefile.inc<br>@@ -15,6 +15,9 @@<br> <br> ifeq ($(CONFIG_SOUTHBRIDGE_AMD_CS5536),y)<br> <br>+romstage-y += early_smbus.c<br>+romstage-y += early_setup.c<br>+<br> ramstage-y += cs5536.c<br> ramstage-y += ide.c<br> ramstage-y += pirq.c<br>diff --git a/src/southbridge/amd/cs5536/cs5536.h b/src/southbridge/amd/cs5536/cs5536.h<br>index 7de9147..72dbd5c 100644<br>--- a/src/southbridge/amd/cs5536/cs5536.h<br>+++ b/src/southbridge/amd/cs5536/cs5536.h<br>@@ -442,6 +442,10 @@<br> #if defined(__PRE_RAM__)<br> void cs5536_setup_onchipuart(int uart);<br> void cs5536_disable_internal_uart(void);<br>+void cs5536_early_setup(void);<br>+<br>+void cs5536_enable_smbus(void);<br>+int smbus_read_byte(unsigned device, unsigned address);<br> #else<br> void chipsetinit(void);<br> #endif<br>diff --git a/src/southbridge/amd/cs5536/early_setup.c b/src/southbridge/amd/cs5536/early_setup.c<br>index 6c69222..0ccca36 100644<br>--- a/src/southbridge/amd/cs5536/early_setup.c<br>+++ b/src/southbridge/amd/cs5536/early_setup.c<br>@@ -19,6 +19,12 @@<br>  * AMD Geode GX Processor CS5536 Companion Device GeodeROM Porting Guide.<br>  */<br> <br>+#include <arch/io.h><br>+#include <cpu/x86/bist.h><br>+#include <cpu/x86/msr.h><br>+#include <cpu/amd/lxdef.h><br>+#include "cs5536.h"<br>+<br> /**<br>  * @brief Setup PCI IDSEL for CS5536<br>  */<br>@@ -244,7 +250,7 @@<br>  * and we don't want to hang on serial, so they are<br>  * commented out<br>  */<br>-static void cs5536_early_setup(void)<br>+void cs5536_early_setup(void)<br> {<br>   msr_t msr;<br> <br>diff --git a/src/southbridge/amd/cs5536/early_smbus.c b/src/southbridge/amd/cs5536/early_smbus.c<br>index e11b91f..ed2b942 100644<br>--- a/src/southbridge/amd/cs5536/early_smbus.c<br>+++ b/src/southbridge/amd/cs5536/early_smbus.c<br>@@ -13,12 +13,16 @@<br>  * GNU General Public License for more details.<br>  */<br> <br>+#include <arch/io.h><br> #include "cs5536.h"<br> #include "smbus.h"<br> <br> /* initialization for SMBus Controller */<br>-static void cs5536_enable_smbus(void)<br>+void cs5536_enable_smbus(void)<br> {<br>+<br>+    if (IS_ENABLED(CONFIG_NO_EARLY_SMBUS))<br>+               return;<br> <br>    /* Set SCL freq and enable SMB controller */<br>  /*outb((0x20 << 1) | SMB_CTRL2_ENABLE, smbus_io_base + SMB_CTRL2); */<br>@@ -29,7 +33,7 @@<br> <br> }<br> <br>-static inline int smbus_read_byte(unsigned device, unsigned address)<br>+int smbus_read_byte(unsigned device, unsigned address)<br> {<br>  return do_smbus_read_byte(SMBUS_IO_BASE, device, address);<br> }<br></pre><p>To view, visit <a href="https://review.coreboot.org/20607">change 20607</a>. To unsubscribe, visit <a href="https://review.coreboot.org/settings">settings</a>.</p><div itemscope itemtype="http://schema.org/EmailMessage"><div itemscope itemprop="action" itemtype="http://schema.org/ViewAction"><link itemprop="url" href="https://review.coreboot.org/20607"/><meta itemprop="name" content="View Change"/></div></div>

<div style="display:none"> Gerrit-Project: coreboot </div>
<div style="display:none"> Gerrit-Branch: master </div>
<div style="display:none"> Gerrit-MessageType: newchange </div>
<div style="display:none"> Gerrit-Change-Id: I2e6a9cd859292b4dd4720b547d1ff0bbb6c319cf </div>
<div style="display:none"> Gerrit-Change-Number: 20607 </div>
<div style="display:none"> Gerrit-PatchSet: 1 </div>
<div style="display:none"> Gerrit-Owner: Martin Roth <martinroth@google.com> </div>