<p>Lijian Zhao has uploaded this change for <strong>review</strong>.</p><p><a href="https://review.coreboot.org/20533">View Change</a></p><pre style="font-family: monospace,monospace; white-space: pre-wrap;">soc/intel/cannonlake: Add memory map support<br><br>Calculate the top of ram from output of Fsp reserved memory range.<br><br>Change-Id: I0dcc8f737c5811c9010cc4a20ea0126ab3f90f14<br>Signed-off-by: Lijian Zhao <lijian.zhao@intel.com><br>---<br>M src/soc/intel/cannonlake/Makefile.inc<br>A src/soc/intel/cannonlake/memmap.c<br>2 files changed, 144 insertions(+), 2 deletions(-)<br><br></pre><pre style="font-family: monospace,monospace; white-space: pre-wrap;">git pull ssh://review.coreboot.org:29418/coreboot refs/changes/33/20533/1</pre><pre style="font-family: monospace,monospace; white-space: pre-wrap;">diff --git a/src/soc/intel/cannonlake/Makefile.inc b/src/soc/intel/cannonlake/Makefile.inc<br>index 480e047..b0fe57f 100644<br>--- a/src/soc/intel/cannonlake/Makefile.inc<br>+++ b/src/soc/intel/cannonlake/Makefile.inc<br>@@ -12,11 +12,11 @@<br> bootblock-y += bootblock/report_platform.c<br> bootblock-y += gpio.c<br> <br>-romstage-y += cbmem.c<br>+romstage-y += memmap.c<br> romstage-y += reset.c<br> romstage-$(CONFIG_DRIVERS_UART_8250MEM) += uart.c<br> <br>-ramstage-y += cbmem.c<br>+ramstage-y += memmap.c<br> ramstage-$(CONFIG_PLATFORM_USES_FSP2_0) += reset.c<br> ramstage-$(CONFIG_DRIVERS_UART_8250MEM) += uart.c<br> <br>diff --git a/src/soc/intel/cannonlake/memmap.c b/src/soc/intel/cannonlake/memmap.c<br>new file mode 100644<br>index 0000000..fb9d5f8<br>--- /dev/null<br>+++ b/src/soc/intel/cannonlake/memmap.c<br>@@ -0,0 +1,142 @@<br>+/*<br>+ * This file is part of the coreboot project.<br>+ *<br>+ * Copyright (C) 2014 Google Inc.<br>+ * Copyright (C) 2015-2017 Intel Corporation.<br>+ *<br>+ * This program is free software; you can redistribute it and/or modify<br>+ * it under the terms of the GNU General Public License as published by<br>+ * the Free Software Foundation; version 2 of the License.<br>+ *<br>+ * This program is distributed in the hope that it will be useful,<br>+ * but WITHOUT ANY WARRANTY; without even the implied warranty of<br>+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the<br>+ * GNU General Public License for more details.<br>+ */<br>+<br>+#include <arch/io.h><br>+#include <cbmem.h><br>+#include <device/device.h><br>+#include <device/pci.h><br>+#include <fsp/util.h><br>+#include <soc/msr.h><br>+#include <soc/systemagent.h><br>+#include <soc/pci_devs.h><br>+#include <stdlib.h><br>+<br>+#ifdef __x86_64__<br>+#define CRx_IN "q"<br>+#define CRx_RET "=q"<br>+#else<br>+#define CRx_IN "r"<br>+#define CRx_RET "=r"<br>+#endif<br>+#define COMPILER_BARRIER "memory"<br>+<br>+static alwaysinline uint32_t read_xmm0(void)<br>+{<br>+ uint32_t value;<br>+ __asm__ __volatile__ (<br>+ "movd %%xmm0, %0"<br>+ : CRx_RET(value)<br>+ :<br>+ : COMPILER_BARRIER<br>+ );<br>+ return value;<br>+}<br>+<br>+static alwaysinline void write_xmm0(uint32_t data)<br>+{<br>+ __asm__ __volatile__ (<br>+ "movd %0, %%xmm0"<br>+ :<br>+ : CRx_IN(data)<br>+ : COMPILER_BARRIER<br>+ );<br>+}<br>+<br>+/*<br>+ * Host Memory Map:<br>+ *<br>+ * +--------------------------+ TOUUD<br>+ * | |<br>+ * +--------------------------+ 4GiB<br>+ * | PCI Address Space |<br>+ * +--------------------------+ TOLUD (also maps into MC address space)<br>+ * | iGD |<br>+ * +--------------------------+ BDSM<br>+ * | GTT |<br>+ * +--------------------------+ BGSM<br>+ * | TSEG |<br>+ * +--------------------------+ TSEGMB<br>+ * | DMA Protected Region |<br>+ * +--------------------------+ DPR<br>+ * | PRM (C6DRAM/SGX) |<br>+ * +--------------------------+ PRMRR<br>+ * | Trace Memory |<br>+ * +--------------------------+ top_of_ram<br>+ * | Reserved - FSP/CBMEM |<br>+ * +--------------------------+ TOLUM<br>+ * | Usage DRAM |<br>+ * +--------------------------+ 0<br>+ *<br>+ * Some of the base registers above can be equal making the size of those<br>+ * regions 0. The reason is because the memory controller internally subtracts<br>+ * the base registers from each other to determine sizes of the regions. In<br>+ * other words, the memory map is in a fixed order no matter what.<br>+ */<br>+<br>+u32 top_of_32bit_ram(void)<br>+{<br>+ u32 top_of_ram = 0;<br>+ struct range_entry fsp_mem;<br>+ u32 fsp_reserve_base;<br>+ int status;<br>+<br>+ /*<br>+ * Check if Tseg has been initialized, we will use this as a flag<br>+ * to check if the MRC is done, and only then continue to read the<br>+ * FSP Reserve Memory HOB.<br>+ */<br>+ status = fsp_find_reserved_memory(&fsp_mem);<br>+ if (status == 0) {<br>+ fsp_reserve_base = (u32)range_entry_base(&fsp_mem);<br>+ top_of_ram = ALIGN_UP((uintptr_t)fsp_reserve_base, 16*MiB);<br>+ write_xmm0(top_of_ram);<br>+ } else<br>+ top_of_ram = read_xmm0();<br>+<br>+ return top_of_ram;<br>+}<br>+<br>+void *cbmem_top(void)<br>+{<br>+ /*<br>+ * +-------------------------+ Top of RAM (aligned)<br>+ * | System Management Mode |<br>+ * | code and data | Length: CONFIG_TSEG_SIZE<br>+ * | (TSEG) |<br>+ * +-------------------------+ SMM base (aligned)<br>+ * | |<br>+ * | Chipset Reserved Memory |<br>+ * | |<br>+ * +-------------------------+ top_of_ram (aligned)<br>+ * | |<br>+ * | CBMEM Root |<br>+ * | |<br>+ * +-------------------------+<br>+ * | |<br>+ * | FSP Reserved Memory |<br>+ * | |<br>+ * +-------------------------+<br>+ * | |<br>+ * | Various CBMEM Entries |<br>+ * | |<br>+ * +-------------------------+ top_of_stack (8 byte aligned)<br>+ * | |<br>+ * | stack (CBMEM Entry) |<br>+ * | |<br>+ * +-------------------------+<br>+ */<br>+ return (void *)top_of_32bit_ram();<br>+}<br></pre><p>To view, visit <a href="https://review.coreboot.org/20533">change 20533</a>. To unsubscribe, visit <a href="https://review.coreboot.org/settings">settings</a>.</p><div itemscope itemtype="http://schema.org/EmailMessage"><div itemscope itemprop="action" itemtype="http://schema.org/ViewAction"><link itemprop="url" href="https://review.coreboot.org/20533"/><meta itemprop="name" content="View Change"/></div></div>
<div style="display:none"> Gerrit-Project: coreboot </div>
<div style="display:none"> Gerrit-Branch: master </div>
<div style="display:none"> Gerrit-MessageType: newchange </div>
<div style="display:none"> Gerrit-Change-Id: I0dcc8f737c5811c9010cc4a20ea0126ab3f90f14 </div>
<div style="display:none"> Gerrit-Change-Number: 20533 </div>
<div style="display:none"> Gerrit-PatchSet: 1 </div>
<div style="display:none"> Gerrit-Owner: Lijian Zhao <lijian.zhao@intel.com> </div>