<p>Subrata Banik has uploaded this change for <strong>review</strong>.</p><p><a href="https://review.coreboot.org/20462">View Change</a></p><pre style="font-family: monospace,monospace; white-space: pre-wrap;">Revert "soc/intel/skylake: storage: Add 2ms delay before exiting D3"<br><br>Don't need this additional 2ms delay as PCR read after sideband write<br>help to fix original hard hang issue.<br><br>This reverts commit d4b6ac19b0a6619ebe645875282643cc50cf7a3e.<br><br>Change-Id: I4232cba5b92e17f728795f7c282af6161e385e9b<br>Signed-off-by: Subrata Banik <subrata.banik@intel.com><br>---<br>M src/soc/intel/skylake/acpi/scs.asl<br>1 file changed, 0 insertions(+), 2 deletions(-)<br><br></pre><pre style="font-family: monospace,monospace; white-space: pre-wrap;">git pull ssh://review.coreboot.org:29418/coreboot refs/changes/62/20462/1</pre><pre style="font-family: monospace,monospace; white-space: pre-wrap;">diff --git a/src/soc/intel/skylake/acpi/scs.asl b/src/soc/intel/skylake/acpi/scs.asl<br>index 60c546b..235a57e 100644<br>--- a/src/soc/intel/skylake/acpi/scs.asl<br>+++ b/src/soc/intel/skylake/acpi/scs.asl<br>@@ -86,7 +86,6 @@<br> <br>               /* Set bits 31, 6, 2, 0 */<br>            ^^PCRO (PID_SCS, 0x600, 0x80000045)<br>-          Sleep (2)<br> <br>          /* Set Power State to D0 */<br>           And (PMCR, 0xFFFC, PMCR)<br>@@ -140,7 +139,6 @@<br> <br>              /* Set bits 8, 7, 2, 0 */<br>             ^^PCRO (PID_SCS, 0x600, 0x00000185)<br>-          Sleep (2)<br> <br>          /* Set Power State to D0 */<br>           And (PMCR, 0xFFFC, PMCR)<br></pre><p>To view, visit <a href="https://review.coreboot.org/20462">change 20462</a>. To unsubscribe, visit <a href="https://review.coreboot.org/settings">settings</a>.</p><div itemscope itemtype="http://schema.org/EmailMessage"><div itemscope itemprop="action" itemtype="http://schema.org/ViewAction"><link itemprop="url" href="https://review.coreboot.org/20462"/><meta itemprop="name" content="View Change"/></div></div>

<div style="display:none"> Gerrit-Project: coreboot </div>
<div style="display:none"> Gerrit-Branch: master </div>
<div style="display:none"> Gerrit-MessageType: newchange </div>
<div style="display:none"> Gerrit-Change-Id: I4232cba5b92e17f728795f7c282af6161e385e9b </div>
<div style="display:none"> Gerrit-Change-Number: 20462 </div>
<div style="display:none"> Gerrit-PatchSet: 1 </div>
<div style="display:none"> Gerrit-Owner: Subrata Banik <subrata.banik@intel.com> </div>
<div style="display:none"> Gerrit-Reviewer: Duncan Laurie <dlaurie@chromium.org> </div>