<p>Marshall Dawson has uploaded this change for <strong>review</strong>.</p><p><a href="https://review.coreboot.org/20529">View Change</a></p><pre style="font-family: monospace,monospace; white-space: pre-wrap;">///// add jadeites<br><br>Basic mainboard copy of gardenia. Use FT4, update devicetree for SIO<br>debug card and SPD addresses. This port is to be a test vehicle and<br>will be migrated alongside of gardenia during the transition to soc/.<br><br>Also add a legacy jadeite board that can be used to test cpu/nb/sb<br>at the same time.<br><br>This patch has been squashed with changes that incrementally update<br>for sb/cpu/nb.<br><br>Change-Id: Ic28b8f584e6b78435a5203192480d1288a337a88<br>---<br>A configs/config.jadeite<br>A src/mainboard/amd/jadeite/BiosCallOuts.c<br>A src/mainboard/amd/jadeite/BiosCallOuts.hh<br>A src/mainboard/amd/jadeite/Kconfig<br>A src/mainboard/amd/jadeite/Kconfig.name<br>A src/mainboard/amd/jadeite/Makefile.inc<br>A src/mainboard/amd/jadeite/OemCustomize.c<br>A src/mainboard/amd/jadeite/acpi/AmdImc.asl<br>A src/mainboard/amd/jadeite/acpi/carrizo_fch.asl<br>A src/mainboard/amd/jadeite/acpi/gpe.asl<br>A src/mainboard/amd/jadeite/acpi/mainboard.asl<br>A src/mainboard/amd/jadeite/acpi/routing.asl<br>A src/mainboard/amd/jadeite/acpi/sleep.asl<br>A src/mainboard/amd/jadeite/acpi/usb_oc.asl<br>A src/mainboard/amd/jadeite/acpi_tables.c<br>A src/mainboard/amd/jadeite/board_info.txt<br>A src/mainboard/amd/jadeite/bootblock/BiosCallOuts.c<br>A src/mainboard/amd/jadeite/bootblock/OemCustomize.c<br>A src/mainboard/amd/jadeite/chromeos.c<br>A src/mainboard/amd/jadeite/chromeos.fmd<br>A src/mainboard/amd/jadeite/cmos.layout<br>A src/mainboard/amd/jadeite/devicetree.cb<br>A src/mainboard/amd/jadeite/dsdt.asl<br>A src/mainboard/amd/jadeite/early_mainboard.c<br>A src/mainboard/amd/jadeite/fchec.c<br>A src/mainboard/amd/jadeite/fchec.h<br>A src/mainboard/amd/jadeite/irq_tables.c<br>A src/mainboard/amd/jadeite/mainboard.c<br>A src/mainboard/amd/jadeite/mptable.c<br>A src/mainboard/amd/jadeite/romstage.c<br>30 files changed, 1,990 insertions(+), 0 deletions(-)<br><br></pre><pre style="font-family: monospace,monospace; white-space: pre-wrap;">git pull ssh://review.coreboot.org:29418/coreboot refs/changes/29/20529/1</pre><pre style="font-family: monospace,monospace; white-space: pre-wrap;">diff --git a/configs/config.jadeite b/configs/config.jadeite<br>new file mode 100644<br>index 0000000..981c52b<br>--- /dev/null<br>+++ b/configs/config.jadeite<br>@@ -0,0 +1,4 @@<br>+CONFIG_VENDOR_AMD=y<br>+CONFIG_BOARD_AMD_JADEITE=y<br>+CONFIG_VGA_BIOS=y<br>+CONFIG_VGA_ROM_RUN=y<br>diff --git a/src/mainboard/amd/jadeite/BiosCallOuts.c b/src/mainboard/amd/jadeite/BiosCallOuts.c<br>new file mode 100644<br>index 0000000..fb32ad5<br>--- /dev/null<br>+++ b/src/mainboard/amd/jadeite/BiosCallOuts.c<br>@@ -0,0 +1,81 @@<br>+/*<br>+ * This file is part of the coreboot project.<br>+ *<br>+ * Copyright (C) 2015-2016 Advanced Micro Devices, Inc.<br>+ *<br>+ * This program is free software; you can redistribute it and/or modify<br>+ * it under the terms of the GNU General Public License as published by<br>+ * the Free Software Foundation; version 2 of the License.<br>+ *<br>+ * This program is distributed in the hope that it will be useful,<br>+ * but WITHOUT ANY WARRANTY; without even the implied warranty of<br>+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the<br>+ * GNU General Public License for more details.<br>+ */<br>+<br>+#include <AGESA.h><br>+#include <BiosCallOuts.h><br>+#include <FchPlatform.h><br>+#include <soc/imc.h><br>+#include <soc/hudson.h><br>+#include <stdlib.h><br>+<br>+static AGESA_STATUS Fch_Oem_config(UINT32 Func, UINTN FchData,<br>+ VOID *ConfigPtr)<br>+{<br>+ AMD_CONFIG_PARAMS *StdHeader = ConfigPtr;<br>+<br>+ if (StdHeader->Func == AMD_INIT_ENV) {<br>+ FCH_DATA_BLOCK *FchParams_env = (FCH_DATA_BLOCK *)FchData;<br>+ printk(BIOS_DEBUG, "Fch OEM config in INIT ENV ");<br>+ if (IS_ENABLED(CONFIG_STONEYRIDGE_IMC_FWM))<br>+ oem_fan_control(FchParams_env);<br>+<br>+ /* XHCI configuration */<br>+ if (IS_ENABLED(CONFIG_STONEYRIDGE_XHCI_ENABLE))<br>+ FchParams_env->Usb.Xhci0Enable = TRUE;<br>+ else<br>+ FchParams_env->Usb.Xhci0Enable = FALSE;<br>+ FchParams_env->Usb.Xhci1Enable = FALSE;<br>+ /* 8: If USB3 port is unremoveable. */<br>+ FchParams_env->Usb.USB30PortInit = 8;<br>+<br>+ /* SATA configuration */<br>+ FchParams_env->Sata.SataClass = CONFIG_STONEYRIDGE_SATA_MODE;<br>+ switch ((SATA_CLASS)CONFIG_STONEYRIDGE_SATA_MODE) {<br>+ case SataRaid:<br>+ case SataAhci:<br>+ case SataAhci7804:<br>+ case SataLegacyIde:<br>+ FchParams_env->Sata.SataIdeMode = FALSE;<br>+ break;<br>+ case SataIde2Ahci:<br>+ case SataIde2Ahci7804:<br>+ default: /* SataNativeIde */<br>+ FchParams_env->Sata.SataIdeMode = TRUE;<br>+ break;<br>+ }<br>+ }<br>+<br>+ printk(BIOS_DEBUG, "Done\n");<br>+<br>+ return AGESA_SUCCESS;<br>+}<br>+<br>+const BIOS_CALLOUT_STRUCT BiosCallouts[] =<br>+{<br>+ {AGESA_ALLOCATE_BUFFER, agesa_AllocateBuffer },<br>+ {AGESA_DEALLOCATE_BUFFER, agesa_DeallocateBuffer },<br>+ {AGESA_LOCATE_BUFFER, agesa_LocateBuffer },<br>+ {AGESA_READ_SPD, agesa_ReadSpd },<br>+ {AGESA_DO_RESET, agesa_Reset },<br>+ {AGESA_READ_SPD_RECOVERY, agesa_NoopUnsupported },<br>+ {AGESA_RUNFUNC_ONAP, agesa_RunFuncOnAp },<br>+ {AGESA_GET_IDS_INIT_DATA, agesa_EmptyIdsInitData },<br>+ {AGESA_HOOKBEFORE_DQS_TRAINING, agesa_NoopSuccess },<br>+ {AGESA_HOOKBEFORE_EXIT_SELF_REF, agesa_NoopSuccess },<br>+ {AGESA_FCH_OEM_CALLOUT, Fch_Oem_config },<br>+ {AGESA_GNB_GFX_GET_VBIOS_IMAGE, agesa_GfxGetVbiosImage }<br>+};<br>+<br>+const int BiosCalloutsLen = ARRAY_SIZE(BiosCallouts);<br>diff --git a/src/mainboard/amd/jadeite/BiosCallOuts.hh b/src/mainboard/amd/jadeite/BiosCallOuts.hh<br>new file mode 100644<br>index 0000000..8c2a047<br>--- /dev/null<br>+++ b/src/mainboard/amd/jadeite/BiosCallOuts.hh<br>@@ -0,0 +1,46 @@<br>+/*<br>+ * This file is part of the coreboot project.<br>+ *<br>+ * Copyright (C) 2015 Advanced Micro Devices, Inc.<br>+ *<br>+ * This program is free software; you can redistribute it and/or modify<br>+ * it under the terms of the GNU General Public License as published by<br>+ * the Free Software Foundation; version 2 of the License.<br>+ *<br>+ * This program is distributed in the hope that it will be useful,<br>+ * but WITHOUT ANY WARRANTY; without even the implied warranty of<br>+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the<br>+ * GNU General Public License for more details.<br>+ */<br>+<br>+#define FAN_INPUT_INTERNAL_DIODE 0<br>+#define FAN_INPUT_TEMP0 1<br>+#define FAN_INPUT_TEMP1 2<br>+#define FAN_INPUT_TEMP2 3<br>+#define FAN_INPUT_TEMP3 4<br>+#define FAN_INPUT_TEMP0_FILTER 5<br>+#define FAN_INPUT_ZERO 6<br>+#define FAN_INPUT_DISABLED 7<br>+<br>+#define FAN_AUTOMODE (1 << 0)<br>+#define FAN_LINEARMODE (1 << 1)<br>+#define FAN_STEPMODE ~(1 << 1)<br>+#define FAN_POLARITY_HIGH (1 << 2)<br>+#define FAN_POLARITY_LOW ~(1 << 2)<br>+<br>+/* Normally, 4-wire fan runs at 25KHz and 3-wire fan runs at 100Hz */<br>+#define FREQ_28KHZ 0x0<br>+#define FREQ_25KHZ 0x1<br>+#define FREQ_23KHZ 0x2<br>+#define FREQ_21KHZ 0x3<br>+#define FREQ_29KHZ 0x4<br>+#define FREQ_18KHZ 0x5<br>+#define FREQ_100HZ 0xF7<br>+#define FREQ_87HZ 0xF8<br>+#define FREQ_58HZ 0xF9<br>+#define FREQ_44HZ 0xFA<br>+#define FREQ_35HZ 0xFB<br>+#define FREQ_29HZ 0xFC<br>+#define FREQ_22HZ 0xFD<br>+#define FREQ_14HZ 0xFE<br>+#define FREQ_11HZ 0xFF<br>diff --git a/src/mainboard/amd/jadeite/Kconfig b/src/mainboard/amd/jadeite/Kconfig<br>new file mode 100644<br>index 0000000..f36cd56<br>--- /dev/null<br>+++ b/src/mainboard/amd/jadeite/Kconfig<br>@@ -0,0 +1,57 @@<br>+#<br>+# This file is part of the coreboot project.<br>+#<br>+# Copyright (C) 2015 Advanced Micro Devices, Inc.<br>+#<br>+# This program is free software; you can redistribute it and/or modify<br>+# it under the terms of the GNU General Public License as published by<br>+# the Free Software Foundation; version 2 of the License.<br>+#<br>+# This program is distributed in the hope that it will be useful,<br>+# but WITHOUT ANY WARRANTY; without even the implied warranty of<br>+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the<br>+# GNU General Public License for more details.<br>+#<br>+<br>+if BOARD_AMD_JADEITE<br>+<br>+config BOARD_SPECIFIC_OPTIONS # dummy<br>+ def_bool y<br>+ select SOC_AMD_STONEYRIDGE_FT4<br>+ select HAVE_OPTION_TABLE<br>+ select HAVE_PIRQ_TABLE<br>+ select SIO_ON_LPC<br>+ select NO_HUDSON_UART<br>+ select SUPERIO_SMSC_SIO1036<br>+ select HAVE_MP_TABLE<br>+ select HAVE_ACPI_TABLES<br>+ select BOARD_ROMSIZE_KB_8192<br>+ select GFXUMA<br>+ select STONEYRIDGE_IMC_FWM<br>+ select MAINBOARD_HAS_CHROMEOS<br>+<br>+config MAINBOARD_DIR<br>+ string<br>+ default amd/jadeite<br>+<br>+config MAINBOARD_PART_NUMBER<br>+ string<br>+ default "JADEITE"<br>+<br>+config MAX_CPUS<br>+ int<br>+ default 4<br>+<br>+config IRQ_SLOT_COUNT<br>+ int<br>+ default 11<br>+<br>+config ONBOARD_VGA_IS_PRIMARY<br>+ bool<br>+ default y<br>+<br>+config STONEYRIDGE_LEGACY_FREE<br>+ bool<br>+ default y<br>+<br>+endif # BOARD_AMD_JADEITE<br>diff --git a/src/mainboard/amd/jadeite/Kconfig.name b/src/mainboard/amd/jadeite/Kconfig.name<br>new file mode 100644<br>index 0000000..b41d8e8<br>--- /dev/null<br>+++ b/src/mainboard/amd/jadeite/Kconfig.name<br>@@ -0,0 +1,2 @@<br>+config BOARD_AMD_JADEITE<br>+ bool "Jadeite"<br>diff --git a/src/mainboard/amd/jadeite/Makefile.inc b/src/mainboard/amd/jadeite/Makefile.inc<br>new file mode 100644<br>index 0000000..5738a53<br>--- /dev/null<br>+++ b/src/mainboard/amd/jadeite/Makefile.inc<br>@@ -0,0 +1,32 @@<br>+#<br>+# This file is part of the coreboot project.<br>+#<br>+# Copyright (C) 2015 Advanced Micro Devices, Inc.<br>+#<br>+# This program is free software; you can redistribute it and/or modify<br>+# it under the terms of the GNU General Public License as published by<br>+# the Free Software Foundation; version 2 of the License.<br>+#<br>+# This program is distributed in the hope that it will be useful,<br>+# but WITHOUT ANY WARRANTY; without even the implied warranty of<br>+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the<br>+# GNU General Public License for more details.<br>+#<br>+<br>+bootblock-$(CONFIG_SUPERIO_SMSC_SIO1036) += ../../../superio/smsc/sio1036/sio1036_early_init.c<br>+bootblock-y += early_mainboard.c<br>+bootblock-y += bootblock/BiosCallOuts.c<br>+bootblock-y += bootblock/OemCustomize.c<br>+<br>+romstage-y += early_mainboard.c<br>+<br>+romstage-y += BiosCallOuts.c<br>+romstage-y += OemCustomize.c<br>+<br>+ramstage-y += BiosCallOuts.c<br>+ramstage-y += OemCustomize.c<br>+ramstage-$(CONFIG_STONEYRIDGE_IMC_FWM) += fchec.c<br>+<br>+verstage-y += chromeos.c<br>+romstage-y += chromeos.c<br>+ramstage-y += chromeos.c<br>diff --git a/src/mainboard/amd/jadeite/OemCustomize.c b/src/mainboard/amd/jadeite/OemCustomize.c<br>new file mode 100644<br>index 0000000..5c764f4<br>--- /dev/null<br>+++ b/src/mainboard/amd/jadeite/OemCustomize.c<br>@@ -0,0 +1,36 @@<br>+/*<br>+ * This file is part of the coreboot project.<br>+ *<br>+ * Copyright (C) 2015-2016 Advanced Micro Devices, Inc.<br>+ *<br>+ * This program is free software; you can redistribute it and/or modify<br>+ * it under the terms of the GNU General Public License as published by<br>+ * the Free Software Foundation; version 2 of the License.<br>+ *<br>+ * This program is distributed in the hope that it will be useful,<br>+ * but WITHOUT ANY WARRANTY; without even the implied warranty of<br>+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the<br>+ * GNU General Public License for more details.<br>+ */<br>+<br>+#include <agesawrapper.h><br>+#include <PlatformMemoryConfiguration.h><br>+<br>+#define FILECODE PROC_GNB_PCIE_FAMILY_0X15_F15PCIECOMPLEXCONFIG_FILECODE<br>+<br>+static const PSO_ENTRY DDR4PlatformMemoryConfiguration[] = {<br>+ DRAM_TECHNOLOGY(ANY_SOCKET, DDR4_TECHNOLOGY),<br>+ NUMBER_OF_DIMMS_SUPPORTED (ANY_SOCKET, ANY_CHANNEL, 2),<br>+ NUMBER_OF_CHANNELS_SUPPORTED (ANY_SOCKET, 2),<br>+ MOTHER_BOARD_LAYERS (LAYERS_6),<br>+ MEMCLK_DIS_MAP (ANY_SOCKET, ANY_CHANNEL, 0xff, 0xff, 0xff, 0xff, 0x00, 0x00, 0x00, 0x00),<br>+ CKE_TRI_MAP (ANY_SOCKET, ANY_CHANNEL, 0xff, 0xff, 0xff, 0xff),<br>+ ODT_TRI_MAP (ANY_SOCKET, ANY_CHANNEL, 0xff, 0xff, 0xff, 0xff),<br>+ CS_TRI_MAP (ANY_SOCKET, ANY_CHANNEL, 0xff, 0xff, 0xff, 0xff, 0x00, 0x00, 0x00, 0x00),<br>+ PSO_END<br>+};<br>+<br>+void OemPostParams(AMD_POST_PARAMS *PostParams)<br>+{<br>+ PostParams->MemConfig.PlatformMemoryConfiguration = (PSO_ENTRY *)DDR4PlatformMemoryConfiguration;<br>+}<br>diff --git a/src/mainboard/amd/jadeite/acpi/AmdImc.asl b/src/mainboard/amd/jadeite/acpi/AmdImc.asl<br>new file mode 100644<br>index 0000000..970858d<br>--- /dev/null<br>+++ b/src/mainboard/amd/jadeite/acpi/AmdImc.asl<br>@@ -0,0 +1,110 @@<br>+/*<br>+ * This file is part of the coreboot project.<br>+ *<br>+ * Copyright (C) 2015 Advanced Micro Devices, Inc.<br>+ *<br>+ * This program is free software; you can redistribute it and/or modify<br>+ * it under the terms of the GNU General Public License as published by<br>+ * the Free Software Foundation; version 2 of the License.<br>+ *<br>+ * This program is distributed in the hope that it will be useful,<br>+ * but WITHOUT ANY WARRANTY; without even the implied warranty of<br>+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the<br>+ * GNU General Public License for more details.<br>+ */<br>+<br>+//BTDC Due to IMC Fan, ACPI control codes<br>+OperationRegion(IMIO, SystemIO, 0x3E, 0x02)<br>+Field(IMIO , ByteAcc, NoLock, Preserve) {<br>+ IMCX,8,<br>+ IMCA,8<br>+}<br>+<br>+IndexField(IMCX, IMCA, ByteAcc, NoLock, Preserve) {<br>+ Offset(0x80),<br>+ MSTI, 8,<br>+ MITS, 8,<br>+ MRG0, 8,<br>+ MRG1, 8,<br>+ MRG2, 8,<br>+ MRG3, 8,<br>+}<br>+<br>+Method(WACK, 0)<br>+{<br>+ Store(0, Local0)<br>+ While (LNotEqual(Local0, 0xFA)) {<br>+ Store(MRG0, Local0)<br>+ Sleep(10)<br>+ }<br>+}<br>+<br>+//Init<br>+Method (ITZE, 0)<br>+{<br>+ Store(0, MRG0)<br>+ Store(0xB5, MRG1)<br>+ Store(0, MRG2)<br>+ Store(0x96, MSTI)<br>+ WACK()<br>+<br>+ Store(0, MRG0)<br>+ Store(0, MRG1)<br>+ Store(0, MRG2)<br>+ Store(0x80, MSTI)<br>+ WACK()<br>+<br>+ Or(MRG2, 0x01, Local0)<br>+<br>+ Store(0, MRG0)<br>+ Store(0, MRG1)<br>+ Store(Local0, MRG2)<br>+ Store(0x81, MSTI)<br>+ WACK()<br>+}<br>+<br>+//Sleep<br>+Method (IMSP, 0)<br>+{<br>+ Store(0, MRG0)<br>+ Store(0xB5, MRG1)<br>+ Store(0, MRG2)<br>+ Store(0x96, MSTI)<br>+ WACK()<br>+<br>+ Store(0, MRG0)<br>+ Store(1, MRG1)<br>+ Store(0, MRG2)<br>+ Store(0x98, MSTI)<br>+ WACK()<br>+<br>+ Store(0, MRG0)<br>+ Store(0xB4, MRG1)<br>+ Store(0, MRG2)<br>+ Store(0x96, MSTI)<br>+ WACK()<br>+}<br>+<br>+//Wake<br>+Method (IMWK, 0)<br>+{<br>+ Store(0, MRG0)<br>+ Store(0xB5, MRG1)<br>+ Store(0, MRG2)<br>+ Store(0x96, MSTI)<br>+ WACK()<br>+<br>+ Store(0, MRG0)<br>+ Store(0, MRG1)<br>+ Store(0, MRG2)<br>+ Store(0x80, MSTI)<br>+ WACK()<br>+<br>+ Or(MRG2, 0x01, Local0)<br>+<br>+ Store(0, MRG0)<br>+ Store(0, MRG1)<br>+ Store(Local0, MRG2)<br>+ Store(0x81, MSTI)<br>+ WACK()<br>+}<br>diff --git a/src/mainboard/amd/jadeite/acpi/carrizo_fch.asl b/src/mainboard/amd/jadeite/acpi/carrizo_fch.asl<br>new file mode 100644<br>index 0000000..954ab43<br>--- /dev/null<br>+++ b/src/mainboard/amd/jadeite/acpi/carrizo_fch.asl<br>@@ -0,0 +1,119 @@<br>+/*<br>+ * This file is part of the coreboot project.<br>+ *<br>+ * Copyright (C) 2015-2016 Advanced Micro Devices, Inc.<br>+ *<br>+ * This program is free software; you can redistribute it and/or modify<br>+ * it under the terms of the GNU General Public License as published by<br>+ * the Free Software Foundation; version 2 of the License.<br>+ *<br>+ * This program is distributed in the hope that it will be useful,<br>+ * but WITHOUT ANY WARRANTY; without even the implied warranty of<br>+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the<br>+ * GNU General Public License for more details.<br>+ */<br>+<br>+Device(AAHB) {<br>+ Name(_HID,"AAHB0000")<br>+ Name(_UID,0x0)<br>+ Name(_CRS, ResourceTemplate()<br>+ {<br>+ IRQ(Edge, ActiveHigh, Exclusive) {7}<br>+ Memory32Fixed(ReadWrite, 0xFEDC0000, 0x2000)<br>+ })<br>+<br>+ Method (_STA, 0x0, NotSerialized) {<br>+ Return (0x0F)<br>+ }<br>+}<br>+<br>+Device(GPIO) {<br>+ Name (_HID, "AMD0030")<br>+ Name (_CID, "AMD0030")<br>+ Name(_UID, 0)<br>+<br>+ Name(_CRS, ResourceTemplate() {<br>+ Interrupt(ResourceConsumer, Level, ActiveLow, Shared, , , ) {7}<br>+ Memory32Fixed(ReadWrite, 0xFED81500, 0x300)<br>+ })<br>+<br>+ Method (_STA, 0x0, NotSerialized) {<br>+ Return (0x0F)<br>+ }<br>+}<br>+<br>+Device(FUR0) {<br>+ Name(_HID,"AMD0020")<br>+ Name(_UID,0x0)<br>+ Name(_CRS, ResourceTemplate() {<br>+ IRQ(Edge, ActiveHigh, Exclusive) {10}<br>+ Memory32Fixed(ReadWrite, 0xFEDC6000, 0x2000)<br>+ })<br>+ Method (_STA, 0x0, NotSerialized) {<br>+ Return (0x0F)<br>+ }<br>+}<br>+<br>+Device(FUR1) {<br>+ Name(_HID,"AMD0020")<br>+ Name(_UID,0x1)<br>+ Name(_CRS, ResourceTemplate() {<br>+ IRQ(Edge, ActiveHigh, Exclusive) {11}<br>+ Memory32Fixed(ReadWrite, 0xFEDC8000, 0x2000)<br>+ })<br>+ Method (_STA, 0x0, NotSerialized) {<br>+ Return (0x0F)<br>+ }<br>+}<br>+<br>+Device(I2CA) {<br>+ Name(_HID,"AMD0010")<br>+ Name(_UID,0x0)<br>+ Name(_CRS, ResourceTemplate() {<br>+ IRQ(Edge, ActiveHigh, Exclusive) {3}<br>+ Memory32Fixed(ReadWrite, 0xFEDC2000, 0x1000)<br>+ })<br>+<br>+ Method (_STA, 0x0, NotSerialized) {<br>+ Return (0x0F)<br>+ }<br>+}<br>+<br>+Device(I2CB)<br>+{<br>+ Name(_HID,"AMD0010")<br>+ Name(_UID,0x1)<br>+ Name(_CRS, ResourceTemplate() {<br>+ IRQ(Edge, ActiveHigh, Exclusive) {15}<br>+ Memory32Fixed(ReadWrite, 0xFEDC3000, 0x1000)<br>+ })<br>+ Method (_STA, 0x0, NotSerialized) {<br>+ Return (0x0F)<br>+ }<br>+}<br>+<br>+Device(I2CC) {<br>+ Name(_HID,"AMD0010")<br>+ Name(_UID,0x0)<br>+ Name(_CRS, ResourceTemplate() {<br>+ IRQ(Edge, ActiveHigh, Exclusive) {6}<br>+ Memory32Fixed(ReadWrite, 0xFEDC4000, 0x1000)<br>+ })<br>+<br>+ Method (_STA, 0x0, NotSerialized) {<br>+ Return (0x0F)<br>+ }<br>+}<br>+<br>+Device(I2CD)<br>+{<br>+ Name(_HID,"AMD0010")<br>+ Name(_UID,0x1)<br>+ Name(_CRS, ResourceTemplate() {<br>+ IRQ(Edge, ActiveHigh, Exclusive) {14}<br>+ Memory32Fixed(ReadWrite, 0xFEDC5000, 0x1000)<br>+ })<br>+ Method (_STA, 0x0, NotSerialized) {<br>+ Return (0x0F)<br>+ }<br>+}<br>diff --git a/src/mainboard/amd/jadeite/acpi/gpe.asl b/src/mainboard/amd/jadeite/acpi/gpe.asl<br>new file mode 100644<br>index 0000000..9a84698<br>--- /dev/null<br>+++ b/src/mainboard/amd/jadeite/acpi/gpe.asl<br>@@ -0,0 +1,74 @@<br>+/*<br>+ * This file is part of the coreboot project.<br>+ *<br>+ * Copyright (C) 2013 Sage Electronic Engineering, LLC<br>+ *<br>+ * This program is free software; you can redistribute it and/or modify<br>+ * it under the terms of the GNU General Public License as published by<br>+ * the Free Software Foundation; version 2 of the License.<br>+ *<br>+ * This program is distributed in the hope that it will be useful,<br>+ * but WITHOUT ANY WARRANTY; without even the implied warranty of<br>+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the<br>+ * GNU General Public License for more details.<br>+ */<br>+<br>+Scope(\_GPE) { /* Start Scope GPE */<br>+<br>+ /* General event 3 */<br>+ Method(_L03) {<br>+ /* DBGO("\\_GPE\\_L00\n") */<br>+ Notify(\_SB.PWRB, 0x02) /* NOTIFY_DEVICE_WAKE */<br>+ }<br>+<br>+ /* Legacy PM event */<br>+ Method(_L08) {<br>+ /* DBGO("\\_GPE\\_L08\n") */<br>+ }<br>+<br>+ /* Temp warning (TWarn) event */<br>+ Method(_L09) {<br>+ /* DBGO("\\_GPE\\_L09\n") */<br>+ /* Notify (\_TZ.TZ00, 0x80) */<br>+ }<br>+<br>+ /* USB controller PME# */<br>+ Method(_L0B) {<br>+ /* DBGO("\\_GPE\\_L0B\n") */<br>+ Notify(\_SB.PCI0.UOH1, 0x02) /* NOTIFY_DEVICE_WAKE */<br>+ Notify(\_SB.PCI0.UOH2, 0x02) /* NOTIFY_DEVICE_WAKE */<br>+ Notify(\_SB.PCI0.UOH3, 0x02) /* NOTIFY_DEVICE_WAKE */<br>+ Notify(\_SB.PCI0.UOH4, 0x02) /* NOTIFY_DEVICE_WAKE */<br>+ Notify(\_SB.PCI0.UOH5, 0x02) /* NOTIFY_DEVICE_WAKE */<br>+ Notify(\_SB.PCI0.UOH6, 0x02) /* NOTIFY_DEVICE_WAKE */<br>+ Notify(\_SB.PCI0.XHC0, 0x02) /* NOTIFY_DEVICE_WAKE */<br>+ Notify(\_SB.PWRB, 0x02) /* NOTIFY_DEVICE_WAKE */<br>+ }<br>+<br>+ /* ExtEvent0 SCI event */<br>+ Method(_L10) {<br>+ /* DBGO("\\_GPE\\_L10\n") */<br>+ }<br>+<br>+ /* ExtEvent1 SCI event */<br>+ Method(_L11) {<br>+ /* DBGO("\\_GPE\\_L11\n") */<br>+ }<br>+<br>+ /* GPIO0 or GEvent8 event */<br>+ Method(_L18) {<br>+ /* DBGO("\\_GPE\\_L18\n") */<br>+ Notify(\_SB.PCI0.PBR4, 0x02) /* NOTIFY_DEVICE_WAKE */<br>+ Notify(\_SB.PCI0.PBR5, 0x02) /* NOTIFY_DEVICE_WAKE */<br>+ Notify(\_SB.PCI0.PBR6, 0x02) /* NOTIFY_DEVICE_WAKE */<br>+ Notify(\_SB.PCI0.PBR7, 0x02) /* NOTIFY_DEVICE_WAKE */<br>+ Notify(\_SB.PWRB, 0x02) /* NOTIFY_DEVICE_WAKE */<br>+ }<br>+<br>+ /* Azalia SCI event */<br>+ Method(_L1B) {<br>+ /* DBGO("\\_GPE\\_L1B\n") */<br>+ Notify(\_SB.PCI0.AZHD, 0x02) /* NOTIFY_DEVICE_WAKE */<br>+ Notify(\_SB.PWRB, 0x02) /* NOTIFY_DEVICE_WAKE */<br>+ }<br>+} /* End Scope GPE */<br>diff --git a/src/mainboard/amd/jadeite/acpi/mainboard.asl b/src/mainboard/amd/jadeite/acpi/mainboard.asl<br>new file mode 100644<br>index 0000000..508daa7<br>--- /dev/null<br>+++ b/src/mainboard/amd/jadeite/acpi/mainboard.asl<br>@@ -0,0 +1,30 @@<br>+/*<br>+ * This file is part of the coreboot project.<br>+ *<br>+ * Copyright (C) 2013 Sage Electronic Engineering, LLC<br>+ *<br>+ * This program is free software; you can redistribute it and/or modify<br>+ * it under the terms of the GNU General Public License as published by<br>+ * the Free Software Foundation; version 2 of the License.<br>+ *<br>+ * This program is distributed in the hope that it will be useful,<br>+ * but WITHOUT ANY WARRANTY; without even the implied warranty of<br>+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the<br>+ * GNU General Public License for more details.<br>+ */<br>+<br>+/* Memory related values */<br>+Name(LOMH, 0x0) /* Start of unused memory in C0000-E0000 range */<br>+Name(PBAD, 0x0) /* Address of BIOS area (If TOM2 != 0, Addr >> 16) */<br>+Name(PBLN, 0x0) /* Length of BIOS area */<br>+<br>+Name(PCBA, CONFIG_MMCONF_BASE_ADDRESS) /* Base address of PCIe config space */<br>+Name(PCLN, Multiply(0x100000, CONFIG_MMCONF_BUS_NUMBER)) /* Length of PCIe config space, 1MB each bus */<br>+Name(HPBA, 0xFED00000) /* Base address of HPET table */<br>+<br>+Name(SSFG, 0x0D) /* S1 support: bit 0, S2 Support: bit 1, etc. S0 & S5 assumed */<br>+<br>+/* Some global data */<br>+Name(OSVR, 3) /* Assume nothing. WinXp = 1, Vista = 2, Linux = 3, WinCE = 4 */<br>+Name(OSV, Ones) /* Assume nothing */<br>+Name(PMOD, One) /* Assume APIC */<br>diff --git a/src/mainboard/amd/jadeite/acpi/routing.asl b/src/mainboard/amd/jadeite/acpi/routing.asl<br>new file mode 100644<br>index 0000000..51cb612<br>--- /dev/null<br>+++ b/src/mainboard/amd/jadeite/acpi/routing.asl<br>@@ -0,0 +1,165 @@<br>+/*<br>+ * This file is part of the coreboot project.<br>+ *<br>+ * Copyright (C) 2015, 2016 Advanced Micro Devices, Inc.<br>+ * Copyright (C) 2013 Sage Electronic Engineering, LLC<br>+ *<br>+ * This program is free software; you can redistribute it and/or modify<br>+ * it under the terms of the GNU General Public License as published by<br>+ * the Free Software Foundation; version 2 of the License.<br>+ *<br>+ * This program is distributed in the hope that it will be useful,<br>+ * but WITHOUT ANY WARRANTY; without even the implied warranty of<br>+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the<br>+ * GNU General Public License for more details.<br>+ */<br>+<br>+/*<br>+DefinitionBlock ("DSDT.AML","DSDT",0x01,"XXXXXX","XXXXXXXX",0x00010001<br>+ )<br>+ {<br>+ #include "routing.asl"<br>+ }<br>+*/<br>+<br>+/* Routing is in System Bus scope */<br>+Name(PR0, Package(){<br>+ /* NB devices */<br>+ /* Bus 0, Dev 0 - F15 Host Controller */<br>+<br>+ /* Bus 0, Dev 1, Func 0 - PCI Bridge for Internal Graphics(IGP) */<br>+ /* Bus 0, Dev 1, Func 1 - HDMI Audio Controller */<br>+ Package(){0x0001FFFF, 0, INTB, 0 },<br>+ Package(){0x0001FFFF, 1, INTC, 0 },<br>+<br>+<br>+ /* Bus 0, Dev 2 Func 0,1,2,3,4,5 - PCIe Bridges */<br>+ Package(){0x0002FFFF, 0, INTC, 0 },<br>+ Package(){0x0002FFFF, 1, INTD, 0 },<br>+ Package(){0x0002FFFF, 2, INTA, 0 },<br>+ Package(){0x0002FFFF, 3, INTB, 0 },<br>+<br>+ /* FCH devices */<br>+ /* Bus 0, Dev 20 - F0:SMBus/ACPI;F3:LPC;F7:SD */<br>+ Package(){0x0014FFFF, 0, INTA, 0 },<br>+ Package(){0x0014FFFF, 1, INTB, 0 },<br>+ Package(){0x0014FFFF, 2, INTC, 0 },<br>+ Package(){0x0014FFFF, 3, INTD, 0 },<br>+<br>+ /* Bus 0, Dev 18 Func 0 - USB: EHCI */<br>+ Package(){0x0012FFFF, 0, INTC, 0 },<br>+ Package(){0x0012FFFF, 1, INTB, 0 },<br>+<br>+ /* Bus 0, Dev 10 Func 0 - USB: xHCI */<br>+ Package(){0x0010FFFF, 0, INTC, 0 },<br>+ Package(){0x0010FFFF, 1, INTB, 0 },<br>+<br>+ /* Bus 0, Dev 17 - SATA controller */<br>+ Package(){0x0011FFFF, 0, INTD, 0 },<br>+<br>+})<br>+<br>+Name(APR0, Package(){<br>+ /* NB devices in APIC mode */<br>+ /* Bus 0, Dev 0 - F15 Host Controller */<br>+<br>+ /* Bus 0, Dev 1 - PCI Bridge for Internal Graphics(IGP) */<br>+ Package(){0x0001FFFF, 0, 0, 43 },<br>+ Package(){0x0001FFFF, 1, 0, 40 },<br>+<br>+ /* Bus 0, Dev 2 - PCIe Bridges */<br>+ Package(){0x0002FFFF, 0, 0, 44 },<br>+ Package(){0x0002FFFF, 1, 0, 45 },<br>+ Package(){0x0002FFFF, 2, 0, 46 },<br>+ Package(){0x0002FFFF, 3, 0, 47 },<br>+<br>+ /* SB devices in APIC mode */<br>+ /* Bus 0, Dev 20 - F0:SMBus/ACPI;F3:LPC;F7:SD */<br>+ Package(){0x0014FFFF, 0, 0, 16 },<br>+ Package(){0x0014FFFF, 1, 0, 17 },<br>+ Package(){0x0014FFFF, 2, 0, 18 },<br>+ Package(){0x0014FFFF, 3, 0, 19 },<br>+<br>+ /* Bus 0, Dev 18 Func 0 - USB: EHCI */<br>+ Package(){0x0012FFFF, 0, 0, 18 },<br>+ Package(){0x0012FFFF, 1, 0, 17 },<br>+<br>+ /* Bus 0, Dev 10 Func 0 - USB: xHCI */<br>+ Package(){0x0010FFFF, 0, 0, 18},<br>+ Package(){0x0010FFFF, 1, 0, 17},<br>+<br>+ /* Bus 0, Dev 17 - SATA controller */<br>+ Package(){0x0011FFFF, 0, 0, 19 },<br>+})<br>+<br>+<br>+/* GPP 0 */<br>+Name(PS4, Package(){<br>+ Package(){0x0000FFFF, 0, INTA, 0 },<br>+ Package(){0x0000FFFF, 1, INTB, 0 },<br>+ Package(){0x0000FFFF, 2, INTC, 0 },<br>+ Package(){0x0000FFFF, 3, INTD, 0 },<br>+})<br>+Name(APS4, Package(){<br>+ /* PCIe slot - Hooked to PCIe slot 4 */<br>+ Package(){0x0000FFFF, 0, 0, 24 },<br>+ Package(){0x0000FFFF, 1, 0, 25 },<br>+ Package(){0x0000FFFF, 2, 0, 26 },<br>+ Package(){0x0000FFFF, 3, 0, 27 },<br>+})<br>+<br>+/* GPP 1 */<br>+Name(PS5, Package(){<br>+ Package(){0x0000FFFF, 0, INTB, 0 },<br>+ Package(){0x0000FFFF, 1, INTC, 0 },<br>+ Package(){0x0000FFFF, 2, INTD, 0 },<br>+ Package(){0x0000FFFF, 3, INTA, 0 },<br>+})<br>+Name(APS5, Package(){<br>+ Package(){0x0000FFFF, 0, 0, 28 },<br>+ Package(){0x0000FFFF, 1, 0, 29 },<br>+ Package(){0x0000FFFF, 2, 0, 30 },<br>+ Package(){0x0000FFFF, 3, 0, 31 },<br>+})<br>+<br>+/* GPP 2 */<br>+Name(PS6, Package(){<br>+ Package(){0x0000FFFF, 0, INTC, 0 },<br>+ Package(){0x0000FFFF, 1, INTD, 0 },<br>+ Package(){0x0000FFFF, 2, INTA, 0 },<br>+ Package(){0x0000FFFF, 3, INTB, 0 },<br>+})<br>+Name(APS6, Package(){<br>+ Package(){0x0000FFFF, 0, 0, 32 },<br>+ Package(){0x0000FFFF, 1, 0, 33 },<br>+ Package(){0x0000FFFF, 2, 0, 34 },<br>+ Package(){0x0000FFFF, 3, 0, 35 },<br>+})<br>+<br>+/* GPP 3 */<br>+Name(PS7, Package(){<br>+ Package(){0x0000FFFF, 0, INTD, 0 },<br>+ Package(){0x0000FFFF, 1, INTA, 0 },<br>+ Package(){0x0000FFFF, 2, INTB, 0 },<br>+ Package(){0x0000FFFF, 3, INTC, 0 },<br>+})<br>+Name(APS7, Package(){<br>+ Package(){0x0000FFFF, 0, 0, 36 },<br>+ Package(){0x0000FFFF, 1, 0, 37 },<br>+ Package(){0x0000FFFF, 2, 0, 38 },<br>+ Package(){0x0000FFFF, 3, 0, 39 },<br>+})<br>+<br>+/* GPP 4 */<br>+Name(PS8, Package(){<br>+ Package(){0x0000FFFF, 0, INTA, 0 },<br>+ Package(){0x0000FFFF, 1, INTB, 0 },<br>+ Package(){0x0000FFFF, 2, INTC, 0 },<br>+ Package(){0x0000FFFF, 3, INTD, 0 },<br>+})<br>+Name(APS8, Package(){<br>+ Package(){0x0000FFFF, 0, 0, 40 },<br>+ Package(){0x0000FFFF, 1, 0, 41 },<br>+ Package(){0x0000FFFF, 2, 0, 42 },<br>+ Package(){0x0000FFFF, 3, 0, 43 },<br>+})<br>diff --git a/src/mainboard/amd/jadeite/acpi/sleep.asl b/src/mainboard/amd/jadeite/acpi/sleep.asl<br>new file mode 100644<br>index 0000000..58f0752<br>--- /dev/null<br>+++ b/src/mainboard/amd/jadeite/acpi/sleep.asl<br>@@ -0,0 +1,86 @@<br>+/*<br>+ * This file is part of the coreboot project.<br>+ *<br>+ * Copyright (C) 2013 Sage Electronic Engineering, LLC<br>+ *<br>+ * This program is free software; you can redistribute it and/or modify<br>+ * it under the terms of the GNU General Public License as published by<br>+ * the Free Software Foundation; version 2 of the License.<br>+ *<br>+ * This program is distributed in the hope that it will be useful,<br>+ * but WITHOUT ANY WARRANTY; without even the implied warranty of<br>+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the<br>+ * GNU General Public License for more details.<br>+ */<br>+<br>+/* Wake status package */<br>+Name(WKST,Package(){Zero, Zero})<br>+<br>+/*<br>+* \_PTS - Prepare to Sleep method<br>+*<br>+* Entry:<br>+* Arg0=The value of the sleeping state S1=1, S2=2, etc<br>+*<br>+* Exit:<br>+* -none-<br>+*<br>+* The _PTS control method is executed at the beginning of the sleep process<br>+* for S1-S5. The sleeping value is passed to the _PTS control method. This<br>+* control method may be executed a relatively long time before entering the<br>+* sleep state and the OS may abort the operation without notification to<br>+* the ACPI driver. This method cannot modify the configuration or power<br>+* state of any device in the system.<br>+*/<br>+Method(_PTS, 1) {<br>+ /* DBGO("\\_PTS\n") */<br>+ /* DBGO("From S0 to S") */<br>+ /* DBGO(Arg0) */<br>+ /* DBGO("\n") */<br>+<br>+ /* Clear wake status structure. */<br>+ Store(0, PEWD)<br>+ Store(0, Index(WKST,0))<br>+ Store(0, Index(WKST,1))<br>+ Store(7, UPWS)<br>+} /* End Method(\_PTS) */<br>+<br>+/*<br>+* \_BFS OEM Back From Sleep method<br>+*<br>+* Entry:<br>+* Arg0=The value of the sleeping state S1=1, S2=2<br>+*<br>+* Exit:<br>+* -none-<br>+*/<br>+Method(\_BFS, 1) {<br>+ /* DBGO("\\_BFS\n") */<br>+ /* DBGO("From S") */<br>+ /* DBGO(Arg0) */<br>+ /* DBGO(" to S0\n") */<br>+}<br>+<br>+/*<br>+* \_WAK System Wake method<br>+*<br>+* Entry:<br>+* Arg0=The value of the sleeping state S1=1, S2=2<br>+*<br>+* Exit:<br>+* Return package of 2 DWords<br>+* Dword 1 - Status<br>+* 0x00000000 wake succeeded<br>+* 0x00000001 Wake was signaled but failed due to lack of power<br>+* 0x00000002 Wake was signaled but failed due to thermal condition<br>+* Dword 2 - Power Supply state<br>+* if non-zero the effective S-state the power supply entered<br>+*/<br>+Method(\_WAK, 1) {<br>+ /* DBGO("\\_WAK\n") */<br>+ /* DBGO("From S") */<br>+ /* DBGO(Arg0) */<br>+ /* DBGO(" to S0\n") */<br>+<br>+ Return(WKST)<br>+} /* End Method(\_WAK) */<br>diff --git a/src/mainboard/amd/jadeite/acpi/usb_oc.asl b/src/mainboard/amd/jadeite/acpi/usb_oc.asl<br>new file mode 100644<br>index 0000000..9566bc4<br>--- /dev/null<br>+++ b/src/mainboard/amd/jadeite/acpi/usb_oc.asl<br>@@ -0,0 +1,39 @@<br>+/*<br>+ * This file is part of the coreboot project.<br>+ *<br>+ * Copyright (C) 2015 Advanced Micro Devices, Inc.<br>+ * Copyright (C) 2013 Sage Electronic Engineering, LLC<br>+ *<br>+ * This program is free software; you can redistribute it and/or modify<br>+ * it under the terms of the GNU General Public License as published by<br>+ * the Free Software Foundation; version 2 of the License.<br>+ *<br>+ * This program is distributed in the hope that it will be useful,<br>+ * but WITHOUT ANY WARRANTY; without even the implied warranty of<br>+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the<br>+ * GNU General Public License for more details.<br>+ */<br>+<br>+/* simple name description */<br>+/*<br>+DefinitionBlock ("DSDT.AML","DSDT",0x01,"XXXXXX","XXXXXXXX",0x00010001<br>+ )<br>+ {<br>+ #include "usb.asl"<br>+ }<br>+*/<br>+<br>+/* USB overcurrent mapping pins. */<br>+Name(UOM0, 0)<br>+Name(UOM1, 2)<br>+Name(UOM2, 0)<br>+Name(UOM3, 7)<br>+Name(UOM4, 2)<br>+Name(UOM5, 2)<br>+Name(UOM6, 6)<br>+Name(UOM7, 2)<br>+Name(UOM8, 6)<br>+Name(UOM9, 6)<br>+<br>+/* USB Overcurrent GPEs */<br>+/* TODO: Update for Gardenia */<br>diff --git a/src/mainboard/amd/jadeite/acpi_tables.c b/src/mainboard/amd/jadeite/acpi_tables.c<br>new file mode 100644<br>index 0000000..a971f4c<br>--- /dev/null<br>+++ b/src/mainboard/amd/jadeite/acpi_tables.c<br>@@ -0,0 +1,61 @@<br>+/*<br>+ * This file is part of the coreboot project.<br>+ *<br>+ * Copyright (C) 2015 Advanced Micro Devices, Inc.<br>+ *<br>+ * This program is free software; you can redistribute it and/or modify<br>+ * it under the terms of the GNU General Public License as published by<br>+ * the Free Software Foundation; version 2 of the License.<br>+ *<br>+ * This program is distributed in the hope that it will be useful,<br>+ * but WITHOUT ANY WARRANTY; without even the implied warranty of<br>+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the<br>+ * GNU General Public License for more details.<br>+ */<br>+<br>+#include <agesawrapper.h><br>+<br>+#include <console/console.h><br>+#include <string.h><br>+#include <arch/acpi.h><br>+#include <arch/acpigen.h><br>+#include <arch/ioapic.h><br>+#include <device/pci.h><br>+#include <device/pci_ids.h><br>+#include <cpu/x86/msr.h><br>+#include <cpu/amd/mtrr.h><br>+#include <cpu/amd/amdfam16.h><br>+<br>+#if 1<br>+#define IO_APIC2_ADDR 0xFEC20000<br>+<br>+unsigned long acpi_fill_madt(unsigned long current)<br>+{<br>+ /* create all subtables for processors */<br>+ current = acpi_create_madt_lapics(current);<br>+<br>+ /* Write Kern IOAPIC, only one */<br>+ current += acpi_create_madt_ioapic((acpi_madt_ioapic_t *) current, CONFIG_MAX_CPUS,<br>+ IO_APIC_ADDR, 0);<br>+<br>+ /* TODO: Remove the hardcode */<br>+ current += acpi_create_madt_ioapic((acpi_madt_ioapic_t *) current, CONFIG_MAX_CPUS+1,<br>+ IO_APIC2_ADDR, 24);<br>+<br>+ current += acpi_create_madt_irqoverride((acpi_madt_irqoverride_t *)<br>+ current, 0, 0, 2, 0);<br>+ current += acpi_create_madt_irqoverride((acpi_madt_irqoverride_t *)<br>+ current, 0, 9, 9, 0xF);<br>+ /* 0: mean bus 0--->ISA */<br>+ /* 0: PIC 0 */<br>+ /* 2: APIC 2 */<br>+ /* 5 mean: 0101 --> Edge-triggered, Active high */<br>+<br>+ /* create all subtables for processors */<br>+ current += acpi_create_madt_lapic_nmi((acpi_madt_lapic_nmi_t *)current, 0xff, 5, 1);<br>+ /* 1: LINT1 connect to NMI */<br>+<br>+ return current;<br>+}<br>+<br>+#endif<br>diff --git a/src/mainboard/amd/jadeite/board_info.txt b/src/mainboard/amd/jadeite/board_info.txt<br>new file mode 100644<br>index 0000000..b351b8e<br>--- /dev/null<br>+++ b/src/mainboard/amd/jadeite/board_info.txt<br>@@ -0,0 +1 @@<br>+Category: eval<br>diff --git a/src/mainboard/amd/jadeite/bootblock/BiosCallOuts.c b/src/mainboard/amd/jadeite/bootblock/BiosCallOuts.c<br>new file mode 100644<br>index 0000000..5800511<br>--- /dev/null<br>+++ b/src/mainboard/amd/jadeite/bootblock/BiosCallOuts.c<br>@@ -0,0 +1,72 @@<br>+/*<br>+ * This file is part of the coreboot project.<br>+ *<br>+ * Copyright (C) 2015-2016 Advanced Micro Devices, Inc.<br>+ *<br>+ * This program is free software; you can redistribute it and/or modify<br>+ * it under the terms of the GNU General Public License as published by<br>+ * the Free Software Foundation; version 2 of the License.<br>+ *<br>+ * This program is distributed in the hope that it will be useful,<br>+ * but WITHOUT ANY WARRANTY; without even the implied warranty of<br>+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the<br>+ * GNU General Public License for more details.<br>+ */<br>+<br>+#include <AGESA.h><br>+#include <BiosCallOuts.h><br>+#include <FchPlatform.h><br>+#include <soc/hudson.h><br>+#include <stdlib.h><br>+<br>+static const GPIO_CONTROL oem_gardenia_gpio[] = {<br>+ /* BT radio disable */<br>+ {14, Function1, FCH_GPIO_PULL_UP_ENABLE | FCH_GPIO_OUTPUT_VALUE<br>+ | FCH_GPIO_OUTPUT_ENABLE},<br>+ /* NFC PU */<br>+ {64, Function0, FCH_GPIO_PULL_UP_ENABLE | FCH_GPIO_OUTPUT_VALUE<br>+ | FCH_GPIO_OUTPUT_ENABLE},<br>+ /* NFC wake */<br>+ {65, Function0, FCH_GPIO_PULL_UP_ENABLE | FCH_GPIO_OUTPUT_VALUE<br>+ | FCH_GPIO_OUTPUT_ENABLE},<br>+ /* Webcam */<br>+ {66, Function0, FCH_GPIO_PULL_UP_ENABLE | FCH_GPIO_OUTPUT_VALUE<br>+ | FCH_GPIO_OUTPUT_ENABLE},<br>+ /* PCIe presence detect */<br>+ {69, Function0, FCH_GPIO_PULL_UP_ENABLE},<br>+ /* GPS sleep */<br>+ {70, Function0, FCH_GPIO_PULL_UP_ENABLE | FCH_GPIO_OUTPUT_VALUE<br>+ | FCH_GPIO_OUTPUT_ENABLE},<br>+ /* MUX for Power Express Eval */<br>+ {116, Function1, FCH_GPIO_PULL_DOWN_ENABLE},<br>+ /* SD power */<br>+ {119, Function2, FCH_GPIO_PULL_UP_ENABLE | FCH_GPIO_OUTPUT_VALUE<br>+ | FCH_GPIO_OUTPUT_ENABLE},<br>+ {-1}<br>+};<br>+<br>+static AGESA_STATUS Fch_Oem_config (UINT32 Func, UINTN FchData,<br>+ VOID *ConfigPtr)<br>+{<br>+ AMD_CONFIG_PARAMS *StdHeader = ConfigPtr;<br>+ FCH_RESET_DATA_BLOCK *FchParams_reset;<br>+<br>+ if (StdHeader->Func == AMD_INIT_RESET) {<br>+ FchParams_reset = (FCH_RESET_DATA_BLOCK *)FchData;<br>+ printk(BIOS_DEBUG, "Fch OEM config in INIT RESET ");<br>+ FchParams_reset->FchReset.SataEnable = hudson_sata_enable();<br>+ FchParams_reset->FchReset.IdeEnable = hudson_ide_enable();<br>+ FchParams_reset->EarlyOemGpioTable = oem_gardenia_gpio;<br>+ }<br>+ printk(BIOS_DEBUG, "Done\n");<br>+<br>+ return AGESA_SUCCESS;<br>+}<br>+<br>+const BIOS_CALLOUT_STRUCT BiosCallouts[] =<br>+{<br>+ {AGESA_FCH_OEM_CALLOUT, Fch_Oem_config },<br>+};<br>+<br>+const int BiosCalloutsLen = ARRAY_SIZE(BiosCallouts);<br>+<br>diff --git a/src/mainboard/amd/jadeite/bootblock/OemCustomize.c b/src/mainboard/amd/jadeite/bootblock/OemCustomize.c<br>new file mode 100644<br>index 0000000..1d3a018<br>--- /dev/null<br>+++ b/src/mainboard/amd/jadeite/bootblock/OemCustomize.c<br>@@ -0,0 +1,152 @@<br>+/*<br>+ * This file is part of the coreboot project.<br>+ *<br>+ * Copyright (C) 2015-2016 Advanced Micro Devices, Inc.<br>+ *<br>+ * This program is free software; you can redistribute it and/or modify<br>+ * it under the terms of the GNU General Public License as published by<br>+ * the Free Software Foundation; version 2 of the License.<br>+ *<br>+ * This program is distributed in the hope that it will be useful,<br>+ * but WITHOUT ANY WARRANTY; without even the implied warranty of<br>+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the<br>+ * GNU General Public License for more details.<br>+ */<br>+<br>+#include <agesawrapper.h><br>+#include <PlatformMemoryConfiguration.h><br>+<br>+#define FILECODE PROC_GNB_PCIE_FAMILY_0X15_F15PCIECOMPLEXCONFIG_FILECODE<br>+<br>+static const PCIe_PORT_DESCRIPTOR PortList [] = {<br>+ /* Initialize Port descriptor (PCIe port, Lanes 7:4, D2F1) for x4 slot */<br>+ {<br>+ 0,<br>+ PCIE_ENGINE_DATA_INITIALIZER (PcieUnusedEngine, 4, 7),<br>+ PCIE_PORT_DATA_INITIALIZER_V2 (PortEnabled, ChannelTypeExt6db, 2, 1,<br>+ HotplugDisabled,<br>+ PcieGenMaxSupported,<br>+ PcieGenMaxSupported,<br>+ AspmL0sL1, 0x04, 0)<br>+ },<br>+ /* Initialize Port descriptor (PCIe port, Lanes 1:0, D2F2) for M.2 */<br>+ {<br>+ 0,<br>+ PCIE_ENGINE_DATA_INITIALIZER (PcieUnusedEngine, 0, 1),<br>+ PCIE_PORT_DATA_INITIALIZER_V2 (PortDisabled, ChannelTypeExt6db, 2, 2,<br>+ HotplugDisabled,<br>+ PcieGenMaxSupported,<br>+ PcieGenMaxSupported,<br>+ AspmL0sL1, 0x17, 0)<br>+ },<br>+ {<br>+ 0,<br>+ PCIE_ENGINE_DATA_INITIALIZER (PcieUnusedEngine, 1, 1),<br>+ PCIE_PORT_DATA_INITIALIZER_V2 (PortDisabled, ChannelTypeExt6db, 2, 3,<br>+ HotplugDisabled,<br>+ PcieGenMaxSupported,<br>+ PcieGenMaxSupported,<br>+ AspmL0sL1, 0x17, 0)<br>+ },<br>+ /* Initialize Port descriptor (PCIe port, Lane 2, D2F4) for x1 slot */<br>+ {<br>+ 0,<br>+ PCIE_ENGINE_DATA_INITIALIZER (PciePortEngine, 2, 2),<br>+ PCIE_PORT_DATA_INITIALIZER_V2 (PortEnabled, ChannelTypeExt6db, 2, 4,<br>+ HotplugDisabled,<br>+ PcieGenMaxSupported,<br>+ PcieGenMaxSupported,<br>+ AspmL0sL1, 0x13, 0)<br>+ },<br>+ /* Initialize Port descriptor (PCIe port, Lane3, D2F5) for SD */<br>+ {<br>+ DESCRIPTOR_TERMINATE_LIST,<br>+ PCIE_ENGINE_DATA_INITIALIZER (PciePortEngine, 3, 3),<br>+ PCIE_PORT_DATA_INITIALIZER_V2 (PortEnabled, ChannelTypeExt6db, 2, 5,<br>+ HotplugDisabled,<br>+ PcieGenMaxSupported,<br>+ PcieGenMaxSupported,<br>+ AspmL0sL1, 0x16, 0)<br>+ },<br>+ /* Initialize Port descriptor (PCIe port, Lane 1, D2F3) for M.2 */<br>+};<br>+<br>+static const PCIe_DDI_DESCRIPTOR DdiList [] = {<br>+ /* DDI0 - eDP */<br>+ {<br>+ 0,<br>+ PCIE_ENGINE_DATA_INITIALIZER (PcieDdiEngine, 8, 11),<br>+ PCIE_DDI_DATA_INITIALIZER (ConnectorTypeEDP, Aux1, Hdp1)<br>+ },<br>+ /* DDI1 - DP */<br>+ {<br>+ 0,<br>+ PCIE_ENGINE_DATA_INITIALIZER (PcieDdiEngine, 12, 15),<br>+ PCIE_DDI_DATA_INITIALIZER (ConnectorTypeHDMI, Aux2, Hdp2)<br>+ },<br>+ /* DDI2 - HDMI */<br>+ {<br>+ DESCRIPTOR_TERMINATE_LIST,<br>+ PCIE_ENGINE_DATA_INITIALIZER (PcieDdiEngine, 16, 19),<br>+ PCIE_DDI_DATA_INITIALIZER (ConnectorTypeDP, Aux3, Hdp3)<br>+ },<br>+};<br>+<br>+static const PCIe_COMPLEX_DESCRIPTOR PcieComplex = {<br>+ .Flags = DESCRIPTOR_TERMINATE_LIST,<br>+ .SocketId = 0,<br>+ .PciePortList = PortList,<br>+ .DdiLinkList = DdiList<br>+};<br>+<br>+static const UINT32 AzaliaCodecAlc286Table[] =<br>+{<br>+ 0x00172051, 0x001721C7, 0x00172222, 0x00172310,<br>+ 0x0017FF00, 0x0017FF00, 0x0017FF00, 0x0017FF00,<br>+ 0x01271C50, 0x01271D01, 0x01271EA6, 0x01271FB7,<br>+ 0x01371C00, 0x01371D00, 0x01371E00, 0x01371F40,<br>+ 0x01471C10, 0x01471D01, 0x01471E17, 0x01471F90,<br>+ 0x01771CF0, 0x01771D11, 0x01771E11, 0x01771F41,<br>+ 0x01871C40, 0x01871D10, 0x01871EA1, 0x01871F04,<br>+ 0x01971CF0, 0x01971D11, 0x01971E11, 0x01971F41,<br>+ 0x01A71CF0, 0x01A71D11, 0x01A71E11, 0x01A71F41,<br>+ 0x01D71C2D, 0x01D71DA5, 0x01D71E67, 0x01D71F40,<br>+ 0x01E71C30, 0x01E71D11, 0x01E71E45, 0x01E71F04,<br>+ 0x02171C20, 0x02171D10, 0x02171E21, 0x02171F04,<br>+ 0x02050071, 0x02040014, 0x02050010, 0x02040C22,<br>+ 0x0205004F, 0x0204B029, 0x0205002B, 0x02040C50,<br>+ 0x0205002D, 0x02041020, 0x02050020, 0x02040000,<br>+ 0x02050019, 0x02040817, 0x02050035, 0x02041AA5,<br>+ 0x02050063, 0x02042906, 0x02050063, 0x02042906,<br>+ 0xffffffff<br>+};<br>+<br>+CONST CODEC_VERB_TABLE_LIST CodecTableList[] =<br>+{<br>+ { (UINT32) 0x10ec0286, AzaliaCodecAlc286Table},<br>+ { (UINT32) 0x0FFFFFFFF, (UINT32 *)0x0FFFFFFFF}<br>+};<br>+<br>+/*---------------------------------------------------------------------------------------*/<br>+/**<br>+ * OemCustomizeInitEarly<br>+ *<br>+ * Description:<br>+ * This is the stub function will call the host environment through the binary block<br>+ * interface (call-out port) to provide a user hook opportunity<br>+ *<br>+ * Parameters:<br>+ * @param[in] **PeiServices<br>+ * @param[in] *InitEarly<br>+ *<br>+ * @retval VOID<br>+ *<br>+ **/<br>+/*---------------------------------------------------------------------------------------*/<br>+VOID OemCustomizeInitEarly (<br>+ IN OUT AMD_EARLY_PARAMS *InitEarly<br>+ )<br>+{<br>+ InitEarly->GnbConfig.PcieComplexList = &PcieComplex;<br>+ InitEarly->PlatformConfig.AzaliaCodecVerbTable = (UINT64)(UINTN)CodecTableList;<br>+}<br>diff --git a/src/mainboard/amd/jadeite/chromeos.c b/src/mainboard/amd/jadeite/chromeos.c<br>new file mode 100644<br>index 0000000..d2ce99f<br>--- /dev/null<br>+++ b/src/mainboard/amd/jadeite/chromeos.c<br>@@ -0,0 +1,42 @@<br>+/*<br>+ * This file is part of the coreboot project.<br>+ *<br>+ * Copyright (C) 2014 Google Inc.<br>+ * Copyright (C) 2016 Intel Corporation.<br>+ * Copyright (C) 2017 Advanced Micro Devices, Inc.<br>+ *<br>+ * This program is free software; you can redistribute it and/or modify<br>+ * it under the terms of the GNU General Public License as published by<br>+ * the Free Software Foundation; version 2 of the License.<br>+ *<br>+ * This program is distributed in the hope that it will be useful,<br>+ * but WITHOUT ANY WARRANTY; without even the implied warranty of<br>+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the<br>+ * GNU General Public License for more details.<br>+ */<br>+<br>+#include <vendorcode/google/chromeos/chromeos.h><br>+#include <boot/coreboot_tables.h><br>+#include <console/console.h><br>+<br>+<br>+void fill_lb_gpios(struct lb_gpios *gpios)<br>+{<br>+// struct lb_gpio chromeos_gpios[] = {<br>+// {-1, ACTIVE_HIGH, get_write_protect_state(), "write protect"},<br>+// {-1, ACTIVE_HIGH, get_recovery_mode_switch(), "recovery"},<br>+// {-1, ACTIVE_HIGH, get_lid_switch(), "lid"},<br>+// {-1, ACTIVE_HIGH, 0, "power"},<br>+// };<br>+// lb_add_gpios(gpios, chromeos_gpios, ARRAY_SIZE(chromeos_gpios));<br>+}<br>+<br>+int get_recovery_mode_switch(void)<br>+{<br>+ return 0;<br>+}<br>+<br>+int get_write_protect_state(void)<br>+{<br>+ return 0;<br>+}<br>diff --git a/src/mainboard/amd/jadeite/chromeos.fmd b/src/mainboard/amd/jadeite/chromeos.fmd<br>new file mode 100644<br>index 0000000..52aa37e<br>--- /dev/null<br>+++ b/src/mainboard/amd/jadeite/chromeos.fmd<br>@@ -0,0 +1,36 @@<br>+FLASH@0xff800000 0x800000 {<br>+SI_ALL@0x0 0xCB000 {<br>+ UNUSED@0x00000 0x20000<br>+ AMD_FW@0x20000 0xAB000<br>+ }<br>+SI_BIOS@0xCB000 0x735000 {<br>+ RW_SECTION_A@0x0 0x21e000 {<br>+ VBLOCK_A@0x0 0x10000<br>+ FW_MAIN_A(CBFS)@0x10000 0x20DFC0<br>+ RW_FWID_A@0x21dfc0 0x40<br>+ }<br>+ RW_SECTION_B@0x21e000 0x21e000 {<br>+ VBLOCK_B@0x0 0x10000<br>+ FW_MAIN_B(CBFS)@0x10000 0x20DFC0<br>+ RW_FWID_B@0x21dfc0 0x40<br>+ }<br>+ RW_MRC_CACHE@0x43C000 0x10000<br>+ RW_ELOG@0x44C000 0x4000<br>+ RW_SHARED@0x450000 0x4000 {<br>+ SHARED_DATA@0x0 0x2000<br>+ VBLOCK_DEV@0x2000 0x2000<br>+ }<br>+ RW_VPD@0x454000 0x2000<br>+ RW_UNUSED@0x456000 0x4F000<br>+# RW_LEGACY(CBFS)@0x200000 0x200000<br>+ WP_RO@0x4A5000 0x290000 {<br>+ RO_SECTION@0x00000 0x290000 {<br>+ FMAP@0x0 0x800<br>+ RO_FRID@0x800 0x40<br>+ RO_FRID_PAD@0x840 0x7c0<br>+ GBB@0x1000 0x70000<br>+ COREBOOT(CBFS)@0x80000 0x210000<br>+ }<br>+ }<br>+ }<br>+}<br>diff --git a/src/mainboard/amd/jadeite/cmos.layout b/src/mainboard/amd/jadeite/cmos.layout<br>new file mode 100644<br>index 0000000..c1338d3<br>--- /dev/null<br>+++ b/src/mainboard/amd/jadeite/cmos.layout<br>@@ -0,0 +1,109 @@<br>+#*****************************************************************************<br>+#<br>+# This file is part of the coreboot project.<br>+#<br>+# Copyright (C) 2015 Advanced Micro Devices, Inc.<br>+#<br>+# This program is free software; you can redistribute it and/or modify<br>+# it under the terms of the GNU General Public License as published by<br>+# the Free Software Foundation; version 2 of the License.<br>+#<br>+# This program is distributed in the hope that it will be useful,<br>+# but WITHOUT ANY WARRANTY; without even the implied warranty of<br>+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the<br>+# GNU General Public License for more details.<br>+#*****************************************************************************<br>+<br>+entries<br>+<br>+#start-bit length config config-ID name<br>+#0 8 r 0 seconds<br>+#8 8 r 0 alarm_seconds<br>+#16 8 r 0 minutes<br>+#24 8 r 0 alarm_minutes<br>+#32 8 r 0 hours<br>+#40 8 r 0 alarm_hours<br>+#48 8 r 0 day_of_week<br>+#56 8 r 0 day_of_month<br>+#64 8 r 0 month<br>+#72 8 r 0 year<br>+#80 4 r 0 rate_select<br>+#84 3 r 0 REF_Clock<br>+#87 1 r 0 UIP<br>+#88 1 r 0 auto_switch_DST<br>+#89 1 r 0 24_hour_mode<br>+#90 1 r 0 binary_values_enable<br>+#91 1 r 0 square-wave_out_enable<br>+#92 1 r 0 update_finished_enable<br>+#93 1 r 0 alarm_interrupt_enable<br>+#94 1 r 0 periodic_interrupt_enable<br>+#95 1 r 0 disable_clock_updates<br>+#96 288 r 0 temporary_filler<br>+0 384 r 0 reserved_memory<br>+384 1 e 4 boot_option<br>+386 1 e 1 ECC_memory<br>+388 4 h 0 reboot_counter<br>+392 3 e 5 baud_rate<br>+395 1 e 1 hw_scrubber<br>+396 1 e 1 interleave_chip_selects<br>+397 2 e 8 max_mem_clock<br>+399 1 e 2 multi_core<br>+400 1 e 1 power_on_after_fail<br>+412 4 e 6 debug_level<br>+416 4 e 7 boot_first<br>+420 4 e 7 boot_second<br>+424 4 e 7 boot_third<br>+428 4 h 0 boot_index<br>+432 8 h 0 boot_countdown<br>+440 4 e 9 slow_cpu<br>+444 1 e 1 nmi<br>+445 1 e 1 iommu<br>+728 256 h 0 user_data<br>+984 16 h 0 check_sum<br>+# Reserve the extended AMD configuration registers<br>+1000 24 r 0 amd_reserved<br>+<br>+enumerations<br>+<br>+#ID value text<br>+1 0 Disable<br>+1 1 Enable<br>+2 0 Enable<br>+2 1 Disable<br>+4 0 Fallback<br>+4 1 Normal<br>+5 0 115200<br>+5 1 57600<br>+5 2 38400<br>+5 3 19200<br>+5 4 9600<br>+5 5 4800<br>+5 6 2400<br>+5 7 1200<br>+6 6 Notice<br>+6 7 Info<br>+6 8 Debug<br>+6 9 Spew<br>+7 0 Network<br>+7 1 HDD<br>+7 2 Floppy<br>+7 8 Fallback_Network<br>+7 9 Fallback_HDD<br>+7 10 Fallback_Floppy<br>+#7 3 ROM<br>+8 0 400Mhz<br>+8 1 333Mhz<br>+8 2 266Mhz<br>+8 3 200Mhz<br>+9 0 off<br>+9 1 87.5%<br>+9 2 75.0%<br>+9 3 62.5%<br>+9 4 50.0%<br>+9 5 37.5%<br>+9 6 25.0%<br>+9 7 12.5%<br>+<br>+checksums<br>+<br>+checksum 392 983 984<br>diff --git a/src/mainboard/amd/jadeite/devicetree.cb b/src/mainboard/amd/jadeite/devicetree.cb<br>new file mode 100644<br>index 0000000..03bf9f7<br>--- /dev/null<br>+++ b/src/mainboard/amd/jadeite/devicetree.cb<br>@@ -0,0 +1,61 @@<br>+#<br>+# This file is part of the coreboot project.<br>+#<br>+# Copyright (C) 2015-2017 Advanced Micro Devices, Inc.<br>+#<br>+# This program is free software; you can redistribute it and/or modify<br>+# it under the terms of the GNU General Public License as published by<br>+# the Free Software Foundation; version 2 of the License.<br>+#<br>+# This program is distributed in the hope that it will be useful,<br>+# but WITHOUT ANY WARRANTY; without even the implied warranty of<br>+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the<br>+# GNU General Public License for more details.<br>+#<br>+chip soc/amd/stoneyridge<br>+<br>+ register "spdAddrLookup" = "<br>+ {<br>+ { {0xA0, 0xA2} }, // socket 0 - Channel 0, slots 0 & 1<br>+ }"<br>+<br>+ device cpu_cluster 0 on<br>+ device lapic 10 on end<br>+ end<br>+ device domain 0 on<br>+ subsystemid 0x1022 0x1410 inherit<br>+ device pci 0.0 on end # Root Complex<br>+ device pci 1.0 on end # Internal Graphics P2P bridge 0x98e4<br>+ device pci 1.1 on end # Internal Multimedia<br>+ device pci 2.0 on end # PCIe Host Bridge<br>+ device pci 2.1 on end # x4 PCIe slot<br>+ device pci 2.2 on end # M.2 slot<br>+ device pci 2.3 on end # M.2 slot<br>+ device pci 2.4 on end # x1 PCIe slot<br>+ device pci 2.5 on end # Cardreader<br>+ # devices on the NB/SB Link, but on the same pci bus<br>+ device pci 9.0 on end # PCIe Host Bridge<br>+ device pci 9.2 on end # HDA<br>+ device pci 10.0 on end # xHCI<br>+ device pci 11.0 on end # SATA<br>+ device pci 12.0 on end # EHCI<br>+ device pci 14.0 on # SM<br>+ chip drivers/generic/generic # dimm 0-0-0<br>+ device i2c 50 on end<br>+ end<br>+ chip drivers/generic/generic # dimm 0-0-1<br>+ device i2c 51 on end<br>+ end<br>+ chip superio/smsc/sio1036 # optional debug c<br>+ end<br>+ end # SM<br>+ device pci 14.3 on end # LPC 0x790e<br>+ device pci 14.7 on end # SD<br>+ device pci 18.0 on end<br>+ device pci 18.1 on end<br>+ device pci 18.2 on end<br>+ device pci 18.3 on end<br>+ device pci 18.4 on end<br>+ device pci 18.5 on end<br>+ end #domain<br>+end #chip soc/amd/stoneyridge<br>diff --git a/src/mainboard/amd/jadeite/dsdt.asl b/src/mainboard/amd/jadeite/dsdt.asl<br>new file mode 100644<br>index 0000000..a9f188e<br>--- /dev/null<br>+++ b/src/mainboard/amd/jadeite/dsdt.asl<br>@@ -0,0 +1,83 @@<br>+/*<br>+ * This file is part of the coreboot project.<br>+ *<br>+ * Copyright (C) 2015 Advanced Micro Devices, Inc.<br>+ *<br>+ * This program is free software; you can redistribute it and/or modify<br>+ * it under the terms of the GNU General Public License as published by<br>+ * the Free Software Foundation; version 2 of the License.<br>+ *<br>+ * This program is distributed in the hope that it will be useful,<br>+ * but WITHOUT ANY WARRANTY; without even the implied warranty of<br>+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the<br>+ * GNU General Public License for more details.<br>+ */<br>+<br>+/* DefinitionBlock Statement */<br>+DefinitionBlock (<br>+ "DSDT.AML", /* Output filename */<br>+ "DSDT", /* Signature */<br>+ 0x02, /* DSDT Revision, needs to be 2 for 64bit */<br>+ "AMD ", /* OEMID */<br>+ "COREBOOT", /* TABLE ID */<br>+ 0x00010001 /* OEM Revision */<br>+ )<br>+{ /* Start of ASL file */<br>+ /* #include <arch/x86/acpi/debug.asl> */ /* Include global debug methods if needed */<br>+<br>+ /* Globals for the platform */<br>+ #include "acpi/mainboard.asl"<br>+<br>+ /* Describe the USB Overcurrent pins */<br>+ #include "acpi/usb_oc.asl"<br>+<br>+ /* PCI IRQ mapping for the Southbridge */<br>+ #include <soc/amd/stoneyridge/acpi/pcie.asl><br>+<br>+ /* Describe the processor tree (\_PR) */<br>+ #include <soc/amd/stoneyridge/acpi/cpu.asl><br>+<br>+ /* Contains the supported sleep states for this chipset */<br>+ #include <soc/amd/stoneyridge/acpi/sleepstates.asl><br>+<br>+ /* Contains the Sleep methods (WAK, PTS, GTS, etc.) */<br>+ #include "acpi/sleep.asl"<br>+<br>+ /* System Bus */<br>+ Scope(\_SB) { /* Start \_SB scope */<br>+ /* global utility methods expected within the \_SB scope */<br>+ #include <arch/x86/acpi/globutil.asl><br>+<br>+ /* Describe IRQ Routing mapping for this platform (within the \_SB scope) */<br>+ #include "acpi/routing.asl"<br>+<br>+ Device(PWRB) {<br>+ Name(_HID, EISAID("PNP0C0C"))<br>+ Name(_UID, 0xAA)<br>+ Name(_PRW, Package () {3, 0x04})<br>+ Name(_STA, 0x0B)<br>+ }<br>+<br>+ Device(PCI0) {<br>+ /* Describe the AMD Northbridge */<br>+ #include <soc/amd/stoneyridge/acpi/northbridge.asl><br>+<br>+ /* Describe the AMD Fusion Controller Hub Southbridge */<br>+ #include <soc/amd/stoneyridge/acpi/fch.asl><br>+ }<br>+<br>+ /* Describe PCI INT[A-H] for the Southbridge */<br>+ #include <soc/amd/stoneyridge/acpi/pci_int.asl><br>+<br>+ /* Describe the devices in the Southbridge */<br>+ #include "acpi/carrizo_fch.asl"<br>+<br>+ } /* End \_SB scope */<br>+<br>+ /* Describe SMBUS for the Southbridge */<br>+ #include <soc/amd/stoneyridge/acpi/smbus.asl><br>+<br>+ /* Define the General Purpose Events for the platform */<br>+ #include "acpi/gpe.asl"<br>+}<br>+/* End of ASL file */<br>diff --git a/src/mainboard/amd/jadeite/early_mainboard.c b/src/mainboard/amd/jadeite/early_mainboard.c<br>new file mode 100644<br>index 0000000..cfc924d<br>--- /dev/null<br>+++ b/src/mainboard/amd/jadeite/early_mainboard.c<br>@@ -0,0 +1,29 @@<br>+/*<br>+ * This file is part of the coreboot project.<br>+ *<br>+ * Copyright (C) 2015-2016 Advanced Micro Devices, Inc.<br>+ *<br>+ * This program is free software; you can redistribute it and/or modify<br>+ * it under the terms of the GNU General Public License as published by<br>+ * the Free Software Foundation; version 2 of the License.<br>+ *<br>+ * This program is distributed in the hope that it will be useful,<br>+ * but WITHOUT ANY WARRANTY; without even the implied warranty of<br>+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the<br>+ * GNU General Public License for more details.<br>+ */<br>+<br>+#include <bootblock_common.h><br>+#include <superio/smsc/sio1036/sio1036.h><br>+<br>+#define SERIAL_DEV PNP_DEV(0x4e, SIO1036_SP1)<br>+<br>+void bootblock_mainboard_early_init(void)<br>+{<br>+ device_t dev = PCI_DEV(0, 0x14, 3);<br>+ u8 byte = pci_read_config8(dev, 0x48);<br>+ byte |= 3;<br>+ pci_write_config8(dev, 0x48, byte);<br>+<br>+ sio1036_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE);<br>+}<br>diff --git a/src/mainboard/amd/jadeite/fchec.c b/src/mainboard/amd/jadeite/fchec.c<br>new file mode 100644<br>index 0000000..532db79<br>--- /dev/null<br>+++ b/src/mainboard/amd/jadeite/fchec.c<br>@@ -0,0 +1,63 @@<br>+/*<br>+ * This file is part of the coreboot project.<br>+ *<br>+ * Copyright (C) 2015 Advanced Micro Devices, Inc.<br>+ *<br>+ * This program is free software; you can redistribute it and/or modify<br>+ * it under the terms of the GNU General Public License as published by<br>+ * the Free Software Foundation; version 2 of the License.<br>+ *<br>+ * This program is distributed in the hope that it will be useful,<br>+ * but WITHOUT ANY WARRANTY; without even the implied warranty of<br>+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the<br>+ * GNU General Public License for more details.<br>+ */<br>+<br>+#include "fchec.h"<br>+<br>+void agesawrapper_fchecfancontrolservice()<br>+{<br>+ FCH_DATA_BLOCK LateParams;<br>+<br>+ /* Thermal Zone Parameter */<br>+ LateParams.Imc.EcStruct.MsgFun81Zone0MsgReg0 = 0x00;<br>+ LateParams.Imc.EcStruct.MsgFun81Zone0MsgReg1 = 0x00; /* Zone */<br>+ LateParams.Imc.EcStruct.MsgFun81Zone0MsgReg2 = 0x3d;<br>+ LateParams.Imc.EcStruct.MsgFun81Zone0MsgReg3 = 0xc6;<br>+ LateParams.Imc.EcStruct.MsgFun81Zone0MsgReg4 = 0x00;<br>+ LateParams.Imc.EcStruct.MsgFun81Zone0MsgReg5 = 0x04;<br>+ LateParams.Imc.EcStruct.MsgFun81Zone0MsgReg6 = 0x98; /* SMBUS Address for SMBUS based temperature sensor such as SB-TSI and ADM1032 */<br>+ LateParams.Imc.EcStruct.MsgFun81Zone0MsgReg7 = 0x01;<br>+ LateParams.Imc.EcStruct.MsgFun81Zone0MsgReg8 = 0x01; /* PWM steping rate in unit of PWM level percentage */<br>+ LateParams.Imc.EcStruct.MsgFun81Zone0MsgReg9 = 0x00;<br>+<br>+ /* IMC Fan Policy temperature thresholds */<br>+ LateParams.Imc.EcStruct.MsgFun83Zone0MsgReg0 = 0x00;<br>+ LateParams.Imc.EcStruct.MsgFun83Zone0MsgReg1 = 0x00; /* Zone */<br>+ LateParams.Imc.EcStruct.MsgFun83Zone0MsgReg2 = 0x3c; /*AC0 threshold in Celsius */<br>+ LateParams.Imc.EcStruct.MsgFun83Zone0MsgReg3 = 0x28; /*AC1 threshold in Celsius */<br>+ LateParams.Imc.EcStruct.MsgFun83Zone0MsgReg4 = 0xff; /*AC2 threshold in Celsius */<br>+ LateParams.Imc.EcStruct.MsgFun83Zone0MsgReg5 = 0xff; /*AC3 threshold in Celsius, 0xFF is not define */<br>+ LateParams.Imc.EcStruct.MsgFun83Zone0MsgReg6 = 0xff; /*AC4 threshold in Celsius, 0xFF is not define */<br>+ LateParams.Imc.EcStruct.MsgFun83Zone0MsgReg7 = 0xff; /*AC5 threshold in Celsius, 0xFF is not define */<br>+ LateParams.Imc.EcStruct.MsgFun83Zone0MsgReg8 = 0xff; /*AC6 threshold in Celsius, 0xFF is not define */<br>+ LateParams.Imc.EcStruct.MsgFun83Zone0MsgReg9 = 0xff; /*AC7 lowest threshold in Celsius, 0xFF is not define */<br>+ LateParams.Imc.EcStruct.MsgFun83Zone0MsgRegA = 0x4b; /*critical threshold* in Celsius, 0xFF is not define */<br>+ LateParams.Imc.EcStruct.MsgFun83Zone0MsgRegB = 0x00;<br>+<br>+ /* IMC Fan Policy PWM Settings */<br>+ LateParams.Imc.EcStruct.MsgFun85Zone0MsgReg0 = 0x00;<br>+ LateParams.Imc.EcStruct.MsgFun85Zone0MsgReg1 = 0x00; /* Zone */<br>+ LateParams.Imc.EcStruct.MsgFun85Zone0MsgReg2 = 0x50; /* AL0 percentage */<br>+ LateParams.Imc.EcStruct.MsgFun85Zone0MsgReg3 = 0x32; /* AL1 percentage */<br>+ LateParams.Imc.EcStruct.MsgFun85Zone0MsgReg4 = 0xff; /* AL2 percentage */<br>+ LateParams.Imc.EcStruct.MsgFun85Zone0MsgReg5 = 0xff; /* AL3 percentage */<br>+ LateParams.Imc.EcStruct.MsgFun85Zone0MsgReg6 = 0xff; /* AL4 percentage */<br>+ LateParams.Imc.EcStruct.MsgFun85Zone0MsgReg7 = 0xff; /* AL5 percentage */<br>+ LateParams.Imc.EcStruct.MsgFun85Zone0MsgReg8 = 0xff; /* AL6 percentage */<br>+ LateParams.Imc.EcStruct.MsgFun85Zone0MsgReg9 = 0xff; /* AL7 percentage */<br>+<br>+ LateParams.Imc.EcStruct.IMCFUNSupportBitMap = 0x111;<br>+<br>+ FchECfancontrolservice(&LateParams);<br>+}<br>diff --git a/src/mainboard/amd/jadeite/fchec.h b/src/mainboard/amd/jadeite/fchec.h<br>new file mode 100644<br>index 0000000..9fb41b3<br>--- /dev/null<br>+++ b/src/mainboard/amd/jadeite/fchec.h<br>@@ -0,0 +1,27 @@<br>+/*<br>+ * This file is part of the coreboot project.<br>+ *<br>+ * Copyright (C) 2012 Advanced Micro Devices, Inc.<br>+ *<br>+ * This program is free software; you can redistribute it and/or modify<br>+ * it under the terms of the GNU General Public License as published by<br>+ * the Free Software Foundation; version 2 of the License.<br>+ *<br>+ * This program is distributed in the hope that it will be useful,<br>+ * but WITHOUT ANY WARRANTY; without even the implied warranty of<br>+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the<br>+ * GNU General Public License for more details.<br>+ */<br>+<br>+#ifndef AMD_GARDENIA_FCHEC<br>+#define AMD_GARDENIA_FCHEC<br>+<br>+#include <soc/imc.h><br>+#include "Porting.h"<br>+#include "AGESA.h"<br>+#include "FchCommonCfg.h"<br>+<br>+extern VOID FchECfancontrolservice (IN VOID *FchDataPtr);<br>+void agesawrapper_fchecfancontrolservice(void);<br>+<br>+#endif<br>diff --git a/src/mainboard/amd/jadeite/irq_tables.c b/src/mainboard/amd/jadeite/irq_tables.c<br>new file mode 100644<br>index 0000000..dd24f73<br>--- /dev/null<br>+++ b/src/mainboard/amd/jadeite/irq_tables.c<br>@@ -0,0 +1,102 @@<br>+/*<br>+ * This file is part of the coreboot project.<br>+ *<br>+ * Copyright (C) 2015 Advanced Micro Devices, Inc.<br>+ *<br>+ * This program is free software; you can redistribute it and/or modify<br>+ * it under the terms of the GNU General Public License as published by<br>+ * the Free Software Foundation; version 2 of the License.<br>+ *<br>+ * This program is distributed in the hope that it will be useful,<br>+ * but WITHOUT ANY WARRANTY; without even the implied warranty of<br>+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the<br>+ * GNU General Public License for more details.<br>+ */<br>+<br>+#include <console/console.h><br>+#include <device/pci.h><br>+#include <string.h><br>+#include <stdint.h><br>+#include <arch/pirq_routing.h><br>+#include <cpu/amd/amdfam16.h><br>+<br>+static void write_pirq_info(struct irq_info *pirq_info, u8 bus, u8 devfn,<br>+ u8 link0, u16 bitmap0, u8 link1, u16 bitmap1,<br>+ u8 link2, u16 bitmap2, u8 link3, u16 bitmap3,<br>+ u8 slot, u8 rfu)<br>+{<br>+ pirq_info->bus = bus;<br>+ pirq_info->devfn = devfn;<br>+ pirq_info->irq[0].link = link0;<br>+ pirq_info->irq[0].bitmap = bitmap0;<br>+ pirq_info->irq[1].link = link1;<br>+ pirq_info->irq[1].bitmap = bitmap1;<br>+ pirq_info->irq[2].link = link2;<br>+ pirq_info->irq[2].bitmap = bitmap2;<br>+ pirq_info->irq[3].link = link3;<br>+ pirq_info->irq[3].bitmap = bitmap3;<br>+ pirq_info->slot = slot;<br>+ pirq_info->rfu = rfu;<br>+}<br>+<br>+unsigned long write_pirq_routing_table(unsigned long addr)<br>+{<br>+ struct irq_routing_table *pirq;<br>+ struct irq_info *pirq_info;<br>+ u32 slot_num;<br>+ u8 *v;<br>+<br>+ u8 sum = 0;<br>+ int i;<br>+<br>+ /* Align the table to be 16 byte aligned. */<br>+ addr += 15;<br>+ addr &= ~15;<br>+<br>+ /* This table must be between 0xf0000 & 0x100000 */<br>+ printk(BIOS_INFO, "Writing IRQ routing tables to 0x%lx...", addr);<br>+<br>+ pirq = (void *)(addr);<br>+ v = (u8 *) (addr);<br>+<br>+ pirq->signature = PIRQ_SIGNATURE;<br>+ pirq->version = PIRQ_VERSION;<br>+<br>+ pirq->rtr_bus = 0;<br>+ pirq->rtr_devfn = PCI_DEVFN(0x14, 4);<br>+<br>+ pirq->exclusive_irqs = 0;<br>+<br>+ pirq->rtr_vendor = 0x1002;<br>+ pirq->rtr_device = 0x4384;<br>+<br>+ pirq->miniport_data = 0;<br>+<br>+ memset(pirq->rfu, 0, sizeof(pirq->rfu));<br>+<br>+ pirq_info = (void *)(&pirq->checksum + 1);<br>+ slot_num = 0;<br>+<br>+ /* pci bridge */<br>+ write_pirq_info(pirq_info, 0, PCI_DEVFN(0x14, 4),<br>+ 0x1, 0xdef8, 0x2, 0xdef8, 0x3, 0xdef8, 0x4, 0xdef8, 0,<br>+ 0);<br>+ pirq_info++;<br>+<br>+ slot_num++;<br>+<br>+ pirq->size = 32 + 16 * slot_num;<br>+<br>+ for (i = 0; i < pirq->size; i++)<br>+ sum += v[i];<br>+<br>+ sum = pirq->checksum - sum;<br>+<br>+ if (sum != pirq->checksum) {<br>+ pirq->checksum = sum;<br>+ }<br>+<br>+ printk(BIOS_INFO, "write_pirq_routing_table done.\n");<br>+<br>+ return (unsigned long)pirq_info;<br>+}<br>diff --git a/src/mainboard/amd/jadeite/mainboard.c b/src/mainboard/amd/jadeite/mainboard.c<br>new file mode 100644<br>index 0000000..9470296<br>--- /dev/null<br>+++ b/src/mainboard/amd/jadeite/mainboard.c<br>@@ -0,0 +1,93 @@<br>+/*<br>+ * This file is part of the coreboot project.<br>+ *<br>+ * Copyright (C) 2015 Advanced Micro Devices, Inc.<br>+ *<br>+ * This program is free software; you can redistribute it and/or modify<br>+ * it under the terms of the GNU General Public License as published by<br>+ * the Free Software Foundation; version 2 of the License.<br>+ *<br>+ * This program is distributed in the hope that it will be useful,<br>+ * but WITHOUT ANY WARRANTY; without even the implied warranty of<br>+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the<br>+ * GNU General Public License for more details.<br>+ */<br>+<br>+#include <console/console.h><br>+#include <device/device.h><br>+#include <arch/acpi.h><br>+#include <agesawrapper.h><br>+#include <amd_pci_util.h><br>+<br>+/***********************************************************<br>+ * These arrays set up the FCH PCI_INTR registers 0xC00/0xC01.<br>+ * This table is responsible for physically routing the PIC and<br>+ * IOAPIC IRQs to the different PCI devices on the system. It<br>+ * is read and written via registers 0xC00/0xC01 as an<br>+ * Index/Data pair. These values are chipset and mainboard<br>+ * dependent and should be updated accordingly.<br>+ *<br>+ * These values are used by the PCI configuration space,<br>+ * MP Tables. TODO: Make ACPI use these values too.<br>+ */<br>+const u8 mainboard_picr_data[] = {<br>+ [0x00] = 0x03,0x04,0x05,0x07,0x0B,0x0A,0x1F,0x1F,<br>+ [0x08] = 0xFA,0xF1,0x00,0x00,0x1F,0x1F,0x1F,0x1F,<br>+ [0x10] = 0x1F,0x1F,0x1F,0x03,0x1F,0x1F,0x1F,0x1F,<br>+ [0x18] = 0x1F,0x00,0x00,0x00,0x00,0x00,0x00,0x00,<br>+ [0x20] = 0x1F,0x1F,0x1F,0x1F,0x1F,0x1F,0x00,0x00,<br>+ [0x28] = 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,<br>+ [0x30] = 0x05,0x04,0x05,0x04,0x04,0x05,0x04,0x05,<br>+ [0x38] = 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,<br>+ [0x40] = 0x04,0x1F,0x00,0x00,0x00,0x00,0x00,0x00,<br>+ [0x48] = 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,<br>+ [0x50] = 0x03,0x04,0x05,0x07,0x1F,0x1F,0x1F,0x1F,<br>+ [0x58] = 0x1F,0x1F,0x1F,0x1F,0x1F,0x1F,0x1F,0x1F,<br>+ [0x60] = 0x1F,0x1F,0x07,0x1F,0x1F,0x1F,0x1F,0x1F,<br>+ [0x68] = 0x1F,0x1F,0x1F,0x1F,0x1F,0x1F,0x1F,0x1F,<br>+ [0x70] = 0x03,0x0F,0x06,0x0E,0x0A,0x0B,0x1F,0x1F,<br>+ [0x78] = 0x1F,0x1F,0x1F,0x1F,0x1F,0x1F,0x1F,0x1F,<br>+};<br>+<br>+const u8 mainboard_intr_data[] = {<br>+ [0x00] = 0x10,0x11,0x12,0x13,0x14,0x15,0x16,0x17,<br>+ [0x08] = 0x00,0x00,0x00,0x00,0x1F,0x1F,0x1F,0x1F,<br>+ [0x10] = 0x09,0x1F,0x1F,0x10,0x1F,0x1F,0x1F,0x10,<br>+ [0x18] = 0x1F,0x1F,0x1F,0x00,0x00,0x00,0x00,0x00,<br>+ [0x20] = 0x1F,0x1F,0x1F,0x1F,0x1F,0x1F,0x00,0x00,<br>+ [0x28] = 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,<br>+ [0x30] = 0x12,0x11,0x12,0x11,0x12,0x11,0x12,0x00,<br>+ [0x38] = 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,<br>+ [0x40] = 0x11,0x13,0x00,0x00,0x00,0x00,0x00,0x00,<br>+ [0x48] = 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,<br>+ [0x50] = 0x1F,0x1F,0x1F,0x1F,0x00,0x00,0x00,0x00,<br>+ [0x58] = 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,<br>+ [0x60] = 0x1F,0x1F,0x07,0x00,0x00,0x00,0x00,0x00,<br>+ [0x68] = 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,<br>+ [0x70] = 0x03,0x0F,0x06,0x0E,0x0A,0x0B,0x1F,0x1F,<br>+ [0x78] = 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,<br>+};<br>+<br>+/* PIRQ Setup */<br>+static void pirq_setup(void)<br>+{<br>+ intr_data_ptr = mainboard_intr_data;<br>+ picr_data_ptr = mainboard_picr_data;<br>+}<br>+<br>+<br>+<br>+/*************************************************<br>+ * enable the dedicated function in gardenia board.<br>+ *************************************************/<br>+static void gardenia_enable(device_t dev)<br>+{<br>+ printk(BIOS_INFO, "Mainboard " CONFIG_MAINBOARD_PART_NUMBER " Enable.\n");<br>+<br>+ /* Initialize the PIRQ data structures for consumption */<br>+ pirq_setup();<br>+}<br>+<br>+struct chip_operations mainboard_ops = {<br>+ .enable_dev = gardenia_enable,<br>+};<br>diff --git a/src/mainboard/amd/jadeite/mptable.c b/src/mainboard/amd/jadeite/mptable.c<br>new file mode 100644<br>index 0000000..0d9064f<br>--- /dev/null<br>+++ b/src/mainboard/amd/jadeite/mptable.c<br>@@ -0,0 +1,163 @@<br>+/*<br>+ * This file is part of the coreboot project.<br>+ *<br>+ * Copyright (C) 2015 Advanced Micro Devices, Inc.<br>+ *<br>+ * This program is free software; you can redistribute it and/or modify<br>+ * it under the terms of the GNU General Public License as published by<br>+ * the Free Software Foundation; version 2 of the License.<br>+ *<br>+ * This program is distributed in the hope that it will be useful,<br>+ * but WITHOUT ANY WARRANTY; without even the implied warranty of<br>+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the<br>+ * GNU General Public License for more details.<br>+ */<br>+<br>+#include <console/console.h><br>+#include <arch/smp/mpspec.h><br>+#include <device/pci.h><br>+#include <arch/io.h><br>+#include <arch/ioapic.h><br>+#include <string.h><br>+#include <stdint.h><br>+#include <cpu/amd/amdfam15.h><br>+#include <arch/cpu.h><br>+#include <cpu/x86/lapic.h><br>+#include <soc/hudson.h><br>+#include <amd_pci_util.h><br>+<br>+static void smp_add_mpc_entry(struct mp_config_table *mc, unsigned length)<br>+{<br>+ mc->mpc_length += length;<br>+ mc->mpc_entry_count++;<br>+}<br>+<br>+static void my_smp_write_bus(struct mp_config_table *mc,<br>+ unsigned char id, const char *bustype)<br>+{<br>+ struct mpc_config_bus *mpc;<br>+ mpc = smp_next_mpc_entry(mc);<br>+ memset(mpc, '\0', sizeof(*mpc));<br>+ mpc->mpc_type = MP_BUS;<br>+ mpc->mpc_busid = id;<br>+ memcpy(mpc->mpc_bustype, bustype, sizeof(mpc->mpc_bustype));<br>+ smp_add_mpc_entry(mc, sizeof(*mpc));<br>+}<br>+<br>+static void *smp_write_config_table(void *v)<br>+{<br>+ struct mp_config_table *mc;<br>+ int bus_isa;<br>+<br>+ /*<br>+ * By the time this function gets called, the IOAPIC registers<br>+ * have been written so they can be read to get the correct<br>+ * APIC ID and Version<br>+ */<br>+ u8 ioapic_id = (io_apic_read(VIO_APIC_VADDR, 0x00) >> 24);<br>+ u8 ioapic_ver = (io_apic_read(VIO_APIC_VADDR, 0x01) & 0xFF);<br>+<br>+ mc = (void *)(((char *)v) + SMP_FLOATING_TABLE_LEN);<br>+<br>+ mptable_init(mc, LOCAL_APIC_ADDR);<br>+ memcpy(mc->mpc_oem, "AMD ", 8);<br>+<br>+ smp_write_processors(mc);<br>+<br>+ //mptable_write_buses(mc, NULL, &bus_isa);<br>+ my_smp_write_bus(mc, 0, "PCI ");<br>+ my_smp_write_bus(mc, 1, "PCI ");<br>+ bus_isa = 0x02;<br>+ my_smp_write_bus(mc, bus_isa, "ISA ");<br>+<br>+ /* I/O APICs: APIC ID Version State Address */<br>+ smp_write_ioapic(mc, ioapic_id, ioapic_ver, VIO_APIC_VADDR);<br>+<br>+ smp_write_ioapic(mc, ioapic_id+1, 0x21, (void *)0xFEC20000);<br>+<br>+ /* I/O Ints: Type Polarity Trigger Bus ID IRQ APIC ID PIN# */<br>+#define IO_LOCAL_INT(type, intr, apicid, pin) \<br>+ smp_write_lintsrc(mc, (type), MP_IRQ_TRIGGER_EDGE | MP_IRQ_POLARITY_HIGH, bus_isa, (intr), (apicid), (pin));<br>+ mptable_add_isa_interrupts(mc, bus_isa, ioapic_id, 0);<br>+<br>+ /* PCI interrupts are level triggered, and are<br>+ * associated with a specific bus/device/function tuple.<br>+ */<br>+#define PCI_INT(bus, dev, int_sign, pin) \<br>+ smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, (bus), (((dev)<<2)|(int_sign)), ioapic_id, (pin))<br>+<br>+ /* Internal VGA */<br>+ PCI_INT(0x0, 0x01, 0x0, intr_data_ptr[0x02]);<br>+ PCI_INT(0x0, 0x01, 0x1, intr_data_ptr[0x03]);<br>+<br>+ /* SMBUS */<br>+ PCI_INT(0x0, 0x14, 0x0, 0x10);<br>+<br>+ /* HD Audio */<br>+ PCI_INT(0x0, 0x14, 0x0, intr_data_ptr[0x13]);<br>+<br>+ /* USB */<br>+ PCI_INT(0x0, 0x12, 0x0, intr_data_ptr[0x30]);<br>+ PCI_INT(0x0, 0x12, 0x1, intr_data_ptr[0x31]);<br>+ PCI_INT(0x0, 0x13, 0x0, intr_data_ptr[0x32]);<br>+ PCI_INT(0x0, 0x13, 0x1, intr_data_ptr[0x33]);<br>+ PCI_INT(0x0, 0x16, 0x0, intr_data_ptr[0x34]);<br>+ PCI_INT(0x0, 0x16, 0x1, intr_data_ptr[0x35]);<br>+ PCI_INT(0x0, 0x14, 0x2, intr_data_ptr[0x36]);<br>+<br>+ /* sata */<br>+ PCI_INT(0x0, 0x11, 0x0, intr_data_ptr[0x40]);<br>+ PCI_INT(0x0, 0x11, 0x0, intr_data_ptr[0x41]);<br>+<br>+ /* on board NIC & Slot PCIE. */<br>+<br>+ /* PCI slots */<br>+ device_t dev = dev_find_slot(0, PCI_DEVFN(0x14, 4));<br>+ if (dev && dev->enabled) {<br>+ u8 bus_pci = dev->link_list->secondary;<br>+ /* PCI_SLOT 0. */<br>+ PCI_INT(bus_pci, 0x5, 0x0, 0x14);<br>+ PCI_INT(bus_pci, 0x5, 0x1, 0x15);<br>+ PCI_INT(bus_pci, 0x5, 0x2, 0x16);<br>+ PCI_INT(bus_pci, 0x5, 0x3, 0x17);<br>+<br>+ /* PCI_SLOT 1. */<br>+ PCI_INT(bus_pci, 0x6, 0x0, 0x15);<br>+ PCI_INT(bus_pci, 0x6, 0x1, 0x16);<br>+ PCI_INT(bus_pci, 0x6, 0x2, 0x17);<br>+ PCI_INT(bus_pci, 0x6, 0x3, 0x14);<br>+<br>+ /* PCI_SLOT 2. */<br>+ PCI_INT(bus_pci, 0x7, 0x0, 0x16);<br>+ PCI_INT(bus_pci, 0x7, 0x1, 0x17);<br>+ PCI_INT(bus_pci, 0x7, 0x2, 0x14);<br>+ PCI_INT(bus_pci, 0x7, 0x3, 0x15);<br>+ }<br>+<br>+ /* PCIe Lan*/<br>+ PCI_INT(0x0, 0x06, 0x0, 0x13);<br>+<br>+ /* FCH PCIe PortA */<br>+ PCI_INT(0x0, 0x15, 0x0, 0x10);<br>+ /* FCH PCIe PortB */<br>+ PCI_INT(0x0, 0x15, 0x1, 0x11);<br>+ /* FCH PCIe PortC */<br>+ PCI_INT(0x0, 0x15, 0x2, 0x12);<br>+ /* FCH PCIe PortD */<br>+ PCI_INT(0x0, 0x15, 0x3, 0x13);<br>+<br>+ /*Local Ints: Type Polarity Trigger Bus ID IRQ APIC ID PIN# */<br>+ IO_LOCAL_INT(mp_ExtINT, 0, MP_APIC_ALL, 0x0);<br>+ IO_LOCAL_INT(mp_NMI, 0, MP_APIC_ALL, 0x1);<br>+ /* There is no extension information... */<br>+<br>+ /* Compute the checksums */<br>+ return mptable_finalize(mc);<br>+}<br>+<br>+unsigned long write_smp_table(unsigned long addr)<br>+{<br>+ void *v;<br>+ v = smp_write_floating_table(addr, 0);<br>+ return (unsigned long)smp_write_config_table(v);<br>+}<br>diff --git a/src/mainboard/amd/jadeite/romstage.c b/src/mainboard/amd/jadeite/romstage.c<br>new file mode 100644<br>index 0000000..e25adbd<br>--- /dev/null<br>+++ b/src/mainboard/amd/jadeite/romstage.c<br>@@ -0,0 +1,15 @@<br>+/*<br>+ * This file is part of the coreboot project.<br>+ *<br>+ * Copyright (C) 2015-2016 Advanced Micro Devices, Inc.<br>+ *<br>+ * This program is free software; you can redistribute it and/or modify<br>+ * it under the terms of the GNU General Public License as published by<br>+ * the Free Software Foundation; version 2 of the License.<br>+ *<br>+ * This program is distributed in the hope that it will be useful,<br>+ * but WITHOUT ANY WARRANTY; without even the implied warranty of<br>+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the<br>+ * GNU General Public License for more details.<br>+ */<br>+<br></pre><p>To view, visit <a href="https://review.coreboot.org/20529">change 20529</a>. To unsubscribe, visit <a href="https://review.coreboot.org/settings">settings</a>.</p><div itemscope itemtype="http://schema.org/EmailMessage"><div itemscope itemprop="action" itemtype="http://schema.org/ViewAction"><link itemprop="url" href="https://review.coreboot.org/20529"/><meta itemprop="name" content="View Change"/></div></div>
<div style="display:none"> Gerrit-Project: coreboot </div>
<div style="display:none"> Gerrit-Branch: master </div>
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<div style="display:none"> Gerrit-Change-Id: Ic28b8f584e6b78435a5203192480d1288a337a88 </div>
<div style="display:none"> Gerrit-Change-Number: 20529 </div>
<div style="display:none"> Gerrit-PatchSet: 1 </div>
<div style="display:none"> Gerrit-Owner: Marshall Dawson <marshalldawson3rd@gmail.com> </div>