<p>Naresh Solanki has uploaded this change for <strong>review</strong>.</p><p><a href="https://review.coreboot.org/20532">View Change</a></p><pre style="font-family: monospace,monospace; white-space: pre-wrap;">soc/intel/skylake: Log wakes due to PCIE root port<br><br>When wake happens due to PME on PCIE root port, then update the same in elog.<br><br>BUG=b:36992859<br>TEST=Build for Soraka, Verify resume due to PME on root port is updated<br>in elog.<br><br>Change-Id: I879a7c332e62ab598942b29d31bad84619b35ea7<br>Signed-off-by: Naresh G Solanki <naresh.solanki@intel.com><br>---<br>M src/soc/intel/skylake/elog.c<br>1 file changed, 41 insertions(+), 15 deletions(-)<br><br></pre><pre style="font-family: monospace,monospace; white-space: pre-wrap;">git pull ssh://review.coreboot.org:29418/coreboot refs/changes/32/20532/1</pre><pre style="font-family: monospace,monospace; white-space: pre-wrap;">diff --git a/src/soc/intel/skylake/elog.c b/src/soc/intel/skylake/elog.c<br>index fde8be2..69bc25e 100644<br>--- a/src/soc/intel/skylake/elog.c<br>+++ b/src/soc/intel/skylake/elog.c<br>@@ -200,20 +200,6 @@<br> static const struct pme_status_info pme_status_info[] = {<br> { PCH_DEVFN_HDA, 0x54, ELOG_WAKE_SOURCE_PME_HDA },<br> { PCH_DEVFN_GBE, 0xcc, ELOG_WAKE_SOURCE_PME_GBE },<br>- { PCH_DEVFN_EMMC, 0x84, ELOG_WAKE_SOURCE_PME_EMMC },<br>- { PCH_DEVFN_SDCARD, 0x84, ELOG_WAKE_SOURCE_PME_SDCARD },<br>- { PCH_DEVFN_PCIE1, 0xa4, ELOG_WAKE_SOURCE_PME_PCIE1 },<br>- { PCH_DEVFN_PCIE2, 0xa4, ELOG_WAKE_SOURCE_PME_PCIE2 },<br>- { PCH_DEVFN_PCIE3, 0xa4, ELOG_WAKE_SOURCE_PME_PCIE3 },<br>- { PCH_DEVFN_PCIE4, 0xa4, ELOG_WAKE_SOURCE_PME_PCIE4 },<br>- { PCH_DEVFN_PCIE5, 0xa4, ELOG_WAKE_SOURCE_PME_PCIE5 },<br>- { PCH_DEVFN_PCIE6, 0xa4, ELOG_WAKE_SOURCE_PME_PCIE6 },<br>- { PCH_DEVFN_PCIE7, 0xa4, ELOG_WAKE_SOURCE_PME_PCIE7 },<br>- { PCH_DEVFN_PCIE8, 0xa4, ELOG_WAKE_SOURCE_PME_PCIE8 },<br>- { PCH_DEVFN_PCIE9, 0xa4, ELOG_WAKE_SOURCE_PME_PCIE9 },<br>- { PCH_DEVFN_PCIE10, 0xa4, ELOG_WAKE_SOURCE_PME_PCIE10 },<br>- { PCH_DEVFN_PCIE11, 0xa4, ELOG_WAKE_SOURCE_PME_PCIE11 },<br>- { PCH_DEVFN_PCIE12, 0xa4, ELOG_WAKE_SOURCE_PME_PCIE12 },<br> { PCH_DEVFN_SATA, 0x74, ELOG_WAKE_SOURCE_PME_SATA },<br> { PCH_DEVFN_CSE, 0x54, ELOG_WAKE_SOURCE_PME_CSE },<br> { PCH_DEVFN_CSE_2, 0x54, ELOG_WAKE_SOURCE_PME_CSE2 },<br>@@ -228,7 +214,7 @@<br> if (!dev)<br> continue;<br> <br>- val = pci_read_config16(dev, pme_status_info[i].reg_offset);<br>+ val = pci_read_config32(dev, pme_status_info[i].reg_offset);<br> <br> if ((val == 0xFFFF) || !(val & PME_STS_BIT))<br> continue;<br>@@ -239,6 +225,43 @@<br> <br> if (!dev_found)<br> elog_add_event_wake(ELOG_WAKE_SOURCE_PME_INTERNAL, 0);<br>+}<br>+<br>+#define RP_PME_STS_BIT (1 << 16)<br>+static void pch_log_rp_wake_source(void)<br>+{<br>+ size_t i;<br>+ device_t dev;<br>+ uint32_t val;<br>+<br>+ static const struct pme_status_info pme_status_info[] = {<br>+ { PCH_DEVFN_PCIE1, 0x60, ELOG_WAKE_SOURCE_PME_PCIE1 },<br>+ { PCH_DEVFN_PCIE2, 0x60, ELOG_WAKE_SOURCE_PME_PCIE2 },<br>+ { PCH_DEVFN_PCIE3, 0x60, ELOG_WAKE_SOURCE_PME_PCIE3 },<br>+ { PCH_DEVFN_PCIE4, 0x60, ELOG_WAKE_SOURCE_PME_PCIE4 },<br>+ { PCH_DEVFN_PCIE5, 0x60, ELOG_WAKE_SOURCE_PME_PCIE5 },<br>+ { PCH_DEVFN_PCIE6, 0x60, ELOG_WAKE_SOURCE_PME_PCIE6 },<br>+ { PCH_DEVFN_PCIE7, 0x60, ELOG_WAKE_SOURCE_PME_PCIE7 },<br>+ { PCH_DEVFN_PCIE8, 0x60, ELOG_WAKE_SOURCE_PME_PCIE8 },<br>+ { PCH_DEVFN_PCIE9, 0x60, ELOG_WAKE_SOURCE_PME_PCIE9 },<br>+ { PCH_DEVFN_PCIE10, 0x60, ELOG_WAKE_SOURCE_PME_PCIE10 },<br>+ { PCH_DEVFN_PCIE11, 0x60, ELOG_WAKE_SOURCE_PME_PCIE11 },<br>+ { PCH_DEVFN_PCIE12, 0x60, ELOG_WAKE_SOURCE_PME_PCIE12 },<br>+ };<br>+<br>+ for (i = 0; i < ARRAY_SIZE(pme_status_info); i++) {<br>+ dev = dev_find_slot(0, pme_status_info[i].devfn);<br>+<br>+ if (!dev)<br>+ continue;<br>+<br>+ val = pci_read_config32(dev, pme_status_info[i].reg_offset);<br>+<br>+ if ((val == 0xFFFFFFFF) || !(val & RP_PME_STS_BIT))<br>+ continue;<br>+<br>+ pch_log_add_elog_event(&pme_status_info[i], dev);<br>+ }<br> }<br> <br> static void pch_log_wake_source(struct chipset_power_state *ps)<br>@@ -263,6 +286,9 @@<br> if (ps->gpe0_sts[GPE_STD] & PME_B0_STS)<br> pch_log_pme_internal_wake_source();<br> <br>+ /* PCIE Root Port */<br>+ pch_log_rp_wake_source();<br>+<br> /* SMBUS Wake */<br> if (ps->gpe0_sts[GPE_STD] & SMB_WAK_STS)<br> elog_add_event_wake(ELOG_WAKE_SOURCE_SMBUS, 0);<br></pre><p>To view, visit <a href="https://review.coreboot.org/20532">change 20532</a>. To unsubscribe, visit <a href="https://review.coreboot.org/settings">settings</a>.</p><div itemscope itemtype="http://schema.org/EmailMessage"><div itemscope itemprop="action" itemtype="http://schema.org/ViewAction"><link itemprop="url" href="https://review.coreboot.org/20532"/><meta itemprop="name" content="View Change"/></div></div>
<div style="display:none"> Gerrit-Project: coreboot </div>
<div style="display:none"> Gerrit-Branch: master </div>
<div style="display:none"> Gerrit-MessageType: newchange </div>
<div style="display:none"> Gerrit-Change-Id: I879a7c332e62ab598942b29d31bad84619b35ea7 </div>
<div style="display:none"> Gerrit-Change-Number: 20532 </div>
<div style="display:none"> Gerrit-PatchSet: 1 </div>
<div style="display:none"> Gerrit-Owner: Naresh Solanki <naresh.solanki@intel.com> </div>