<p>Lijian Zhao has uploaded this change for <strong>review</strong>.</p><p><a href="https://review.coreboot.org/20497">View Change</a></p><pre style="font-family: monospace,monospace; white-space: pre-wrap;">soc/intel/cannonlake: Minimal changes to call FSPM<br><br>The following minimal changes will be needed to call into Fsp Memory Init<br>1.SA BARs need to be programmed.<br>2.Assume power state is S0.<br><br>Change-Id: Iab96b27d4220acf4089b901bca28018eaba940a1<br>Signed-off-by: Lijian Zhao <lijian.zhao@intel.com><br>---<br>M src/soc/intel/cannonlake/Makefile.inc<br>M src/soc/intel/cannonlake/include/soc/pm.h<br>A src/soc/intel/cannonlake/include/soc/romstage.h<br>A src/soc/intel/cannonlake/romstage/Makefile.inc<br>A src/soc/intel/cannonlake/romstage/power_state.c<br>A src/soc/intel/cannonlake/romstage/romstage.c<br>A src/soc/intel/cannonlake/romstage/systemagent.c<br>7 files changed, 191 insertions(+), 5 deletions(-)<br><br></pre><pre style="font-family: monospace,monospace; white-space: pre-wrap;">git pull ssh://review.coreboot.org:29418/coreboot refs/changes/97/20497/1</pre><pre style="font-family: monospace,monospace; white-space: pre-wrap;">diff --git a/src/soc/intel/cannonlake/Makefile.inc b/src/soc/intel/cannonlake/Makefile.inc<br>index 27c2e9b..480e047 100644<br>--- a/src/soc/intel/cannonlake/Makefile.inc<br>+++ b/src/soc/intel/cannonlake/Makefile.inc<br>@@ -1,5 +1,6 @@<br> ifeq ($(CONFIG_SOC_INTEL_CANNONLAKE),y)<br> <br>+subdirs-y += romstage<br> subdirs-y += ../../../cpu/intel/microcode<br> subdirs-y += ../../../cpu/x86/mtrr<br> subdirs-y += ../../../cpu/x86/tsc<br>diff --git a/src/soc/intel/cannonlake/include/soc/pm.h b/src/soc/intel/cannonlake/include/soc/pm.h<br>index 9c7c41a..d692507 100644<br>--- a/src/soc/intel/cannonlake/include/soc/pm.h<br>+++ b/src/soc/intel/cannonlake/include/soc/pm.h<br>@@ -1,7 +1,8 @@<br> /*<br> * This file is part of the coreboot project.<br> *<br>- * Copyright (C) 2017 Intel Corporation.<br>+ * Copyright (C) 2014 Google Inc.<br>+ * Copyright (C) 2015-2016 Intel Corporation.<br> *<br> * This program is free software; you can redistribute it and/or modify<br> * it under the terms of the GNU General Public License as published by<br>@@ -13,9 +14,26 @@<br> * GNU General Public License for more details.<br> */<br> <br>-#ifndef _SOC_CANNONLAKE_PM_H_<br>-#define _SOC_CANNONLAKE_PM_H_<br>+#ifndef _SOC_PM_H_<br>+#define _SOC_PM_H_<br> <br>-/* nothing here yet. Thanks for looking, though! */<br>+#include <arch/acpi.h><br>+#include <soc/pmc.h><br> <br>-#endif<br>\ No newline at end of file<br>+struct chipset_power_state {<br>+ uint16_t pm1_sts;<br>+ uint16_t pm1_en;<br>+ uint32_t pm1_cnt;<br>+ uint16_t tco1_sts;<br>+ uint16_t tco2_sts;<br>+ uint32_t gpe0_sts[4];<br>+ uint32_t gpe0_en[4];<br>+ uint32_t gen_pmcon_a;<br>+ uint32_t gen_pmcon_b;<br>+ uint32_t gblrst_cause[2];<br>+ uint32_t prev_sleep_state;<br>+} __attribute__ ((packed));<br>+<br>+struct chipset_power_state *fill_power_state(void);<br>+<br>+#endif<br>diff --git a/src/soc/intel/cannonlake/include/soc/romstage.h b/src/soc/intel/cannonlake/include/soc/romstage.h<br>new file mode 100644<br>index 0000000..2cdbaa5<br>--- /dev/null<br>+++ b/src/soc/intel/cannonlake/include/soc/romstage.h<br>@@ -0,0 +1,26 @@<br>+/*<br>+ * This file is part of the coreboot project.<br>+ *<br>+ * Copyright (C) 2014 Google Inc.<br>+ * Copyright (C) 2015-2017 Intel Corporation.<br>+ *<br>+ * This program is free software; you can redistribute it and/or modify<br>+ * it under the terms of the GNU General Public License as published by<br>+ * the Free Software Foundation; version 2 of the License.<br>+ *<br>+ * This program is distributed in the hope that it will be useful,<br>+ * but WITHOUT ANY WARRANTY; without even the implied warranty of<br>+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the<br>+ * GNU General Public License for more details.<br>+ */<br>+<br>+#ifndef _SOC_ROMSTAGE_H_<br>+#define _SOC_ROMSTAGE_H_<br>+<br>+#include <arch/cpu.h><br>+#include <fsp/api.h><br>+<br>+void mainboard_memory_init_params(FSPM_UPD *mupd);<br>+void systemagent_early_init(void);<br>+<br>+#endif /* _SOC_ROMSTAGE_H_ */<br>diff --git a/src/soc/intel/cannonlake/romstage/Makefile.inc b/src/soc/intel/cannonlake/romstage/Makefile.inc<br>new file mode 100644<br>index 0000000..99bc25f<br>--- /dev/null<br>+++ b/src/soc/intel/cannonlake/romstage/Makefile.inc<br>@@ -0,0 +1,18 @@<br>+#<br>+# This file is part of the coreboot project.<br>+#<br>+# Copyright (C) 2015-2017 Intel Corporation<br>+#<br>+# This program is free software; you can redistribute it and/or modify<br>+# it under the terms of the GNU General Public License as published by<br>+# the Free Software Foundation; version 2 of the License.<br>+#<br>+# This program is distributed in the hope that it will be useful,<br>+# but WITHOUT ANY WARRANTY; without even the implied warranty of<br>+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the<br>+# GNU General Public License for more details.<br>+#<br>+<br>+romstage-y += power_state.c<br>+romstage-y += romstage.c<br>+romstage-y += systemagent.c<br>diff --git a/src/soc/intel/cannonlake/romstage/power_state.c b/src/soc/intel/cannonlake/romstage/power_state.c<br>new file mode 100644<br>index 0000000..7f94014<br>--- /dev/null<br>+++ b/src/soc/intel/cannonlake/romstage/power_state.c<br>@@ -0,0 +1,35 @@<br>+/*<br>+ * This file is part of the coreboot project.<br>+ *<br>+ * Copyright (C) 2014 Google Inc.<br>+ * Copyright (C) 2015 Intel Corporation.<br>+ *<br>+ * This program is free software; you can redistribute it and/or modify<br>+ * it under the terms of the GNU General Public License as published by<br>+ * the Free Software Foundation; version 2 of the License.<br>+ *<br>+ * This program is distributed in the hope that it will be useful,<br>+ * but WITHOUT ANY WARRANTY; without even the implied warranty of<br>+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the<br>+ * GNU General Public License for more details.<br>+ */<br>+<br>+#include <arch/early_variables.h><br>+#include <arch/io.h><br>+#include <cbmem.h><br>+#include <console/console.h><br>+#include <soc/pm.h><br>+<br>+static struct chipset_power_state power_state CAR_GLOBAL;<br>+<br>+/* Fill power state structure from ACPI PM registers */<br>+struct chipset_power_state *fill_power_state(void)<br>+{<br>+ struct chipset_power_state *ps = car_get_var_ptr(&power_state);<br>+<br>+ ps->prev_sleep_state = 0;<br>+ printk(BIOS_DEBUG, "prev_sleep_state %d\n", ps->prev_sleep_state);<br>+ return ps;<br>+}<br>+<br>+<br>diff --git a/src/soc/intel/cannonlake/romstage/romstage.c b/src/soc/intel/cannonlake/romstage/romstage.c<br>new file mode 100644<br>index 0000000..5a860a2<br>--- /dev/null<br>+++ b/src/soc/intel/cannonlake/romstage/romstage.c<br>@@ -0,0 +1,43 @@<br>+/*<br>+ * This file is part of the coreboot project.<br>+ *<br>+ * Copyright (C) 2016 Intel Corp.<br>+ *<br>+ * This program is free software; you can redistribute it and/or modify<br>+ * it under the terms of the GNU General Public License as published by<br>+ * the Free Software Foundation; version 2 of the License.<br>+ *<br>+ * This program is distributed in the hope that it will be useful,<br>+ * but WITHOUT ANY WARRANTY; without even the implied warranty of<br>+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the<br>+ * GNU General Public License for more details.<br>+ */<br>+<br>+#include <arch/io.h><br>+#include <cbmem.h><br>+#include <console/console.h><br>+#include <fsp/util.h><br>+#include <memory_info.h><br>+#include <soc/pm.h><br>+#include <soc/romstage.h><br>+#include <timestamp.h><br>+<br>+asmlinkage void car_stage_entry(void)<br>+{<br>+ bool s3wake;<br>+ struct chipset_power_state *ps;<br>+<br>+ console_init();<br>+<br>+ /* Program MCHBAR, DMIBAR, GDXBAR and EDRAMBAR */<br>+ systemagent_early_init();<br>+<br>+ ps = fill_power_state();<br>+ timestamp_add_now(TS_START_ROMSTAGE);<br>+ s3wake = ps->prev_sleep_state == ACPI_S3;<br>+ fsp_memory_init(s3wake);<br>+}<br>+<br>+void platform_fsp_memory_init_params_cb(FSPM_UPD *mupd, uint32_t version)<br>+{<br>+}<br>diff --git a/src/soc/intel/cannonlake/romstage/systemagent.c b/src/soc/intel/cannonlake/romstage/systemagent.c<br>new file mode 100644<br>index 0000000..dc17506<br>--- /dev/null<br>+++ b/src/soc/intel/cannonlake/romstage/systemagent.c<br>@@ -0,0 +1,45 @@<br>+/*<br>+ * This file is part of the coreboot project.<br>+ *<br>+ * Copyright (C) 2007-2010 coresystems GmbH<br>+ * Copyright (C) 2014 Google Inc.<br>+ * Copyright (C) 2017 Intel Corporation.<br>+ *<br>+ * This program is free software; you can redistribute it and/or modify<br>+ * it under the terms of the GNU General Public License as published by<br>+ * the Free Software Foundation; version 2 of the License.<br>+ *<br>+ * This program is distributed in the hope that it will be useful,<br>+ * but WITHOUT ANY WARRANTY; without even the implied warranty of<br>+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the<br>+ * GNU General Public License for more details.<br>+ */<br>+<br>+#include <device/device.h><br>+#include <intelblocks/systemagent.h><br>+#include <soc/iomap.h><br>+#include <soc/romstage.h><br>+#include <soc/systemagent.h><br>+<br>+void systemagent_early_init(void)<br>+{<br>+ static const struct sa_mmio_descriptor soc_fixed_pci_resources[] = {<br>+ {MCHBAR, MCH_BASE_ADDRESS, MCH_BASE_SIZE, "MCHBAR"},<br>+ {DMIBAR, DMI_BASE_ADDRESS, DMI_BASE_SIZE, "DMIBAR"},<br>+ {EPBAR, EP_BASE_ADDRESS, EP_BASE_SIZE, "EPBAR"},<br>+ };<br>+<br>+ static const struct sa_mmio_descriptor soc_fixed_mch_resources[] = {<br>+ {REGBAR, REG_BASE_ADDRESS, REG_BASE_SIZE, "REGBAR"},<br>+ {EDRAMBAR, EDRAM_BASE_ADDRESS, EDRAM_BASE_SIZE, "EDRAMBAR"},<br>+ };<br>+<br>+ /* Set Fixed MMIO addresss into PCI configuration space */<br>+ sa_set_pci_bar(soc_fixed_pci_resources,<br>+ ARRAY_SIZE(soc_fixed_pci_resources));<br>+ /* Set Fixed MMIO addresss into MCH base address */<br>+ sa_set_mch_bar(soc_fixed_mch_resources,<br>+ ARRAY_SIZE(soc_fixed_mch_resources));<br>+ /* Enable PAM regisers */<br>+ enable_pam_region();<br>+}<br></pre><p>To view, visit <a href="https://review.coreboot.org/20497">change 20497</a>. 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<div style="display:none"> Gerrit-Project: coreboot </div>
<div style="display:none"> Gerrit-Branch: master </div>
<div style="display:none"> Gerrit-MessageType: newchange </div>
<div style="display:none"> Gerrit-Change-Id: Iab96b27d4220acf4089b901bca28018eaba940a1 </div>
<div style="display:none"> Gerrit-Change-Number: 20497 </div>
<div style="display:none"> Gerrit-PatchSet: 1 </div>
<div style="display:none"> Gerrit-Owner: Lijian Zhao <lijian.zhao@intel.com> </div>