<p>Lijian Zhao has uploaded this change for <strong>review</strong>.</p><p><a href="https://review.coreboot.org/20484">View Change</a></p><pre style="font-family: monospace,monospace; white-space: pre-wrap;">soc/intel/cannonlake: Add microcode support<br><br>Microcode need to loadded prior to FSP initialization.<br><br>Change-Id: Idd70bd3e6555866d9bb232e8904aed4120c79fe7<br>Signed-off-by: Lijian Zhao <lijian.zhao@intel.com><br>---<br>M src/soc/intel/cannonlake/Kconfig<br>M src/soc/intel/cannonlake/Makefile.inc<br>2 files changed, 3 insertions(+), 1 deletion(-)<br><br></pre><pre style="font-family: monospace,monospace; white-space: pre-wrap;">git pull ssh://review.coreboot.org:29418/coreboot refs/changes/84/20484/2</pre><pre style="font-family: monospace,monospace; white-space: pre-wrap;">diff --git a/src/soc/intel/cannonlake/Kconfig b/src/soc/intel/cannonlake/Kconfig<br>index 3012c61..de8125f 100644<br>--- a/src/soc/intel/cannonlake/Kconfig<br>+++ b/src/soc/intel/cannonlake/Kconfig<br>@@ -18,6 +18,7 @@<br>       select UDELAY_TSC<br>     select REG_SCRIPT<br>     select C_ENVIRONMENT_BOOTBLOCK<br>+       select CPU_INTEL_FIRMWARE_INTERFACE_TABLE<br>     select HAVE_HARD_RESET<br>        select HAVE_INTEL_FIRMWARE<br>    select INTEL_CAR_NEM_ENHANCED<br>@@ -35,6 +36,7 @@<br>      select SOC_INTEL_COMMON_BLOCK_SMBUS<br>   select SOC_INTEL_COMMON_BLOCK_RTC<br>     select SOC_INTEL_COMMON_BLOCK_CSE<br>+    select SUPPORT_CPU_UCODE_IN_CBFS<br> <br> config UART_DEBUG<br>       bool "Enable UART debug port."<br>diff --git a/src/soc/intel/cannonlake/Makefile.inc b/src/soc/intel/cannonlake/Makefile.inc<br>index 4651a23..bf14092 100644<br>--- a/src/soc/intel/cannonlake/Makefile.inc<br>+++ b/src/soc/intel/cannonlake/Makefile.inc<br>@@ -1,6 +1,6 @@<br> ifeq ($(CONFIG_SOC_INTEL_CANNONLAKE),y)<br> <br>-romstage-y += cbmem.c<br>+subdirs-y += ../../../cpu/intel/microcode<br> <br> ramstage-y += cbmem.c<br> <br></pre><p>To view, visit <a href="https://review.coreboot.org/20484">change 20484</a>. To unsubscribe, visit <a href="https://review.coreboot.org/settings">settings</a>.</p><div itemscope itemtype="http://schema.org/EmailMessage"><div itemscope itemprop="action" itemtype="http://schema.org/ViewAction"><link itemprop="url" href="https://review.coreboot.org/20484"/><meta itemprop="name" content="View Change"/></div></div>

<div style="display:none"> Gerrit-Project: coreboot </div>
<div style="display:none"> Gerrit-Branch: master </div>
<div style="display:none"> Gerrit-MessageType: newchange </div>
<div style="display:none"> Gerrit-Change-Id: Idd70bd3e6555866d9bb232e8904aed4120c79fe7 </div>
<div style="display:none"> Gerrit-Change-Number: 20484 </div>
<div style="display:none"> Gerrit-PatchSet: 2 </div>
<div style="display:none"> Gerrit-Owner: Lijian Zhao <lijian.zhao@intel.com> </div>
<div style="display:none"> Gerrit-Reviewer: Aaron Durbin <adurbin@chromium.org> </div>
<div style="display:none"> Gerrit-Reviewer: Andrey Petrov <andrey.petrov@intel.com> </div>
<div style="display:none"> Gerrit-Reviewer: Bora Guvendik <bora.guvendik@intel.com> </div>
<div style="display:none"> Gerrit-Reviewer: John Zhao <john.zhao@intel.com> </div>
<div style="display:none"> Gerrit-Reviewer: Subrata Banik <subrata.banik@intel.com> </div>
<div style="display:none"> Gerrit-Reviewer: build bot (Jenkins) <no-reply@coreboot.org> </div>