<p>Patrick Rudolph has uploaded this change for <strong>review</strong>.</p><p><a href="https://review.coreboot.org/20472">View Change</a></p><pre style="font-family: monospace,monospace; white-space: pre-wrap;">nb/intel/sandybridge/peg: Add PEG code<br><br>* Add ACPI code for PEG.<br>* Add PCIe driver for PEG.<br><br>Change-Id: I80a106b1f969103206f24dc5c4b268503acfa81f<br>Signed-off-by: Patrick Rudolph <siro@das-labor.org><br>---<br>M src/northbridge/intel/sandybridge/Makefile.inc<br>A src/northbridge/intel/sandybridge/acpi/peg.asl<br>M src/northbridge/intel/sandybridge/acpi/sandybridge.asl<br>A src/northbridge/intel/sandybridge/pcie.c<br>4 files changed, 137 insertions(+), 0 deletions(-)<br><br></pre><pre style="font-family: monospace,monospace; white-space: pre-wrap;">git pull ssh://review.coreboot.org:29418/coreboot refs/changes/72/20472/1</pre><pre style="font-family: monospace,monospace; white-space: pre-wrap;">diff --git a/src/northbridge/intel/sandybridge/Makefile.inc b/src/northbridge/intel/sandybridge/Makefile.inc<br>index 846d31b..a2ab06d 100644<br>--- a/src/northbridge/intel/sandybridge/Makefile.inc<br>+++ b/src/northbridge/intel/sandybridge/Makefile.inc<br>@@ -17,6 +17,7 @@<br> <br> ramstage-y += ram_calc.c<br> ramstage-y += northbridge.c<br>+ramstage-y += pcie.c<br> ramstage-y += gma.c<br> ramstage-$(CONFIG_SANDYBRIDGE_IVYBRIDGE_LVDS) += gma_sandybridge_lvds.c<br> ramstage-$(CONFIG_SANDYBRIDGE_IVYBRIDGE_LVDS) += gma_ivybridge_lvds.c<br>diff --git a/src/northbridge/intel/sandybridge/acpi/peg.asl b/src/northbridge/intel/sandybridge/acpi/peg.asl<br>new file mode 100644<br>index 0000000..18e3ff2<br>--- /dev/null<br>+++ b/src/northbridge/intel/sandybridge/acpi/peg.asl<br>@@ -0,0 +1,44 @@<br>+/*<br>+ * This file is part of the coreboot project.<br>+ *<br>+ * Copyright (C) 2017 Patrick Rudolph <siro@das-labor.org><br>+ *<br>+ * This program is free software; you can redistribute it and/or<br>+ * modify it under the terms of the GNU General Public License as<br>+ * published by the Free Software Foundation; version 2 of<br>+ * the License.<br>+ *<br>+ * This program is distributed in the hope that it will be useful,<br>+ * but WITHOUT ANY WARRANTY; without even the implied warranty of<br>+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the<br>+ * GNU General Public License for more details.<br>+ */<br>+<br>+Device (PEGP)<br>+{<br>+ Name (_ADR, 0x00010000)<br>+<br>+ // PCI Interrupt Routing.<br>+ Method (_PRT)<br>+ {<br>+ If (PICM) {<br>+ Return (Package() {<br>+ Package() { 0x0000ffff, 0, 0, 16 },<br>+ Package() { 0x0000ffff, 1, 0, 17 },<br>+ Package() { 0x0000ffff, 2, 0, 18 },<br>+ Package() { 0x0000ffff, 3, 0, 19 }<br>+ })<br>+ } Else {<br>+ Return (Package() {<br>+ Package() { 0x0000ffff, 0, \_SB.PCI0.LPCB.LNKA, 0 },<br>+ Package() { 0x0000ffff, 1, \_SB.PCI0.LPCB.LNKB, 0 },<br>+ Package() { 0x0000ffff, 2, \_SB.PCI0.LPCB.LNKC, 0 },<br>+ Package() { 0x0000ffff, 3, \_SB.PCI0.LPCB.LNKD, 0 }<br>+ })<br>+ }<br>+ }<br>+<br>+ Device (DEV0) {<br>+ Name(_ADR, 0x00000000)<br>+ }<br>+}<br>diff --git a/src/northbridge/intel/sandybridge/acpi/sandybridge.asl b/src/northbridge/intel/sandybridge/acpi/sandybridge.asl<br>index 609106f..301ee8a 100644<br>--- a/src/northbridge/intel/sandybridge/acpi/sandybridge.asl<br>+++ b/src/northbridge/intel/sandybridge/acpi/sandybridge.asl<br>@@ -16,6 +16,7 @@<br> <br> #include "../sandybridge.h"<br> #include "hostbridge.asl"<br>+#include "peg.asl"<br> <br> /* PCI Device Resource Consumption */<br> Device (PDRC)<br>diff --git a/src/northbridge/intel/sandybridge/pcie.c b/src/northbridge/intel/sandybridge/pcie.c<br>new file mode 100644<br>index 0000000..ba8da43<br>--- /dev/null<br>+++ b/src/northbridge/intel/sandybridge/pcie.c<br>@@ -0,0 +1,91 @@<br>+/*<br>+ * This file is part of the coreboot project.<br>+ *<br>+ * Copyright (C) 2017 Patrick Rudolph <siro@das-labor.org><br>+ *<br>+ * This program is free software; you can redistribute it and/or<br>+ * modify it under the terms of the GNU General Public License as<br>+ * published by the Free Software Foundation; version 2 of<br>+ * the License.<br>+ *<br>+ * This program is distributed in the hope that it will be useful,<br>+ * but WITHOUT ANY WARRANTY; without even the implied warranty of<br>+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the<br>+ * GNU General Public License for more details.<br>+ */<br>+<br>+#include <console/console.h><br>+#include <device/device.h><br>+#include <device/pci.h><br>+#include <device/pciexp.h><br>+#include <device/pci_ids.h><br>+#include <southbridge/intel/common/pciehp.h><br>+#include "sandybridge.h"<br>+<br>+static void pcie_disable(device_t dev)<br>+{<br>+ printk(BIOS_DEBUG, "%s: Disabling device\n", dev_path(dev));<br>+<br>+ dev->enabled = 0;<br>+}<br>+<br>+static const char *pcie_acpi_name(device_t dev)<br>+{<br>+ ASSERT(dev);<br>+ ASSERT(dev->bus);<br>+<br>+ if (dev->bus->secondary == 0 &&<br>+ PCI_SLOT(dev->path.pci.devfn) == 0x01 &&<br>+ PCI_FUNC(dev->path.pci.devfn) == 0x00)<br>+ return "PEGP";<br>+<br>+ ASSERT(dev->bus->dev);<br>+ ASSERT(dev->bus->dev->bus);<br>+<br>+ if (dev->bus->dev->bus->secondary == 0 &&<br>+ PCI_SLOT(dev->bus->dev->path.pci.devfn) == 0x01 &&<br>+ PCI_FUNC(dev->bus->dev->path.pci.devfn) == 0x00 &&<br>+ PCI_SLOT(dev->path.pci.devfn) == 0x00 &&<br>+ PCI_FUNC(dev->path.pci.devfn) == 0x00)<br>+ return "DEV0";<br>+<br>+ return NULL;<br>+}<br>+<br>+<br>+static void<br>+pcie_set_subsystem(device_t dev, unsigned int vendor, unsigned int device)<br>+{<br>+ /* NOTE: This is not the default position! */<br>+ if (!vendor || !device)<br>+ pci_write_config32(dev, 0x94,<br>+ pci_read_config32(dev, 0));<br>+ else<br>+ pci_write_config32(dev, 0x94,<br>+ ((device & 0xffff) << 16) | (vendor & 0xffff));<br>+}<br>+<br>+static struct pci_operations pci_ops = {<br>+ .set_subsystem = pcie_set_subsystem,<br>+};<br>+<br>+static struct device_operations device_ops = {<br>+ .read_resources = pci_bus_read_resources,<br>+ .set_resources = pci_dev_set_resources,<br>+ .enable_resources = pci_bus_enable_resources,<br>+ .scan_bus = pciexp_scan_bridge,<br>+ .reset_bus = pci_bus_reset,<br>+ .disable = pcie_disable,<br>+ .ops_pci = &pci_ops,<br>+ .acpi_name = pcie_acpi_name,<br>+};<br>+<br>+static const unsigned short pci_device_ids[] = { 0x0101, 0x0105, 0x0109, 0x010d,<br>+ 0x0151, 0x0155, 0x0159, 0x015d,<br>+ 0 };<br>+<br>+static const struct pci_driver pch_pcie __pci_driver = {<br>+ .ops = &device_ops,<br>+ .vendor = PCI_VENDOR_ID_INTEL,<br>+ .devices = pci_device_ids,<br>+};<br></pre><p>To view, visit <a href="https://review.coreboot.org/20472">change 20472</a>. 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<div style="display:none"> Gerrit-Project: coreboot </div>
<div style="display:none"> Gerrit-Branch: master </div>
<div style="display:none"> Gerrit-MessageType: newchange </div>
<div style="display:none"> Gerrit-Change-Id: I80a106b1f969103206f24dc5c4b268503acfa81f </div>
<div style="display:none"> Gerrit-Change-Number: 20472 </div>
<div style="display:none"> Gerrit-PatchSet: 1 </div>
<div style="display:none"> Gerrit-Owner: Patrick Rudolph <siro@das-labor.org> </div>