<p>Ryan Salsamendi has uploaded this change for <strong>review</strong>.</p><p><a href="https://review.coreboot.org/20465">View Change</a></p><pre style="font-family: monospace,monospace; white-space: pre-wrap;">northbridge/intel/haswell: Fix undefined behavior<br><br>Fix undefined behavior found by clang's -Wshift-sign-overflow, find,<br>and source inspection. Left shifting an int where the right operand is<br>>= the width of the type is undefined. Add UL suffix since it's safe<br>for unsigned types.<br><br>Change-Id: Id1ed2252ce3ed052730dd10b24c453c34c2ab4ff<br>Signed-off-by: Ryan Salsamendi <rsalsamendi@hotmail.com><br>---<br>M src/northbridge/intel/haswell/acpi.c<br>M src/northbridge/intel/haswell/early_init.c<br>M src/northbridge/intel/haswell/finalize.c<br>3 files changed, 11 insertions(+), 7 deletions(-)<br><br></pre><pre style="font-family: monospace,monospace; white-space: pre-wrap;">git pull ssh://review.coreboot.org:29418/coreboot refs/changes/65/20465/1</pre><pre style="font-family: monospace,monospace; white-space: pre-wrap;">diff --git a/src/northbridge/intel/haswell/acpi.c b/src/northbridge/intel/haswell/acpi.c<br>index 8afef00..e032948 100644<br>--- a/src/northbridge/intel/haswell/acpi.c<br>+++ b/src/northbridge/intel/haswell/acpi.c<br>@@ -29,6 +29,7 @@<br> u32 pciexbar = 0;<br> u32 pciexbar_reg;<br> int max_buses;<br>+ u32 mask;<br> <br> dev = dev_find_slot(0, PCI_DEVFN(0, 0));<br> if (!dev)<br>@@ -40,17 +41,20 @@<br> if (!(pciexbar_reg & (1 << 0)))<br> return current;<br> <br>+ mask = (1UL << 31) | (1 << 30) | (1 << 29) | (1 << 28);<br> switch ((pciexbar_reg >> 1) & 3) {<br> case 0: // 256MB<br>- pciexbar = pciexbar_reg & ((1 << 31)|(1 << 30)|(1 << 29)|(1 << 28));<br>+ pciexbar = pciexbar_reg & mask;<br> max_buses = 256;<br> break;<br> case 1: // 128M<br>- pciexbar = pciexbar_reg & ((1 << 31)|(1 << 30)|(1 << 29)|(1 << 28)|(1 << 27));<br>+ mask |= (1 << 27);<br>+ pciexbar = pciexbar_reg & mask;<br> max_buses = 128;<br> break;<br> case 2: // 64M<br>- pciexbar = pciexbar_reg & ((1 << 31)|(1 << 30)|(1 << 29)|(1 << 28)|(1 << 27)|(1 << 26));<br>+ mask |= (1 << 27) | (1 << 26);<br>+ pciexbar = pciexbar_reg & mask;<br> max_buses = 64;<br> break;<br> default: // RSVD<br>diff --git a/src/northbridge/intel/haswell/early_init.c b/src/northbridge/intel/haswell/early_init.c<br>index f426339..a2b0f7f 100644<br>--- a/src/northbridge/intel/haswell/early_init.c<br>+++ b/src/northbridge/intel/haswell/early_init.c<br>@@ -81,7 +81,7 @@<br> <br> /* GPU RC6 workaround for sighting 366252 */<br> reg32 = MCHBAR32(0x5d14);<br>- reg32 |= (1 << 31);<br>+ reg32 |= (1UL << 31);<br> MCHBAR32(0x5d14) = reg32;<br> <br> /* VLW */<br>diff --git a/src/northbridge/intel/haswell/finalize.c b/src/northbridge/intel/haswell/finalize.c<br>index 5a82449..04f7356 100644<br>--- a/src/northbridge/intel/haswell/finalize.c<br>+++ b/src/northbridge/intel/haswell/finalize.c<br>@@ -35,11 +35,11 @@<br> pci_or_config32(PCI_DEV_HSW, 0xbc, 1 << 0); /* TOLUD */<br> <br> MCHBAR32_OR(0x5500, 1 << 0); /* PAVP */<br>- MCHBAR32_OR(0x5f00, 1 << 31); /* SA PM */<br>+ MCHBAR32_OR(0x5f00, 1UL << 31); /* SA PM */<br> MCHBAR32_OR(0x6020, 1 << 0); /* UMA GFX */<br> MCHBAR32_OR(0x63fc, 1 << 0); /* VTDTRK */<br>- MCHBAR32_OR(0x6800, 1 << 31);<br>- MCHBAR32_OR(0x7000, 1 << 31);<br>+ MCHBAR32_OR(0x6800, 1UL << 31);<br>+ MCHBAR32_OR(0x7000, 1UL << 31);<br> MCHBAR32_OR(0x77fc, 1 << 0);<br> <br> /* Memory Controller Lockdown */<br></pre><p>To view, visit <a href="https://review.coreboot.org/20465">change 20465</a>. To unsubscribe, visit <a href="https://review.coreboot.org/settings">settings</a>.</p><div itemscope itemtype="http://schema.org/EmailMessage"><div itemscope itemprop="action" itemtype="http://schema.org/ViewAction"><link itemprop="url" href="https://review.coreboot.org/20465"/><meta itemprop="name" content="View Change"/></div></div>
<div style="display:none"> Gerrit-Project: coreboot </div>
<div style="display:none"> Gerrit-Branch: master </div>
<div style="display:none"> Gerrit-MessageType: newchange </div>
<div style="display:none"> Gerrit-Change-Id: Id1ed2252ce3ed052730dd10b24c453c34c2ab4ff </div>
<div style="display:none"> Gerrit-Change-Number: 20465 </div>
<div style="display:none"> Gerrit-PatchSet: 1 </div>
<div style="display:none"> Gerrit-Owner: Ryan Salsamendi <rsalsamendi@hotmail.com> </div>