<p>Ryan Salsamendi has uploaded this change for <strong>review</strong>.</p><p><a href="https://review.coreboot.org/20466">View Change</a></p><pre style="font-family: monospace,monospace; white-space: pre-wrap;">drivers/intel/gma: Fix undefined behavior<br><br>Fix undefined behavior found by clang's -Wshift-sign-overflow, find,<br>and source inspection. Left shifting an int where the right operand is<br>>= the width of the type is undefined. Add UL suffix since it's safe<br>for unsigned types.<br><br>Change-Id: I5240a19647c8ad59f64925f3e1c199446a886d2d<br>Signed-off-by: Ryan Salsamendi <rsalsamendi@hotmail.com><br>---<br>M src/drivers/intel/gma/i915.h<br>M src/drivers/intel/gma/i915_reg.h<br>M src/drivers/intel/gma/intel_bios.h<br>M src/drivers/intel/gma/opregion.h<br>4 files changed, 76 insertions(+), 76 deletions(-)<br><br></pre><pre style="font-family: monospace,monospace; white-space: pre-wrap;">git pull ssh://review.coreboot.org:29418/coreboot refs/changes/66/20466/1</pre><pre style="font-family: monospace,monospace; white-space: pre-wrap;">diff --git a/src/drivers/intel/gma/i915.h b/src/drivers/intel/gma/i915.h<br>index 9a2acdb..22b4f34 100644<br>--- a/src/drivers/intel/gma/i915.h<br>+++ b/src/drivers/intel/gma/i915.h<br>@@ -33,7 +33,7 @@<br> <br> /* things that are, strangely, not defined anywhere? */<br> #define PCH_PP_UNLOCK 0xabcd0000<br>-#define WMx_LP_SR_EN (1<<31)<br>+#define WMx_LP_SR_EN (1UL<<31)<br> #define PRB0_TAIL 0x02030<br> #define PRB0_HEAD 0x02034<br> #define PRB0_START 0x02038<br>diff --git a/src/drivers/intel/gma/i915_reg.h b/src/drivers/intel/gma/i915_reg.h<br>index e88ecfb..ae774a5 100644<br>--- a/src/drivers/intel/gma/i915_reg.h<br>+++ b/src/drivers/intel/gma/i915_reg.h<br>@@ -600,7 +600,7 @@<br> #define FW_BLC 0x020d8<br> #define FW_BLC2 0x020dc<br> #define FW_BLC_SELF 0x020e0 /* 915+ only */<br>-#define FW_BLC_SELF_EN_MASK (1<<31)<br>+#define FW_BLC_SELF_EN_MASK (1UL<<31)<br> #define FW_BLC_SELF_FIFO_MASK (1<<16) /* 945 only */<br> #define FW_BLC_SELF_EN (1<<15) /* 945 only */<br> #define MM_BURST_LENGTH 0x00700000<br>@@ -751,7 +751,7 @@<br> #define FBC_CFB_BASE 0x03200 /* 4k page aligned */<br> #define FBC_LL_BASE 0x03204 /* 4k page aligned */<br> #define FBC_CONTROL 0x03208<br>-#define FBC_CTL_EN (1<<31)<br>+#define FBC_CTL_EN (1UL<<31)<br> #define FBC_CTL_PERIODIC (1<<30)<br> #define FBC_CTL_INTERVAL_SHIFT (16)<br> #define FBC_CTL_UNCOMPRESSIBLE (1<<14)<br>@@ -761,7 +761,7 @@<br> #define FBC_COMMAND 0x0320c<br> #define FBC_CMD_COMPRESS (1<<0)<br> #define FBC_STATUS 0x03210<br>-#define FBC_STAT_COMPRESSING (1<<31)<br>+#define FBC_STAT_COMPRESSING (1UL<<31)<br> #define FBC_STAT_COMPRESSED (1<<30)<br> #define FBC_STAT_MODIFIED (1<<29)<br> #define FBC_STAT_CURRENT_LINE (1<<0)<br>@@ -782,7 +782,7 @@<br> /* Framebuffer compression for GM45+ */<br> #define DPFC_CB_BASE 0x3200<br> #define DPFC_CONTROL 0x3208<br>-#define DPFC_CTL_EN (1<<31)<br>+#define DPFC_CTL_EN (1UL<<31)<br> #define DPFC_CTL_PLANEA (0<<30)<br> #define DPFC_CTL_PLANEB (1<<30)<br> #define DPFC_CTL_FENCE_EN (1<<29)<br>@@ -805,7 +805,7 @@<br> #define DPFC_STATUS2 0x3214<br> #define DPFC_FENCE_YOFF 0x3218<br> #define DPFC_CHICKEN 0x3224<br>-#define DPFC_HT_MODIFY (1<<31)<br>+#define DPFC_HT_MODIFY (1UL<<31)<br> <br> /* Framebuffer compression for Ironlake */<br> #define ILK_DPFC_CB_BASE 0x43200<br>@@ -878,7 +878,7 @@<br> #define GMBUS_NUM_PORTS (GMBUS_PORT_DPD - GMBUS_PORT_SSC + 1)<br> #define GMBUS_PORT_MASK 7<br> #define GMBUS1 0x5104 /* command/status */<br>-#define GMBUS_SW_CLR_INT (1<<31)<br>+#define GMBUS_SW_CLR_INT (1UL<<31)<br> #define GMBUS_SW_RDY (1<<30)<br> #define GMBUS_ENT (1<<29) /* enable timeout */<br> #define GMBUS_CYCLE_NONE (0<<25)<br>@@ -906,7 +906,7 @@<br> #define GMBUS_HW_WAIT_EN (1<<1)<br> #define GMBUS_HW_RDY_EN (1<<0)<br> #define GMBUS5 0x5120 /* byte index */<br>-#define GMBUS_2BYTE_INDEX_EN (1<<31)<br>+#define GMBUS_2BYTE_INDEX_EN (1UL<<31)<br> <br> /*<br> * Clock control & power management<br>@@ -926,7 +926,7 @@<br> #define _DPLL_A 0x06014<br> #define _DPLL_B 0x06018<br> #define DPLL(pipe) _PIPE(pipe, _DPLL_A, _DPLL_B)<br>-#define DPLL_VCO_ENABLE (1 << 31)<br>+#define DPLL_VCO_ENABLE (1UL << 31)<br> #define DPLL_DVO_HIGH_SPEED (1 << 30)<br> #define DPLL_EXT_BUFFER_ENABLE_VLV (1 << 30)<br> #define DPLL_SYNCLOCK_ENABLE (1 << 29)<br>@@ -954,11 +954,11 @@<br> #define PPCR_ON (1<<0)<br> <br> #define DVOB 0x61140<br>-#define DVOB_ON (1<<31)<br>+#define DVOB_ON (1UL<<31)<br> #define DVOC 0x61160<br>-#define DVOC_ON (1<<31)<br>+#define DVOC_ON (1UL<<31)<br> #define LVDS 0x61180<br>-#define LVDS_ON (1<<31)<br>+#define LVDS_ON (1UL<<31)<br> #define LVDS_CLOCK_A_POWERUP_ALL (3 << 8)<br> #define LVDS_CLOCK_B_POWERUP_ALL (3 << 4)<br> #define LVDS_CLOCK_BOTH_POWERUP_ALL (3 << 2)<br>@@ -1301,7 +1301,7 @@<br> #define PCH_ADPA 0xe1100<br> #define VLV_ADPA (VLV_DISPLAY_BASE + ADPA)<br> <br>-#define ADPA_DAC_ENABLE (1<<31)<br>+#define ADPA_DAC_ENABLE (1UL<<31)<br> #define ADPA_DAC_DISABLE 0<br> #define ADPA_PIPE_SELECT_MASK (1<<30)<br> #define ADPA_PIPE_A_SELECT 0<br>@@ -1405,7 +1405,7 @@<br> /* SDVO port control */<br> #define SDVOB 0x61140<br> #define SDVOC 0x61160<br>-#define SDVO_ENABLE (1 << 31)<br>+#define SDVO_ENABLE (1UL << 31)<br> #define SDVO_PIPE_B_SELECT (1 << 30)<br> #define SDVO_STALL_SELECT (1 << 29)<br> #define SDVO_INTERRUPT_ENABLE (1 << 26)<br>@@ -1443,7 +1443,7 @@<br> #define DVOA 0x61120<br> #define DVOB 0x61140<br> #define DVOC 0x61160<br>-#define DVO_ENABLE (1 << 31)<br>+#define DVO_ENABLE (1UL << 31)<br> #define DVO_PIPE_B_SELECT (1 << 30)<br> #define DVO_PIPE_STALL_UNUSED (0 << 28)<br> #define DVO_PIPE_STALL (1 << 28)<br>@@ -1479,7 +1479,7 @@<br> * Enables the LVDS port. This bit must be set before DPLLs are enabled, as<br> * the DPLL semantics change when the LVDS is assigned to that pipe.<br> */<br>-#define LVDS_PORT_EN (1 << 31)<br>+#define LVDS_PORT_EN (1UL << 31)<br> /* Selects pipe B for LVDS data. Must be set on pre-965. */<br> #define LVDS_PIPEB_SELECT (1 << 30)<br> #define LVDS_PIPE_MASK (1 << 30)<br>@@ -1531,7 +1531,7 @@<br> #define VIDEO_DIP_DATA_SIZE 32<br> #define VIDEO_DIP_CTL 0x61170<br> /* Pre HSW: */<br>-#define VIDEO_DIP_ENABLE (1 << 31)<br>+#define VIDEO_DIP_ENABLE (1UL << 31)<br> #define VIDEO_DIP_PORT_B (1 << 29)<br> #define VIDEO_DIP_PORT_C (2 << 29)<br> #define VIDEO_DIP_PORT_D (3 << 29)<br>@@ -1559,7 +1559,7 @@<br> <br> /* Panel power sequencing */<br> #define PP_STATUS 0x61200<br>-#define PP_ON (1 << 31)<br>+#define PP_ON (1UL << 31)<br> /*<br> * Indicates that all dependencies of the panel are on:<br> *<br>@@ -1592,7 +1592,7 @@<br> <br> /* Panel fitting */<br> #define PFIT_CONTROL 0x61230<br>-#define PFIT_ENABLE (1 << 31)<br>+#define PFIT_ENABLE (1UL << 31)<br> #define PFIT_PIPE_MASK (3 << 29)<br> #define PFIT_PIPE_SHIFT 29<br> #define VERT_INTERP_DISABLE (0 << 10)<br>@@ -1627,7 +1627,7 @@<br> <br> /* Backlight control */<br> #define BLC_PWM_CTL2 0x61250 /* 965+ only */<br>-#define BLM_PWM_ENABLE (1 << 31)<br>+#define BLM_PWM_ENABLE (1UL << 31)<br> #define BLM_COMBINATION_MODE (1 << 30) /* gen4 only */<br> #define BLM_PIPE_SELECT (1 << 29)<br> #define BLM_PIPE_SELECT_IVB (3 << 29)<br>@@ -1672,11 +1672,11 @@<br> /* New registers for PCH-split platforms. Safe where new bits show up, the<br> * register layout machtes with gen4 BLC_PWM_CTL[12]. */<br> #define BLC_PWM_CPU_CTL2 0x48250<br>-#define BLC_PWM2_ENABLE (1<<31)<br>+#define BLC_PWM2_ENABLE (1UL<<31)<br> #define BLC_PWM_CPU_CTL 0x48254<br> <br> #define BLM_HIST_CTL 0x48260<br>-#define ENH_HIST_ENABLE (1<<31)<br>+#define ENH_HIST_ENABLE (1UL<<31)<br> #define ENH_MODIF_TBL_ENABLE (1<<30)<br> #define ENH_PIPE_A_SELECT (0<<29)<br> #define ENH_PIPE_B_SELECT (1<<29)<br>@@ -1692,7 +1692,7 @@<br> #define BLM_HIST_ENH 0x48264<br> <br> #define BLM_HIST_GUARD_BAND 0x48268<br>-#define BLM_HIST_INTR_ENABLE (1<<31)<br>+#define BLM_HIST_INTR_ENABLE (1UL<<31)<br> #define BLM_HIST_EVENT_STATUS (1<<30)<br> #define BLM_HIST_INTR_DELAY_MASK (0xFF<<22)<br> #define BLM_HIST_INTR_DELAY_SHIFT 22<br>@@ -1700,7 +1700,7 @@<br> /* PCH CTL1 is totally different, all but the below bits are reserved. CTL2 is<br> * like the normal CTL from gen4 and earlier. Hooray for confusing naming. */<br> #define BLC_PWM_PCH_CTL1 0xc8250<br>-#define BLM_PCH_PWM_ENABLE (1 << 31)<br>+#define BLM_PCH_PWM_ENABLE (1UL << 31)<br> #define BLM_PCH_OVERRIDE_ENABLE (1 << 30)<br> #define BLM_PCH_POLARITY (1 << 29)<br> #define BLC_PWM_PCH_CTL2 0xc8254<br>@@ -1708,7 +1708,7 @@<br> /* TV port control */<br> #define TV_CTL 0x68000<br> /** Enables the TV encoder */<br>-# define TV_ENC_ENABLE (1 << 31)<br>+# define TV_ENC_ENABLE (1UL << 31)<br> /** Sources the TV encoder input from pipe B instead of A. */<br> # define TV_ENC_PIPEB_SELECT (1 << 30)<br> /** Outputs composite video (DAC A only) */<br>@@ -1780,7 +1780,7 @@<br> *<br> * This gets cleared when TV_DAC_STATE_EN is cleared<br> */<br>-# define TVDAC_STATE_CHG (1 << 31)<br>+# define TVDAC_STATE_CHG (1UL << 31)<br> # define TVDAC_SENSE_MASK (7 << 28)<br> /** Reports that DAC A voltage is above the detect threshold */<br> # define TVDAC_A_SENSE (1 << 30)<br>@@ -1907,7 +1907,7 @@<br> <br> #define TV_H_CTL_2 0x68034<br> /** Enables the colorburst (needed for non-component color) */<br>-# define TV_BURST_ENA (1 << 31)<br>+# define TV_BURST_ENA (1UL << 31)<br> /** Offset of the colorburst from the start of hsync, in pixels minus one. */<br> # define TV_HBURST_START_SHIFT 16<br> # define TV_HBURST_START_MASK 0x1fff0000<br>@@ -1952,7 +1952,7 @@<br> <br> #define TV_V_CTL_3 0x68044<br> /** Enables generation of the equalization signal */<br>-# define TV_EQUAL_ENA (1 << 31)<br>+# define TV_EQUAL_ENA (1UL << 31)<br> /** Length of vsync, in half lines */<br> # define TV_VEQ_LEN_MASK 0x007f0000<br> # define TV_VEQ_LEN_SHIFT 16<br>@@ -2026,7 +2026,7 @@<br> <br> #define TV_SC_CTL_1 0x68060<br> /** Turns on the first subcarrier phase generation DDA */<br>-# define TV_SC_DDA1_EN (1 << 31)<br>+# define TV_SC_DDA1_EN (1UL << 31)<br> /** Turns on the first subcarrier phase generation DDA */<br> # define TV_SC_DDA2_EN (1 << 30)<br> /** Turns on the first subcarrier phase generation DDA */<br>@@ -2089,7 +2089,7 @@<br> * If set, the rest of the registers are ignored, and the calculated values can<br> * be read back from the register.<br> */<br>-# define TV_AUTO_SCALE (1 << 31)<br>+# define TV_AUTO_SCALE (1UL << 31)<br> /**<br> * Disables the vertical filter.<br> *<br>@@ -2152,7 +2152,7 @@<br> # define TV_VSCALE_IP_FRAC_SHIFT 0<br> <br> #define TV_CC_CONTROL 0x68090<br>-# define TV_CC_ENABLE (1 << 31)<br>+# define TV_CC_ENABLE (1UL << 31)<br> /**<br> * Specifies which field to send the CC data in.<br> *<br>@@ -2168,7 +2168,7 @@<br> # define TV_CC_LINE_SHIFT 0<br> <br> #define TV_CC_DATA 0x68094<br>-# define TV_CC_RDY (1 << 31)<br>+# define TV_CC_RDY (1UL << 31)<br> /** Second word of CC data to be transmitted. */<br> # define TV_CC_DATA_2_MASK 0x007f0000<br> # define TV_CC_DATA_2_SHIFT 16<br>@@ -2191,7 +2191,7 @@<br> #define DP_C 0x64200<br> #define DP_D 0x64300<br> <br>-#define DP_PORT_EN (1 << 31)<br>+#define DP_PORT_EN (1UL << 31)<br> #define DP_PIPEB_SELECT (1 << 30)<br> #define DP_PIPE_MASK (1 << 30)<br> <br>@@ -2301,7 +2301,7 @@<br> #define DPD_AUX_CH_DATA4 0x64320<br> #define DPD_AUX_CH_DATA5 0x64324<br> <br>-#define DP_AUX_CH_CTL_SEND_BUSY (1 << 31)<br>+#define DP_AUX_CH_CTL_SEND_BUSY (1UL << 31)<br> #define DP_AUX_CH_CTL_DONE (1 << 30)<br> #define DP_AUX_CH_CTL_INTERRUPT (1 << 29)<br> #define DP_AUX_CH_CTL_TIME_OUT_ERROR (1 << 28)<br>@@ -2380,7 +2380,7 @@<br> #define DSL_LINEMASK_GEN2 0x00000fff<br> #define DSL_LINEMASK_GEN3 0x00001fff<br> #define _PIPEACONF 0x70008<br>-#define PIPECONF_ENABLE (1<<31)<br>+#define PIPECONF_ENABLE (1UL<<31)<br> #define PIPECONF_DISABLE 0<br> #define PIPECONF_DOUBLE_WIDE (1<<30)<br> #define I965_PIPECONF_ACTIVE (1<<30)<br>@@ -2524,7 +2524,7 @@<br> #define DSPFW_CURSORA_SHIFT 8<br> #define DSPFW_PLANEC_MASK (0x7f)<br> #define DSPFW3 0x7003c<br>-#define DSPFW_HPLL_SR_EN (1<<31)<br>+#define DSPFW_HPLL_SR_EN (1UL<<31)<br> #define DSPFW_CURSOR_SR_SHIFT 24<br> #define PINEVIEW_SELF_REFRESH_EN (1<<30)<br> #define DSPFW_CURSOR_SR_MASK (0x3f<<24)<br>@@ -2536,14 +2536,14 @@<br> #define DRAIN_LATENCY_PRECISION_32 32<br> #define DRAIN_LATENCY_PRECISION_16 16<br> #define VLV_DDL1 0x70050<br>-#define DDL_CURSORA_PRECISION_32 (1<<31)<br>-#define DDL_CURSORA_PRECISION_16 (0<<31)<br>+#define DDL_CURSORA_PRECISION_32 (1UL<<31)<br>+#define DDL_CURSORA_PRECISION_16 (0UL<<31)<br> #define DDL_CURSORA_SHIFT 24<br> #define DDL_PLANEA_PRECISION_32 (1<<7)<br> #define DDL_PLANEA_PRECISION_16 (0<<7)<br> #define VLV_DDL2 0x70054<br>-#define DDL_CURSORB_PRECISION_32 (1<<31)<br>-#define DDL_CURSORB_PRECISION_16 (0<<31)<br>+#define DDL_CURSORB_PRECISION_32 (1UL<<31)<br>+#define DDL_CURSORB_PRECISION_16 (0UL<<31)<br> #define DDL_CURSORB_SHIFT 24<br> #define DDL_PLANEB_PRECISION_32 (1<<7)<br> #define DDL_PLANEB_PRECISION_16 (0<<7)<br>@@ -2592,7 +2592,7 @@<br> #define WM0_PIPEB_ILK 0x45104<br> #define WM0_PIPEC_IVB 0x45200<br> #define WM1_LP_ILK 0x45108<br>-#define WM1_LP_SR_EN (1<<31)<br>+#define WM1_LP_SR_EN (1UL<<31)<br> #define WM1_LP_LATENCY_SHIFT 24<br> #define WM1_LP_LATENCY_MASK (0x7f<<24)<br> #define WM1_LP_FBC_MASK (0xf<<20)<br>@@ -2601,13 +2601,13 @@<br> #define WM1_LP_SR_SHIFT 8<br> #define WM1_LP_CURSOR_MASK (0x3f)<br> #define WM2_LP_ILK 0x4510c<br>-#define WM2_LP_EN (1<<31)<br>+#define WM2_LP_EN (1UL<<31)<br> #define WM3_LP_ILK 0x45110<br>-#define WM3_LP_EN (1<<31)<br>+#define WM3_LP_EN (1UL<<31)<br> #define WM1S_LP_ILK 0x45120<br> #define WM2S_LP_IVB 0x45124<br> #define WM3S_LP_IVB 0x45128<br>-#define WM1S_LP_EN (1<<31)<br>+#define WM1S_LP_EN (1UL<<31)<br> <br> /* Memory latency timer register */<br> #define MLTR_ILK 0x11222<br>@@ -2730,7 +2730,7 @@<br> <br> /* Display A control */<br> #define _DSPACNTR 0x70180<br>-#define DISPLAY_PLANE_ENABLE (1<<31)<br>+#define DISPLAY_PLANE_ENABLE (1UL<<31)<br> #define DISPLAY_PLANE_DISABLE 0<br> #define DISPPLANE_GAMMA_ENABLE (1<<30)<br> #define DISPPLANE_GAMMA_DISABLE 0<br>@@ -2831,7 +2831,7 @@<br> <br> /* Sprite A control */<br> #define _DVSACNTR 0x72180<br>-#define DVS_ENABLE (1<<31)<br>+#define DVS_ENABLE (1UL<<31)<br> #define DVS_GAMMA_ENABLE (1<<30)<br> #define DVS_PIXFORMAT_MASK (3<<25)<br> #define DVS_FORMAT_YUV422 (0<<25)<br>@@ -2859,7 +2859,7 @@<br> #define _DVSATILEOFF 0x721a4<br> #define _DVSASURFLIVE 0x721ac<br> #define _DVSASCALE 0x72204<br>-#define DVS_SCALE_ENABLE (1<<31)<br>+#define DVS_SCALE_ENABLE (1UL<<31)<br> #define DVS_FILTER_MASK (3<<29)<br> #define DVS_FILTER_MEDIUM (0<<29)<br> #define DVS_FILTER_ENHANCING (1<<29)<br>@@ -2896,7 +2896,7 @@<br> #define DVSSURFLIVE(pipe) _PIPE(pipe, _DVSASURFLIVE, _DVSBSURFLIVE)<br> <br> #define _SPRA_CTL 0x70280<br>-#define SPRITE_ENABLE (1<<31)<br>+#define SPRITE_ENABLE (1UL<<31)<br> #define SPRITE_GAMMA_ENABLE (1<<30)<br> #define SPRITE_PIXFORMAT_MASK (7<<25)<br> #define SPRITE_FORMAT_YUV422 (0<<25)<br>@@ -2931,7 +2931,7 @@<br> #define _SPRA_OFFSET 0x702a4<br> #define _SPRA_SURFLIVE 0x702ac<br> #define _SPRA_SCALE 0x70304<br>-#define SPRITE_SCALE_ENABLE (1<<31)<br>+#define SPRITE_SCALE_ENABLE (1UL<<31)<br> #define SPRITE_FILTER_MASK (3<<29)<br> #define SPRITE_FILTER_MEDIUM (0<<29)<br> #define SPRITE_FILTER_ENHANCING (1<<29)<br>@@ -2972,7 +2972,7 @@<br> <br> /* VBIOS regs */<br> #define VGACNTRL 0x71400<br>-# define VGA_DISP_DISABLE (1 << 31)<br>+# define VGA_DISP_DISABLE (1UL << 31)<br> # define VGA_2X_MODE (1 << 30)<br> # define VGA_PIPE_B_SELECT (1 << 29)<br> <br>@@ -3070,7 +3070,7 @@<br> /* IVB+ has 3 fitters, 0 is 7x5 capable, the other two only 3x3 */<br> #define _PFA_CTL_1 0x68080<br> #define _PFB_CTL_1 0x68880<br>-#define PF_ENABLE (1<<31)<br>+#define PF_ENABLE (1UL<<31)<br> #define PF_PIPE_SEL_MASK_IVB (3<<29)<br> #define PF_PIPE_SEL_IVB(pipe) ((pipe)<<29)<br> #define PF_FILTER_MASK (3<<23)<br>@@ -3099,7 +3099,7 @@<br> #define LGC_PALETTE(pipe) _PIPE(pipe, _LGC_PALETTE_A, _LGC_PALETTE_B)<br> <br> /* interrupts */<br>-#define DE_MASTER_IRQ_CONTROL (1 << 31)<br>+#define DE_MASTER_IRQ_CONTROL (1UL << 31)<br> #define DE_SPRITEB_FLIP_DONE (1 << 29)<br> #define DE_SPRITEA_FLIP_DONE (1 << 28)<br> #define DE_PLANEB_FLIP_DONE (1 << 27)<br>@@ -3142,7 +3142,7 @@<br> #define DE_PIPEA_VBLANK_IVB (1<<0)<br> <br> #define VLV_MASTER_IER 0x4400c /* Gunit master IER */<br>-#define MASTER_INTERRUPT_ENABLE (1<<31)<br>+#define MASTER_INTERRUPT_ENABLE (1UL<<31)<br> <br> #define DEISR 0x44000<br> #define DEIMR 0x44004<br>@@ -3175,7 +3175,7 @@<br> #define ILK_DPARB_GATE (1<<22)<br> #define ILK_VSDPFD_FULL (1<<21)<br> #define ILK_DISPLAY_CHICKEN_FUSES 0x42014<br>-#define ILK_INTERNAL_GRAPHICS_DISABLE (1<<31)<br>+#define ILK_INTERNAL_GRAPHICS_DISABLE (1UL<<31)<br> #define ILK_INTERNAL_DISPLAY_DISABLE (1<<30)<br> #define ILK_DISPLAY_DEBUG_DISABLE (1<<29)<br> #define ILK_HDCP_DISABLE (1<<25)<br>@@ -3258,7 +3258,7 @@<br> #define SDE_TRANS_MASK (0x3f)<br> <br> /* south display engine interrupt: CPT/PPT */<br>-#define SDE_AUDIO_POWER_D_CPT (1 << 31)<br>+#define SDE_AUDIO_POWER_D_CPT (1UL << 31)<br> #define SDE_AUDIO_POWER_C_CPT (1 << 30)<br> #define SDE_AUDIO_POWER_B_CPT (1 << 29)<br> #define SDE_AUDIO_POWER_SHIFT_CPT 29<br>@@ -3541,8 +3541,8 @@<br> #define _PCH_TRANSACONF 0xf0008<br> #define _PCH_TRANSBCONF 0xf1008<br> #define PCH_TRANSCONF(plane) _PIPE(plane, _PCH_TRANSACONF, _PCH_TRANSBCONF)<br>-#define TRANS_DISABLE (0<<31)<br>-#define TRANS_ENABLE (1<<31)<br>+#define TRANS_DISABLE (0UL<<31)<br>+#define TRANS_ENABLE (1UL<<31)<br> #define TRANS_STATE_MASK (1<<30)<br> #define TRANS_STATE_DISABLE (0<<30)<br> #define TRANS_STATE_ENABLE (1<<30)<br>@@ -3568,7 +3568,7 @@<br> #define _TRANSA_CHICKEN2 0xf0064<br> #define _TRANSB_CHICKEN2 0xf1064<br> #define TRANS_CHICKEN2(pipe) _PIPE(pipe, _TRANSA_CHICKEN2, _TRANSB_CHICKEN2)<br>-#define TRANS_CHICKEN2_TIMING_OVERRIDE (1<<31)<br>+#define TRANS_CHICKEN2_TIMING_OVERRIDE (1UL<<31)<br> <br> <br> #define SOUTH_CHICKEN1 0xc2000<br>@@ -3596,8 +3596,8 @@<br> #define _FDI_TXA_CTL 0x60100<br> #define _FDI_TXB_CTL 0x61100<br> #define FDI_TX_CTL(pipe) _PIPE(pipe, _FDI_TXA_CTL, _FDI_TXB_CTL)<br>-#define FDI_TX_DISABLE (0<<31)<br>-#define FDI_TX_ENABLE (1<<31)<br>+#define FDI_TX_DISABLE (0UL<<31)<br>+#define FDI_TX_ENABLE (1UL<<31)<br> #define FDI_LINK_TRAIN_PATTERN_1 (0<<28)<br> #define FDI_LINK_TRAIN_PATTERN_2 (1<<28)<br> #define FDI_LINK_TRAIN_PATTERN_IDLE (2<<28)<br>@@ -3647,7 +3647,7 @@<br> #define _FDI_RXA_CTL 0xf000c<br> #define _FDI_RXB_CTL 0xf100c<br> #define FDI_RX_CTL(pipe) _PIPE(pipe, _FDI_RXA_CTL, _FDI_RXB_CTL)<br>-#define FDI_RX_ENABLE (1<<31)<br>+#define FDI_RX_ENABLE (1UL<<31)<br> /* train, dp width same as FDI_TX */<br> #define FDI_FS_ERRC_ENABLE (1<<27)<br> #define FDI_FE_ERRC_ENABLE (1<<26)<br>@@ -3720,7 +3720,7 @@<br> <br> /* or SDVOB */<br> #define HDMIB 0xe1140<br>-#define PORT_ENABLE (1 << 31)<br>+#define PORT_ENABLE (1UL << 31)<br> #define TRANSCODER(pipe) ((pipe) << 30)<br> #define TRANSCODER_CPT(pipe) ((pipe) << 29)<br> #define TRANSCODER_MASK (1 << 30)<br>@@ -3749,7 +3749,7 @@<br> #define PCH_LVDS 0xe1180<br> #define LVDS_DETECTED (1 << 1)<br> #define LVDS_BORDER_ENABLE (1 << 15)<br>-#define LVDS_PORT_ENABLE (1 << 31)<br>+#define LVDS_PORT_ENABLE (1UL << 31)<br> #define LVDS_CLOCK_A_POWERUP_ALL (3 << 8)<br> #define LVDS_CLOCK_B_POWERUP_ALL (3 << 4)<br> #define LVDS_CLOCK_BOTH_POWERUP_ALL (3 << 2)<br>@@ -3842,7 +3842,7 @@<br> #define TRANS_DP_CTL_B 0xe1300<br> #define TRANS_DP_CTL_C 0xe2300<br> #define TRANS_DP_CTL(pipe) _PIPE(pipe, TRANS_DP_CTL_A, TRANS_DP_CTL_B)<br>-#define TRANS_DP_OUTPUT_ENABLE (1<<31)<br>+#define TRANS_DP_OUTPUT_ENABLE (1UL<<31)<br> #define TRANS_DP_PORT_SEL_B (0<<29)<br> #define TRANS_DP_PORT_SEL_C (1<<29)<br> #define TRANS_DP_PORT_SEL_D (2<<29)<br>@@ -3929,7 +3929,7 @@<br> #define GEN7_L3BANK2X_CLOCK_GATE_DISABLE (1<<25)<br> <br> #define GEN6_RPNSWREQ 0xA008<br>-#define GEN6_TURBO_DISABLE (1<<31)<br>+#define GEN6_TURBO_DISABLE (1UL<<31)<br> #define GEN6_FREQUENCY(x) ((x)<<25)<br> #define GEN6_OFFSET(x) ((x)<<19)<br> #define GEN6_AGGRESSIVE_TURBO (0<<15)<br>@@ -3941,7 +3941,7 @@<br> #define GEN6_RC_CTL_RC1e_ENABLE (1<<20)<br> #define GEN6_RC_CTL_RC7_ENABLE (1<<22)<br> #define GEN6_RC_CTL_EI_MODE(x) ((x)<<27)<br>-#define GEN6_RC_CTL_HW_ENABLE (1<<31)<br>+#define GEN6_RC_CTL_HW_ENABLE (1UL<<31)<br> #define GEN6_RP_DOWN_TIMEOUT 0xA010<br> #define GEN6_RP_INTERRUPT_LIMITS 0xA014<br> #define GEN6_RPSTAT1 0xA01C<br>@@ -4009,7 +4009,7 @@<br> #define GEN6_GT_GFX_RC6pp 0x138110<br> <br> #define GEN6_PCODE_MAILBOX 0x138124<br>-#define GEN6_PCODE_READY (1<<31)<br>+#define GEN6_PCODE_READY (1UL<<31)<br> #define GEN6_READ_OC_PARAMS 0xc<br> #define GEN6_PCODE_WRITE_MIN_FREQ_TABLE 0x8<br> #define GEN6_PCODE_READ_MIN_FREQ_TABLE 0x9<br>@@ -4180,7 +4180,7 @@<br> #define HSW_PWR_WELL_ENABLE (1UL<<31)<br> #define HSW_PWR_WELL_STATE (1<<30)<br> #define HSW_PWR_WELL_CTL5 0x45410<br>-#define HSW_PWR_WELL_ENABLE_SINGLE_STEP (1<<31)<br>+#define HSW_PWR_WELL_ENABLE_SINGLE_STEP (1UL<<31)<br> #define HSW_PWR_WELL_PWR_GATE_OVERRIDE (1<<20)<br> #define HSW_PWR_WELL_FORCE_ON (1<<19)<br> #define HSW_PWR_WELL_CTL6 0x45414<br>@@ -4192,7 +4192,7 @@<br> #define TRANS_DDI_FUNC_CTL_EDP 0x6F400<br> #define TRANS_DDI_FUNC_CTL(tran) _TRANSCODER(tran, TRANS_DDI_FUNC_CTL_A, \<br> TRANS_DDI_FUNC_CTL_B)<br>-#define TRANS_DDI_FUNC_ENABLE (1<<31)<br>+#define TRANS_DDI_FUNC_ENABLE (1UL<<31)<br> /* Those bits are ignored by pipe EDP since it can only connect to DDI A */<br> #define TRANS_DDI_PORT_MASK (7<<28)<br> #define TRANS_DDI_SELECT_PORT(x) ((x)<<28)<br>@@ -4224,7 +4224,7 @@<br> #define DP_TP_CTL_A 0x64040<br> #define DP_TP_CTL_B 0x64140<br> #define DP_TP_CTL(port) _PORT(port, DP_TP_CTL_A, DP_TP_CTL_B)<br>-#define DP_TP_CTL_ENABLE (1<<31)<br>+#define DP_TP_CTL_ENABLE (1UL<<31)<br> #define DP_TP_CTL_MODE_SST (0<<27)<br> #define DP_TP_CTL_MODE_MST (1<<27)<br> #define DP_TP_CTL_ENHANCED_FRAME_ENABLE (1<<18)<br>@@ -4248,7 +4248,7 @@<br> #define DDI_BUF_CTL_A 0x64000<br> #define DDI_BUF_CTL_B 0x64100<br> #define DDI_BUF_CTL(port) _PORT(port, DDI_BUF_CTL_A, DDI_BUF_CTL_B)<br>-#define DDI_BUF_CTL_ENABLE (1<<31)<br>+#define DDI_BUF_CTL_ENABLE (1UL<<31)<br> #define DDI_BUF_EMP_400MV_0DB_HSW (0<<24) /* Sel0 */<br> #define DDI_BUF_EMP_400MV_3_5DB_HSW (1<<24) /* Sel1 */<br> #define DDI_BUF_EMP_400MV_6DB_HSW (2<<24) /* Sel2 */<br>@@ -4313,7 +4313,7 @@<br> <br> /* SPLL */<br> #define SPLL_CTL 0x46020<br>-#define SPLL_PLL_ENABLE (1<<31)<br>+#define SPLL_PLL_ENABLE (1UL<<31)<br> #define SPLL_PLL_SSC (1<<28)<br> #define SPLL_PLL_NON_SSC (2<<28)<br> #define SPLL_PLL_FREQ_810MHz (0<<26)<br>@@ -4322,7 +4322,7 @@<br> /* WRPLL */<br> #define WRPLL_CTL1 0x46040<br> #define WRPLL_CTL2 0x46060<br>-#define WRPLL_PLL_ENABLE (1<<31)<br>+#define WRPLL_PLL_ENABLE (1UL<<31)<br> #define WRPLL_PLL_SELECT_SSC (0x01<<28)<br> #define WRPLL_PLL_SELECT_NON_SSC (0x02<<28)<br> #define WRPLL_PLL_SELECT_LCPLL_2700 (0x03<<28)<br>@@ -4364,7 +4364,7 @@<br> <br> /* LCPLL Control */<br> #define LCPLL_CTL 0x130040<br>-#define LCPLL_PLL_DISABLE (1<<31)<br>+#define LCPLL_PLL_DISABLE (1UL<<31)<br> #define LCPLL_PLL_LOCK (1<<30)<br> #define LCPLL_CLK_FREQ_MASK (3<<26)<br> #define LCPLL_CLK_FREQ_450 (0<<26)<br>diff --git a/src/drivers/intel/gma/intel_bios.h b/src/drivers/intel/gma/intel_bios.h<br>index 000d7d5..2e1211b 100644<br>--- a/src/drivers/intel/gma/intel_bios.h<br>+++ b/src/drivers/intel/gma/intel_bios.h<br>@@ -584,7 +584,7 @@<br> #define SWF11_DPMS_STANDBY (1<<0)<br> #define SWF11_DPMS_ON 0<br> <br>-#define SWF14_GFX_PFIT_EN (1<<31)<br>+#define SWF14_GFX_PFIT_EN (1UL<<31)<br> #define SWF14_TEXT_PFIT_EN (1<<30)<br> #define SWF14_LID_STATUS_CLOSED (1<<29) /* 0 here means open */<br> #define SWF14_POPUP_EN (1<<28)<br>diff --git a/src/drivers/intel/gma/opregion.h b/src/drivers/intel/gma/opregion.h<br>index 3f94380..eebea58 100644<br>--- a/src/drivers/intel/gma/opregion.h<br>+++ b/src/drivers/intel/gma/opregion.h<br>@@ -168,7 +168,7 @@<br> #define IGD_BACKLIGHT_BRIGHTNESS 0xff<br> #define IGD_INITIAL_BRIGHTNESS 0x64<br> <br>-#define IGD_FIELD_VALID (1 << 31)<br>+#define IGD_FIELD_VALID (1UL << 31)<br> #define IGD_WORD_FIELD_VALID (1 << 15)<br> #define IGD_PFIT_STRETCH 6<br> <br></pre><p>To view, visit <a href="https://review.coreboot.org/20466">change 20466</a>. To unsubscribe, visit <a href="https://review.coreboot.org/settings">settings</a>.</p><div itemscope itemtype="http://schema.org/EmailMessage"><div itemscope itemprop="action" itemtype="http://schema.org/ViewAction"><link itemprop="url" href="https://review.coreboot.org/20466"/><meta itemprop="name" content="View Change"/></div></div>
<div style="display:none"> Gerrit-Project: coreboot </div>
<div style="display:none"> Gerrit-Branch: master </div>
<div style="display:none"> Gerrit-MessageType: newchange </div>
<div style="display:none"> Gerrit-Change-Id: I5240a19647c8ad59f64925f3e1c199446a886d2d </div>
<div style="display:none"> Gerrit-Change-Number: 20466 </div>
<div style="display:none"> Gerrit-PatchSet: 1 </div>
<div style="display:none"> Gerrit-Owner: Ryan Salsamendi <rsalsamendi@hotmail.com> </div>