<p>Ryan Salsamendi has uploaded this change for <strong>review</strong>.</p><p><a href="https://review.coreboot.org/20464">View Change</a></p><pre style="font-family: monospace,monospace; white-space: pre-wrap;">southbridge/intel/lynxpoint: Fix undefined behavior<br><br>Fix undefined behavior found by clang's -Wshift-sign-overflow, find,<br>and source inspection. Left shifting an int where the right operand is<br>>= the width of the type is undefined. Add UL suffix since it's safe<br>for unsigned types.<br><br>Change-Id: I10db2566199200ceb3068721cfb35eadb2be1f68<br>Signed-off-by: Ryan Salsamendi <rsalsamendi@hotmail.com><br>---<br>M src/southbridge/intel/lynxpoint/finalize.c<br>M src/southbridge/intel/lynxpoint/lp_gpio.h<br>M src/southbridge/intel/lynxpoint/lpc.c<br>M src/southbridge/intel/lynxpoint/pch.h<br>M src/southbridge/intel/lynxpoint/pcie.c<br>M src/southbridge/intel/lynxpoint/sata.c<br>6 files changed, 11 insertions(+), 10 deletions(-)<br><br></pre><pre style="font-family: monospace,monospace; white-space: pre-wrap;">git pull ssh://review.coreboot.org:29418/coreboot refs/changes/64/20464/1</pre><pre style="font-family: monospace,monospace; white-space: pre-wrap;">diff --git a/src/southbridge/intel/lynxpoint/finalize.c b/src/southbridge/intel/lynxpoint/finalize.c<br>index 1ff38e9..79a0915 100644<br>--- a/src/southbridge/intel/lynxpoint/finalize.c<br>+++ b/src/southbridge/intel/lynxpoint/finalize.c<br>@@ -40,7 +40,7 @@<br> #endif<br> <br> /* TCLOCKDN: TC Lockdown */<br>- RCBA32_OR(0x0050, (1 << 31));<br>+ RCBA32_OR(0x0050, (1UL << 31));<br> <br> /* BIOS Interface Lockdown */<br> RCBA32_OR(0x3410, (1 << 0));<br>@@ -55,7 +55,7 @@<br> pci_or_config8(PCH_LPC_DEV, 0xa6, (1 << 1) | (1 << 2));<br> <br> /* PMSYNC */<br>- RCBA32_OR(PMSYNC_CONFIG, (1 << 31));<br>+ RCBA32_OR(PMSYNC_CONFIG, (1UL << 31));<br> <br> /* R/WO registers */<br> RCBA32(0x21a4) = RCBA32(0x21a4);<br>diff --git a/src/southbridge/intel/lynxpoint/lp_gpio.h b/src/southbridge/intel/lynxpoint/lp_gpio.h<br>index c35e770..64e9c31 100644<br>--- a/src/southbridge/intel/lynxpoint/lp_gpio.h<br>+++ b/src/southbridge/intel/lynxpoint/lp_gpio.h<br>@@ -51,9 +51,9 @@<br> #define GPI_LEVEL (1 << 30)<br> <br> #define GPO_LEVEL_SHIFT 31<br>-#define GPO_LEVEL_MASK (1 << GPO_LEVEL_SHIFT)<br>-#define GPO_LEVEL_LOW (0 << GPO_LEVEL_SHIFT)<br>-#define GPO_LEVEL_HIGH (1 << GPO_LEVEL_SHIFT)<br>+#define GPO_LEVEL_MASK (1UL << GPO_LEVEL_SHIFT)<br>+#define GPO_LEVEL_LOW (0UL << GPO_LEVEL_SHIFT)<br>+#define GPO_LEVEL_HIGH (1UL << GPO_LEVEL_SHIFT)<br> <br> /* conf1 */<br> <br>diff --git a/src/southbridge/intel/lynxpoint/lpc.c b/src/southbridge/intel/lynxpoint/lpc.c<br>index 37cd94b..b8ffeba 100644<br>--- a/src/southbridge/intel/lynxpoint/lpc.c<br>+++ b/src/southbridge/intel/lynxpoint/lpc.c<br>@@ -475,7 +475,7 @@<br> reg32 &= ~(1 << 29); // LPC Dynamic<br> else<br> reg32 |= (1 << 29); // LPC Dynamic<br>- reg32 |= (1 << 31); // LP LPC<br>+ reg32 |= (1UL << 31); // LP LPC<br> reg32 |= (1 << 30); // LP BLA<br> reg32 |= (1 << 28); // GPIO Dynamic<br> reg32 |= (1 << 27); // HPET Dynamic<br>diff --git a/src/southbridge/intel/lynxpoint/pch.h b/src/southbridge/intel/lynxpoint/pch.h<br>index d76faf7..655aef1 100644<br>--- a/src/southbridge/intel/lynxpoint/pch.h<br>+++ b/src/southbridge/intel/lynxpoint/pch.h<br>@@ -242,7 +242,7 @@<br> #define GEN_PMCON_2 0xa2<br> #define GEN_PMCON_3 0xa4<br> #define PMIR 0xac<br>-#define PMIR_CF9LOCK (1 << 31)<br>+#define PMIR_CF9LOCK (1UL << 31)<br> #define PMIR_CF9GR (1 << 20)<br> <br> /* GEN_PMCON_3 bits */<br>@@ -389,7 +389,7 @@<br> #define XHCI_USB3_PORTSC_WRC (1 << 19) /* Warm Reset Complete */<br> #define XHCI_USB3_PORTSC_LWS (1 << 16) /* Link Write Strobe */<br> #define XHCI_USB3_PORTSC_PED (1 << 1) /* Port Enabled/Disabled */<br>-#define XHCI_USB3_PORTSC_WPR (1 << 31) /* Warm Port Reset */<br>+#define XHCI_USB3_PORTSC_WPR (1UL << 31) /* Warm Port Reset */<br> #define XHCI_USB3_PORTSC_PLS (0xf << 5) /* Port Link State */<br> #define XHCI_PLSR_DISABLED (4 << 5) /* Port is disabled */<br> #define XHCI_PLSR_RXDETECT (5 << 5) /* Port is disconnected */<br>diff --git a/src/southbridge/intel/lynxpoint/pcie.c b/src/southbridge/intel/lynxpoint/pcie.c<br>index 3d01cd6..d58ef6d 100644<br>--- a/src/southbridge/intel/lynxpoint/pcie.c<br>+++ b/src/southbridge/intel/lynxpoint/pcie.c<br>@@ -188,6 +188,7 @@<br> for (i = 0; i < rpc.num_ports; i++) {<br> device_t dev;<br> int rp;<br>+ static const uint32_t highBit = (1UL << 31);<br> <br> dev = rpc.ports[i];<br> rp = root_port_number(dev);<br>@@ -214,7 +215,7 @@<br> }<br> <br> pci_update_config8(dev, 0xe2, ~(3 << 4), (3 << 4));<br>- pci_update_config32(dev, 0x420, ~(1 << 31), (1 << 31));<br>+ pci_update_config32(dev, 0x420, ~highBit, highBit);<br> <br> /* Per-Port CLKREQ# handling. */<br> if (is_lp && gpio_is_native(18 + rp - 1))<br>diff --git a/src/southbridge/intel/lynxpoint/sata.c b/src/southbridge/intel/lynxpoint/sata.c<br>index 31081d7..c45579b 100644<br>--- a/src/southbridge/intel/lynxpoint/sata.c<br>+++ b/src/southbridge/intel/lynxpoint/sata.c<br>@@ -134,7 +134,7 @@<br> reg32 |= 1 << 18; /* BWG step 10 */<br> reg32 |= 1 << 29; /* BWG step 11 */<br> if (pch_is_lp()) {<br>- reg32 &= ~((1 << 31) | (1 << 30));<br>+ reg32 &= ~((1UL << 31) | (1 << 30));<br> reg32 |= 1 << 23;<br> reg32 |= 1 << 24; /* Disable listen mode (hotplug) */<br> }<br></pre><p>To view, visit <a href="https://review.coreboot.org/20464">change 20464</a>. To unsubscribe, visit <a href="https://review.coreboot.org/settings">settings</a>.</p><div itemscope itemtype="http://schema.org/EmailMessage"><div itemscope itemprop="action" itemtype="http://schema.org/ViewAction"><link itemprop="url" href="https://review.coreboot.org/20464"/><meta itemprop="name" content="View Change"/></div></div>
<div style="display:none"> Gerrit-Project: coreboot </div>
<div style="display:none"> Gerrit-Branch: master </div>
<div style="display:none"> Gerrit-MessageType: newchange </div>
<div style="display:none"> Gerrit-Change-Id: I10db2566199200ceb3068721cfb35eadb2be1f68 </div>
<div style="display:none"> Gerrit-Change-Number: 20464 </div>
<div style="display:none"> Gerrit-PatchSet: 1 </div>
<div style="display:none"> Gerrit-Owner: Ryan Salsamendi <rsalsamendi@hotmail.com> </div>