<p>Ryan Salsamendi has uploaded this change for <strong>review</strong>.</p><p><a href="https://review.coreboot.org/20444">View Change</a></p><pre style="font-family: monospace,monospace; white-space: pre-wrap;">northbridge/intel/haswell: Fix undefined behavior.<br><br>Fix reports found by undefined behavior sanitizer. Left shifting an int<br>where the right operand is >= the width of the type is undefined. Add<br>UL suffix since it's safe for unsigned types.<br><br>Change-Id: If2d34e4f05494c17bf9b9dec113b8f6863214e56<br>Signed-off-by: Ryan Salsamendi <rsalsamendi@hotmail.com><br>---<br>M src/drivers/intel/gma/i915_reg.h<br>M src/northbridge/intel/haswell/gma.c<br>M src/northbridge/intel/haswell/northbridge.c<br>3 files changed, 12 insertions(+), 7 deletions(-)<br><br></pre><pre style="font-family: monospace,monospace; white-space: pre-wrap;">git pull ssh://review.coreboot.org:29418/coreboot refs/changes/44/20444/1</pre><pre style="font-family: monospace,monospace; white-space: pre-wrap;">diff --git a/src/drivers/intel/gma/i915_reg.h b/src/drivers/intel/gma/i915_reg.h<br>index dee6865..e88ecfb 100644<br>--- a/src/drivers/intel/gma/i915_reg.h<br>+++ b/src/drivers/intel/gma/i915_reg.h<br>@@ -2979,7 +2979,7 @@<br> /* Ironlake */<br> <br> #define CPU_VGACNTRL 0x41000<br>-#define CPU_VGA_DISABLE (1<<31)<br>+#define CPU_VGA_DISABLE (1UL<<31)<br> <br> #define DIGITAL_PORT_HOTPLUG_CNTRL 0x44030<br> #define DIGITAL_PORTA_HOTPLUG_ENABLE (1 << 4)<br>@@ -4177,7 +4177,7 @@<br> #define HSW_PWR_WELL_CTL2 0x45404 /* Driver */<br> #define HSW_PWR_WELL_CTL3 0x45408 /* KVMR */<br> #define HSW_PWR_WELL_CTL4 0x4540C /* Debug */<br>-#define HSW_PWR_WELL_ENABLE (1<<31)<br>+#define HSW_PWR_WELL_ENABLE (1UL<<31)<br> #define HSW_PWR_WELL_STATE (1<<30)<br> #define HSW_PWR_WELL_CTL5 0x45410<br> #define HSW_PWR_WELL_ENABLE_SINGLE_STEP (1<<31)<br>diff --git a/src/northbridge/intel/haswell/gma.c b/src/northbridge/intel/haswell/gma.c<br>index f22ff48..75f3b7a 100644<br>--- a/src/northbridge/intel/haswell/gma.c<br>+++ b/src/northbridge/intel/haswell/gma.c<br>@@ -252,13 +252,13 @@<br> gtt_write_regs(haswell_gt_setup);<br> <br> /* Wait for Mailbox Ready */<br>- gtt_poll(0x138124, (1 << 31), (0 << 31));<br>+ gtt_poll(0x138124, (1UL << 31), (0UL << 31));<br> /* Mailbox Data - RC6 VIDS */<br> gtt_write(0x138128, 0x00000000);<br> /* Mailbox Command */<br> gtt_write(0x138124, 0x80000004);<br> /* Wait for Mailbox Ready */<br>- gtt_poll(0x138124, (1 << 31), (0 << 31));<br>+ gtt_poll(0x138124, (1UL << 31), (0UL << 31));<br> <br> /* Enable PM Interrupts */<br> gtt_write(GEN6_PMIER, GEN6_PM_MBOX_EVENT | GEN6_PM_THERMAL_EVENT |<br>diff --git a/src/northbridge/intel/haswell/northbridge.c b/src/northbridge/intel/haswell/northbridge.c<br>index a8c8015..df3916b 100644<br>--- a/src/northbridge/intel/haswell/northbridge.c<br>+++ b/src/northbridge/intel/haswell/northbridge.c<br>@@ -36,6 +36,7 @@<br> static int get_pcie_bar(device_t dev, unsigned int index, u32 *base, u32 *len)<br> {<br> u32 pciexbar_reg;<br>+ u32 mask;<br> <br> *base = 0;<br> *len = 0;<br>@@ -47,15 +48,19 @@<br> <br> switch ((pciexbar_reg >> 1) & 3) {<br> case 0: // 256MB<br>- *base = pciexbar_reg & ((1 << 31)|(1 << 30)|(1 << 29)|(1 << 28));<br>+ mask = ((1UL << 31)|(1 << 30)|(1 << 29)|(1 << 28));<br>+ *base = pciexbar_reg & mask;<br> *len = 256 * 1024 * 1024;<br> return 1;<br> case 1: // 128M<br>- *base = pciexbar_reg & ((1 << 31)|(1 << 30)|(1 << 29)|(1 << 28)|(1 << 27));<br>+ mask = ((1UL << 31)|(1 << 30)|(1 << 29)|(1 << 28)|(1 << 27));<br>+ *base = pciexbar_reg & mask;<br> *len = 128 * 1024 * 1024;<br> return 1;<br> case 2: // 64M<br>- *base = pciexbar_reg & ((1 << 31)|(1 << 30)|(1 << 29)|(1 << 28)|(1 << 27)|(1 << 26));<br>+ mask = ((1UL << 31)|(1 << 30)|(1 << 29)|(1 << 28)|(1 << 27);<br>+ mask |= (1 << 26));<br>+ *base = pciexbar_reg & mask;<br> *len = 64 * 1024 * 1024;<br> return 1;<br> }<br></pre><p>To view, visit <a href="https://review.coreboot.org/20444">change 20444</a>. To unsubscribe, visit <a href="https://review.coreboot.org/settings">settings</a>.</p><div itemscope itemtype="http://schema.org/EmailMessage"><div itemscope itemprop="action" itemtype="http://schema.org/ViewAction"><link itemprop="url" href="https://review.coreboot.org/20444"/><meta itemprop="name" content="View Change"/></div></div>
<div style="display:none"> Gerrit-Project: coreboot </div>
<div style="display:none"> Gerrit-Branch: master </div>
<div style="display:none"> Gerrit-MessageType: newchange </div>
<div style="display:none"> Gerrit-Change-Id: If2d34e4f05494c17bf9b9dec113b8f6863214e56 </div>
<div style="display:none"> Gerrit-Change-Number: 20444 </div>
<div style="display:none"> Gerrit-PatchSet: 1 </div>
<div style="display:none"> Gerrit-Owner: Ryan Salsamendi <rsalsamendi@hotmail.com> </div>