<p>Shelley Chen has uploaded this change for <strong>review</strong>.</p><p><a href="https://review.coreboot.org/20418">View Change</a></p><pre style="font-family: monospace,monospace; white-space: pre-wrap;">Fizz: Set PL2 and PsysPL2 MSRs<br><br>BUG=b:7473486, b:35775024<br>BRANCH=None<br>TEST=On bootup make sure PL2 and PsysPL2 values set<br> properly (through debug output)<br><br>Change-Id: I847a8458382e7db1689b426f32ff2dcbc5a0899c<br>Signed-off-by: Shelley Chen <shchen@chromium.org><br>---<br>M src/mainboard/google/fizz/devicetree.cb<br>M src/mainboard/google/fizz/mainboard.c<br>M src/soc/intel/skylake/cpu.c<br>M src/soc/intel/skylake/include/soc/cpu.h<br>M src/soc/intel/skylake/include/soc/msr.h<br>5 files changed, 71 insertions(+), 6 deletions(-)<br><br></pre><pre style="font-family: monospace,monospace; white-space: pre-wrap;">git pull ssh://review.coreboot.org:29418/coreboot refs/changes/18/20418/1</pre><pre style="font-family: monospace,monospace; white-space: pre-wrap;">diff --git a/src/mainboard/google/fizz/devicetree.cb b/src/mainboard/google/fizz/devicetree.cb<br>index a493de5..d0bddba 100644<br>--- a/src/mainboard/google/fizz/devicetree.cb<br>+++ b/src/mainboard/google/fizz/devicetree.cb<br>@@ -210,7 +210,6 @@<br> }"<br> <br> register "speed_shift_enable" = "1"<br>- register "tdp_pl2_override" = "7"<br> register "tcc_offset" = "10" # TCC of 90C<br> <br> # Use default SD card detect GPIO configuration<br>diff --git a/src/mainboard/google/fizz/mainboard.c b/src/mainboard/google/fizz/mainboard.c<br>index a925f08..4eb12d4 100644<br>--- a/src/mainboard/google/fizz/mainboard.c<br>+++ b/src/mainboard/google/fizz/mainboard.c<br>@@ -17,6 +17,7 @@<br> #include <console/console.h><br> #include <device/device.h><br> #include <ec/ec.h><br>+#include <soc/cpu.h><br> #include <soc/pci_devs.h><br> #include <soc/nhlt.h><br> #include <vendorcode/google/chromeos/chromeos.h><br>@@ -24,6 +25,41 @@<br> static const char *oem_id = "GOOGLE";<br> static const char *oem_table_id = "FIZZ";<br> <br>+/*<br>+ * mainboard_get_pl2<br>+ *<br>+ * @return value Pl2 should be set to based on cpu id<br>+ *<br>+ * NOTE: This is purely based on cpu id, which only work for the<br>+ * current build because we have a different cpu id per sku. However,<br>+ * on the next build, we'll have distinct board ids per sku. We'll<br>+ * need to modify that at this point.<br>+ */<br>+u32 mainboard_get_pl2(void)<br>+{<br>+ struct cpuid_result cpuidr;<br>+<br>+ cpuidr = cpuid(1);<br>+ printk(BIOS_DEBUG, "CPU(1): 0x%x\n", cpuidr.eax);<br>+ if (cpuidr.eax == 0x806ea) {<br>+ /* i7 needs higher pl2 */<br>+ return 44;<br>+ }<br>+ return 29;<br>+}<br>+<br>+/*<br>+ * mainboard_get_psyspl2<br>+ *<br>+ * This is 90 Watts across all SKUs for Fizz<br>+ *<br>+ * @return value PsysPl2 should be set to<br>+ */<br>+u32 mainboard_get_psyspl2(void)<br>+{<br>+ return 90;<br>+}<br>+<br> static void mainboard_init(device_t dev)<br> {<br> mainboard_ec_init();<br>diff --git a/src/soc/intel/skylake/cpu.c b/src/soc/intel/skylake/cpu.c<br>index e3be738..825fd15 100644<br>--- a/src/soc/intel/skylake/cpu.c<br>+++ b/src/soc/intel/skylake/cpu.c<br>@@ -104,6 +104,19 @@<br> [0x11] = 128,<br> };<br> <br>+u32 __attribute__((weak)) mainboard_get_pl2(void)<br>+{<br>+ device_t dev = SA_DEV_ROOT;<br>+ config_t *conf = dev->chip_info;<br>+<br>+ return conf->tdp_pl2_override;<br>+}<br>+<br>+u32 __attribute__((weak)) mainboard_get_psyspl2(void)<br>+{<br>+ return 0;<br>+}<br>+<br> /*<br> * Configure processor power limits if possible<br> * This must be done AFTER set of BIOS_RESET_CPL<br>@@ -115,8 +128,8 @@<br> unsigned int power_unit;<br> unsigned int tdp, min_power, max_power, max_time, tdp_pl2;<br> u8 power_limit_1_val;<br>- device_t dev = SA_DEV_ROOT;<br>- config_t *conf = dev->chip_info;<br>+ u32 pl2_val;<br>+ u32 psyspl2_val;<br> <br> if (power_limit_1_time > ARRAY_SIZE(power_limit_time_sec_to_msr))<br> power_limit_1_time = 28;<br>@@ -159,10 +172,12 @@<br> limit.lo |= (power_limit_1_val & PKG_POWER_LIMIT_TIME_MASK) <<<br> PKG_POWER_LIMIT_TIME_SHIFT;<br> <br>- /* Set short term power limit to 1.25 * TDP */<br>+ /* Set short term power limit to 1.25 TDP if no config given */<br> limit.hi = 0;<br>- tdp_pl2 = (conf->tdp_pl2_override == 0) ?<br>- (tdp * 125) / 100 : (conf->tdp_pl2_override * power_unit);<br>+ pl2_val = mainboard_get_pl2();<br>+ tdp_pl2 = (pl2_val == 0) ?<br>+ (tdp * 125) / 100 : (pl2_val * power_unit);<br>+ printk(BIOS_DEBUG, "CPU PL2 = %u Watts\n", pl2_val);<br> limit.hi |= (tdp_pl2) & PKG_POWER_LIMIT_MASK;<br> limit.hi |= PKG_POWER_LIMIT_CLAMP;<br> limit.hi |= PKG_POWER_LIMIT_EN;<br>@@ -174,6 +189,18 @@<br> MCHBAR32(MCH_PKG_POWER_LIMIT_LO) = limit.lo & (~(PKG_POWER_LIMIT_EN));<br> MCHBAR32(MCH_PKG_POWER_LIMIT_HI) = limit.hi;<br> <br>+ /* Set PsysPl2 */<br>+ limit.lo = 0;<br>+ limit.hi = 0;<br>+ psyspl2_val = mainboard_get_psyspl2();<br>+ if (psyspl2_val) {<br>+ printk(BIOS_DEBUG, "CPU PsysPL2 = %u Watts\n", psyspl2_val);<br>+ limit.hi |= (psyspl2_val) & PKG_POWER_LIMIT_MASK;<br>+ limit.hi |= PKG_POWER_LIMIT_EN;<br>+<br>+ wrmsr(MSR_PLATFORM_POWER_LIMIT, limit);<br>+ }<br>+<br> /* Set DDR RAPL power limit by copying from MMIO to MSR */<br> msr.lo = MCHBAR32(MCH_DDR_POWER_LIMIT_LO);<br> msr.hi = MCHBAR32(MCH_DDR_POWER_LIMIT_HI);<br>diff --git a/src/soc/intel/skylake/include/soc/cpu.h b/src/soc/intel/skylake/include/soc/cpu.h<br>index 059367a..47d3e63 100644<br>--- a/src/soc/intel/skylake/include/soc/cpu.h<br>+++ b/src/soc/intel/skylake/include/soc/cpu.h<br>@@ -50,6 +50,8 @@<br> (IRTL_1024_NS >> 10))<br> <br> /* Configure power limits for turbo mode */<br>+u32 mainboard_get_pl2(void);<br>+u32 mainboard_get_psyspl2(void);<br> void set_power_limits(u8 power_limit_1_time);<br> <br> /* CPU identification */<br>diff --git a/src/soc/intel/skylake/include/soc/msr.h b/src/soc/intel/skylake/include/soc/msr.h<br>index bb4b8e7..ef4027a 100644<br>--- a/src/soc/intel/skylake/include/soc/msr.h<br>+++ b/src/soc/intel/skylake/include/soc/msr.h<br>@@ -41,5 +41,6 @@<br> #define MSR_VR_MISC_CONFIG2 0x636<br> #define MSR_PP0_POWER_LIMIT 0x638<br> #define MSR_PP1_POWER_LIMIT 0x640<br>+#define MSR_PLATFORM_POWER_LIMIT 0x65c<br> <br> #endif<br></pre><p>To view, visit <a href="https://review.coreboot.org/20418">change 20418</a>. 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<div style="display:none"> Gerrit-Project: coreboot </div>
<div style="display:none"> Gerrit-Branch: master </div>
<div style="display:none"> Gerrit-MessageType: newchange </div>
<div style="display:none"> Gerrit-Change-Id: I847a8458382e7db1689b426f32ff2dcbc5a0899c </div>
<div style="display:none"> Gerrit-Change-Number: 20418 </div>
<div style="display:none"> Gerrit-PatchSet: 1 </div>
<div style="display:none"> Gerrit-Owner: Shelley Chen <shchen@google.com> </div>