<p>Marshall Dawson has uploaded this change for <strong>review</strong>.</p><p><a href="https://review.coreboot.org/20401">View Change</a></p><pre style="font-family: monospace,monospace; white-space: pre-wrap;">soc/amd/stoneyridge: Remove unused SD controller<br><br>Remove the unused support code from the old multi-device hudson<br>SD controller. The binaryPI blob contains the correct steps<br>for setting up SD and the public BKDG doesn't completely document<br>the controller.<br><br>The sd.c file was using device IDs not associated with the Stoney<br>Ridge APU. The hudson_enable() code removed was also looking for<br>incorrect device IDs and the PM_MANUAL_RESET register doesn't<br>behave as the source indicates.<br><br>The SD default settings may be overridden. Future improvements<br>may include a few Kconfig options and a weak call to the mainboard<br>for overriding additional defaults.<br><br>BUG=chrome-os-partner:62580062<br><br>Change-Id: I7dbd70320740e8a05e6bf16af125d67012f20674<br>Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com><br>---<br>M src/soc/amd/stoneyridge/Makefile.inc<br>M src/soc/amd/stoneyridge/hudson.c<br>D src/soc/amd/stoneyridge/sd.c<br>3 files changed, 0 insertions(+), 92 deletions(-)<br><br></pre><pre style="font-family: monospace,monospace; white-space: pre-wrap;">git pull ssh://review.coreboot.org:29418/coreboot refs/changes/01/20401/1</pre><pre style="font-family: monospace,monospace; white-space: pre-wrap;">diff --git a/src/soc/amd/stoneyridge/Makefile.inc b/src/soc/amd/stoneyridge/Makefile.inc<br>index f80605a..55e2cb1 100644<br>--- a/src/soc/amd/stoneyridge/Makefile.inc<br>+++ b/src/soc/amd/stoneyridge/Makefile.inc<br>@@ -72,7 +72,6 @@<br> ramstage-y += northbridge.c<br> ramstage-y += reset.c<br> ramstage-y += sata.c<br>-ramstage-y += sd.c<br> ramstage-y += sm.c<br> ramstage-y += smbus.c<br> ramstage-y += ramtop.c<br>diff --git a/src/soc/amd/stoneyridge/hudson.c b/src/soc/amd/stoneyridge/hudson.c<br>index af1095c..0eee351 100644<br>--- a/src/soc/amd/stoneyridge/hudson.c<br>+++ b/src/soc/amd/stoneyridge/hudson.c<br>@@ -63,33 +63,6 @@<br> void hudson_enable(device_t dev)<br> {<br> printk(BIOS_DEBUG, "hudson_enable()\n");<br>- switch (dev->path.pci.devfn) {<br>- case (0x14 << 3) | 7: /* 0:14.7 SD */<br>- if (dev->enabled == 0) {<br>- // read the VENDEV ID<br>- device_t sd_dev = dev_find_slot(0, PCI_DEVFN(0x14, 7));<br>- u32 sd_device_id = pci_read_config32(sd_dev, 0) >> 16;<br>- /* turn off the SDHC controller in the PM reg */<br>- u8 reg8;<br>- if (sd_device_id == PCI_DEVICE_ID_AMD_HUDSON_SD) {<br>- reg8 = pm_read8(PM_HUD_SD_FLASH_CTRL);<br>- reg8 &= ~BIT(0);<br>- pm_write8(PM_HUD_SD_FLASH_CTRL, reg8);<br>- } else if (sd_device_id<br>- == PCI_DEVICE_ID_AMD_YANGTZE_SD) {<br>- reg8 = pm_read8(PM_YANG_SD_FLASH_CTRL);<br>- reg8 &= ~BIT(0);<br>- pm_write8(PM_YANG_SD_FLASH_CTRL, reg8);<br>- }<br>- /* remove device 0:14.7 from PCI space */<br>- reg8 = pm_read8(PM_MANUAL_RESET);<br>- reg8 &= ~BIT(6);<br>- pm_write8(PM_MANUAL_RESET, reg8);<br>- }<br>- break;<br>- default:<br>- break;<br>- }<br> }<br> <br> static void hudson_init_acpi_ports(void)<br>diff --git a/src/soc/amd/stoneyridge/sd.c b/src/soc/amd/stoneyridge/sd.c<br>deleted file mode 100644<br>index 7188aad..0000000<br>--- a/src/soc/amd/stoneyridge/sd.c<br>+++ /dev/null<br>@@ -1,64 +0,0 @@<br>-/*<br>- * This file is part of the coreboot project.<br>- *<br>- * Copyright (C) 2013 Sage Electronic Engineering, LLC<br>- *<br>- * This program is free software; you can redistribute it and/or modify<br>- * it under the terms of the GNU General Public License as published by<br>- * the Free Software Foundation; version 2 of the License.<br>- *<br>- * This program is distributed in the hope that it will be useful,<br>- * but WITHOUT ANY WARRANTY; without even the implied warranty of<br>- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the<br>- * GNU General Public License for more details.<br>- */<br>-<br>-#include <device/device.h><br>-#include <delay.h><br>-#include <device/pci.h><br>-#include <device/pci_ids.h><br>-#include <device/pci_ops.h><br>-#include <arch/io.h><br>-#include <soc/hudson.h><br>-<br>-static void sd_init(struct device *dev)<br>-{<br>- u32 stepping;<br>-<br>- stepping = pci_read_config32(dev_find_slot(0, PCI_DEVFN(0x18, 3)),<br>- 0xfc);<br>-<br>- struct soc_amd_stoneyridge_config *sd_chip =<br>- (struct soc_amd_stoneyridge_config *)(dev->chip_info);<br>-<br>- if (sd_chip->sd_mode == 3) { /* SD 3.0 mode */<br>- pci_write_config32(dev, 0xa4, 0x31fec8b2);<br>- pci_write_config32(dev, 0xa8, 0x00002503);<br>- pci_write_config32(dev, 0xb0, 0x02180c19);<br>- pci_write_config32(dev, 0xd0, 0x0000078b);<br>- } else { /* SD 2.0 mode */<br>- if ((stepping & 0x0000000f) == 0) { /* Stepping A0 */<br>- pci_write_config32(dev, 0xa4, 0x31de32b2);<br>- pci_write_config32(dev, 0xb0, 0x01180c19);<br>- pci_write_config32(dev, 0xd0, 0x0000058b);<br>- } else { /* Stepping >= A1 */<br>- pci_write_config32(dev, 0xa4, 0x31fe3fb2);<br>- pci_write_config32(dev, 0xb0, 0x01180c19);<br>- pci_write_config32(dev, 0xd0, 0x0000078b);<br>- }<br>- }<br>-}<br>-<br>-static struct device_operations sd_ops = {<br>- .read_resources = pci_dev_read_resources,<br>- .set_resources = pci_dev_set_resources,<br>- .enable_resources = pci_dev_enable_resources,<br>- .init = sd_init,<br>- .scan_bus = 0,<br>-};<br>-<br>-static const struct pci_driver sd_driver __pci_driver = {<br>- .ops = &sd_ops,<br>- .vendor = PCI_VENDOR_ID_AMD,<br>- .device = PCI_DEVICE_ID_AMD_YANGTZE_SD,<br>-};<br></pre><p>To view, visit <a href="https://review.coreboot.org/20401">change 20401</a>. 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<div style="display:none"> Gerrit-Project: coreboot </div>
<div style="display:none"> Gerrit-Branch: master </div>
<div style="display:none"> Gerrit-MessageType: newchange </div>
<div style="display:none"> Gerrit-Change-Id: I7dbd70320740e8a05e6bf16af125d67012f20674 </div>
<div style="display:none"> Gerrit-Change-Number: 20401 </div>
<div style="display:none"> Gerrit-PatchSet: 1 </div>
<div style="display:none"> Gerrit-Owner: Marshall Dawson <marshalldawson3rd@gmail.com> </div>