<p>HAOUAS Elyes has uploaded this change for <strong>review</strong>.</p><p><a href="https://review.coreboot.org/20398">View Change</a></p><pre style="font-family: monospace,monospace; white-space: pre-wrap;">northbridge: Add whitespace around '<<'<br><br>Change-Id: I0bf2653c08c4955bf95dcbec2d5a0c891339866b<br>Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr><br>---<br>M src/northbridge/amd/agesa/family10/northbridge.c<br>M src/northbridge/amd/agesa/family10/reset_test.h<br>M src/northbridge/amd/agesa/family12/amdfam12_conf.c<br>M src/northbridge/amd/agesa/family12/northbridge.c<br>M src/northbridge/amd/agesa/family14/amdfam14_conf.c<br>M src/northbridge/amd/agesa/family15/northbridge.c<br>M src/northbridge/amd/agesa/family15rl/northbridge.c<br>M src/northbridge/amd/agesa/family15tn/northbridge.c<br>M src/northbridge/amd/agesa/family16kb/northbridge.c<br>M src/northbridge/amd/amdfam10/amdfam10.h<br>M src/northbridge/amd/amdfam10/early_ht.c<br>M src/northbridge/amd/amdfam10/get_pci1234.c<br>M src/northbridge/amd/amdfam10/ht_config.c<br>M src/northbridge/amd/amdfam10/misc_control.c<br>M src/northbridge/amd/amdfam10/northbridge.c<br>M src/northbridge/amd/amdfam10/pci.c<br>M src/northbridge/amd/amdfam10/raminit_sysinfo_in_ram.c<br>M src/northbridge/amd/amdht/comlib.c<br>M src/northbridge/amd/amdht/h3finit.c<br>M src/northbridge/amd/amdht/h3ncmn.c<br>M src/northbridge/amd/amdk8/amdk8.h<br>M src/northbridge/amd/amdk8/coherent_ht.c<br>M src/northbridge/amd/amdk8/f.h<br>M src/northbridge/amd/amdk8/f_pci.c<br>M src/northbridge/amd/amdk8/incoherent_ht.c<br>M src/northbridge/amd/amdk8/misc_control.c<br>M src/northbridge/amd/amdk8/northbridge.c<br>M src/northbridge/amd/amdk8/pre_f.h<br>M src/northbridge/amd/amdk8/raminit.c<br>M src/northbridge/amd/amdk8/raminit_f.c<br>M src/northbridge/amd/amdk8/raminit_f_dqs.c<br>M src/northbridge/amd/amdmct/mct/mct_d.c<br>M src/northbridge/amd/amdmct/mct/mct_d_gcc.c<br>M src/northbridge/amd/amdmct/mct/mctdqs_d.c<br>M src/northbridge/amd/amdmct/mct/mctecc_d.c<br>M src/northbridge/amd/amdmct/mct/mctgr.c<br>M src/northbridge/amd/amdmct/mct/mcthdi.c<br>M src/northbridge/amd/amdmct/mct/mctmtr_d.c<br>M src/northbridge/amd/amdmct/mct/mctpro_d.c<br>M src/northbridge/amd/amdmct/mct/mctsrc.c<br>M src/northbridge/amd/amdmct/mct/mctsrc2p.c<br>M src/northbridge/amd/amdmct/mct/mcttmrl.c<br>M src/northbridge/amd/amdmct/mct_ddr3/mct_d.c<br>M src/northbridge/amd/amdmct/mct_ddr3/mct_d_gcc.c<br>M src/northbridge/amd/amdmct/mct_ddr3/mctcsi_d.c<br>M src/northbridge/amd/amdmct/mct_ddr3/mctdqs_d.c<br>M src/northbridge/amd/amdmct/mct_ddr3/mcthdi.c<br>M src/northbridge/amd/amdmct/mct_ddr3/mctmtr_d.c<br>M src/northbridge/amd/amdmct/mct_ddr3/mctsrc.c<br>M src/northbridge/amd/amdmct/mct_ddr3/mctsrc1p.c<br>M src/northbridge/amd/amdmct/mct_ddr3/mctsrc2p.c<br>M src/northbridge/amd/amdmct/mct_ddr3/mcttmrl.c<br>M src/northbridge/amd/amdmct/mct_ddr3/mctwl.c<br>M src/northbridge/amd/amdmct/mct_ddr3/mutilc_d.c<br>M src/northbridge/amd/lx/northbridge.c<br>M src/northbridge/amd/pi/00630F01/northbridge.c<br>M src/northbridge/amd/pi/00660F01/northbridge.c<br>M src/northbridge/amd/pi/00670F00/northbridge.c<br>M src/northbridge/amd/pi/00730F01/northbridge.c<br>M src/northbridge/intel/e7505/e7505.h<br>M src/northbridge/intel/e7505/raminit.c<br>M src/northbridge/intel/gm45/iommu.c<br>M src/northbridge/intel/gm45/pm.c<br>M src/northbridge/intel/gm45/raminit.c<br>M src/northbridge/intel/haswell/northbridge.c<br>M src/northbridge/intel/i3100/memory_initialized.c<br>M src/northbridge/intel/i3100/pciexp_porta.c<br>M src/northbridge/intel/i3100/pciexp_porta_ep80579.c<br>M src/northbridge/intel/i3100/raminit.c<br>M src/northbridge/intel/i3100/raminit_ep80579.c<br>M src/northbridge/intel/i82830/memory_initialized.c<br>M src/northbridge/intel/i945/gma.c<br>M src/northbridge/intel/i945/raminit.c<br>M src/northbridge/intel/pineview/raminit.c<br>M src/northbridge/intel/sandybridge/raminit_common.h<br>M src/northbridge/intel/x4x/raminit_ddr2.c<br>M src/northbridge/intel/x4x/x4x.h<br>77 files changed, 742 insertions(+), 742 deletions(-)<br><br></pre><pre style="font-family: monospace,monospace; white-space: pre-wrap;">git pull ssh://review.coreboot.org:29418/coreboot refs/changes/98/20398/1</pre><pre style="font-family: monospace,monospace; white-space: pre-wrap;">diff --git a/src/northbridge/amd/agesa/family10/northbridge.c b/src/northbridge/amd/agesa/family10/northbridge.c<br>index 6f7a053..15693b7 100644<br>--- a/src/northbridge/amd/agesa/family10/northbridge.c<br>+++ b/src/northbridge/amd/agesa/family10/northbridge.c<br>@@ -63,14 +63,14 @@<br> temp = pci_read_config32(dev, 0x44 + (nodeid << 3)); //[39:24] at [31:16]<br> d.mask = ((temp & 0xfff80000)>>(8+3)); // mask out DramMask [26:24] too<br> temp = pci_read_config32(dev, 0x144 + (nodeid <<3)) & 0xff; //[47:40] at [7:0]<br>- d.mask |= temp<<21;<br>+ d.mask |= temp << 21;<br> <br> temp = pci_read_config32(dev, 0x40 + (nodeid << 3)); //[39:24] at [31:16]<br> d.mask |= (temp & 1); // enable bit<br> <br> d.base = ((temp & 0xfff80000)>>(8+3)); // mask out DramBase [26:24) too<br> temp = pci_read_config32(dev, 0x140 + (nodeid <<3)) & 0xff; //[47:40] at [7:0]<br>- d.base |= temp<<21;<br>+ d.base |= temp << 21;<br> return d;<br> }<br> <br>@@ -82,12 +82,12 @@<br> if ((segbusn & 0xff)>(0xe0-1)) {// use next segn<br> u32 segn = (segbusn >> 8) & 0x0f;<br> segn++;<br>- segbusn = segn<<8;<br>+ segbusn = segn << 8;<br> }<br> if (segbusn>>8) {<br> u32 val;<br> val = pci_read_config32(dev, 0x160);<br>- val &= ~(0xf<<25);<br>+ val &= ~(0xf << 25);<br> val |= (segbusn & 0xf00)<<(25-8);<br> pci_write_config32(dev, 0x160, val);<br> }<br>@@ -135,9 +135,9 @@<br> index = (reg-0xc0)>>3;<br> <br> val = (nodeid & 0x3f); // 6 bits used<br>- sysconf.conf_io_addr[index] = val | ((io_max<<8) & 0xfffff000); //limit : with nodeid<br>+ sysconf.conf_io_addr[index] = val | ((io_max << 8) & 0xfffff000); //limit : with nodeid<br> val = 3 | ((linkn & 0x7)<<4); // 8 bits used<br>- sysconf.conf_io_addrx[index] = val | ((io_min<<8) & 0xfffff000); // base : with enable bit<br>+ sysconf.conf_io_addrx[index] = val | ((io_min << 8) & 0xfffff000); // base : with enable bit<br> <br> if (sysconf.io_addr_num<(index+1))<br> sysconf.io_addr_num = index+1;<br>@@ -166,11 +166,11 @@<br> u32 tempreg;<br> <br> /* io range allocation */<br>- tempreg = (nodeid&0xf) | ((nodeid & 0x30)<<(8-4)) | (linkn<<4) | ((io_max&0xf0)<<(12-4)); //limit<br>+ tempreg = (nodeid&0xf) | ((nodeid & 0x30)<<(8-4)) | (linkn << 4) | ((io_max&0xf0)<<(12-4)); //limit<br> for (i = 0; i < sysconf.nodes; i++)<br> pci_write_config32(__f1_dev[i], reg+4, tempreg);<br> <br>- tempreg = 3 /*| (3<<4)*/ | ((io_min&0xf0)<<(12-4)); //base :ISA and VGA ?<br>+ tempreg = 3 /*| (3 << 4)*/ | ((io_min&0xf0)<<(12-4)); //base :ISA and VGA ?<br> for (i = 0; i < sysconf.nodes; i++)<br> pci_write_config32(__f1_dev[i], reg, tempreg);<br> }<br>@@ -181,7 +181,7 @@<br> u32 tempreg;<br> <br> /* io range allocation */<br>- tempreg = (nodeid&0xf) | (linkn<<4) | (mmio_max&0xffffff00); //limit<br>+ tempreg = (nodeid&0xf) | (linkn << 4) | (mmio_max&0xffffff00); //limit<br> for (i = 0; i < nodes; i++)<br> pci_write_config32(__f1_dev[i], reg+4, tempreg);<br> tempreg = 3 | (nodeid & 0x30) | (mmio_min&0xffffff00);<br>@@ -267,7 +267,7 @@<br> {<br> u32 val;<br> <br>- val = 1 | (nodeid<<4) | (linkn<<12);<br>+ val = 1 | (nodeid << 4) | (linkn << 12);<br> /* it will routing (1)mmio 0xa0000:0xbffff (2) io 0x3b0:0x3bb,<br> 0x3c0:0x3df */<br> f1_write_config32(0xf4, val);<br>@@ -329,7 +329,7 @@<br> if (!reg) {<br> //because of Extend conf space, we will never run out of reg, but we need one index to differ them. so same node and same link can have multi range<br> u32 index = get_io_addr_index(nodeid, link);<br>- reg = 0x110+ (index<<24) + (4<<20); // index could be 0, 255<br>+ reg = 0x110+ (index << 24) + (4 << 20); // index could be 0, 255<br> }<br> <br> resource = new_resource(dev, IOINDEX(0x1000 + reg, link));<br>@@ -366,7 +366,7 @@<br> // but we need one index to differ them. so same node and<br> // same link can have multi range<br> u32 index = get_mmio_addr_index(nodeid, link);<br>- reg = 0x110+ (index<<24) + (6<<20); // index could be 0, 63<br>+ reg = 0x110+ (index << 24) + (6 << 20); // index could be 0, 63<br> <br> }<br> resource = new_resource(dev, IOINDEX(0x1000 + reg, link));<br>@@ -669,7 +669,7 @@<br> <br> hole = pci_read_config32(__f1_dev[i], 0xf0);<br> if (hole & 1) { // we find the hole<br>- mem_hole.hole_startk = (hole & (0xff<<24)) >> 10;<br>+ mem_hole.hole_startk = (hole & (0xff << 24)) >> 10;<br> mem_hole.node_id = i; // record the node No with hole<br> break; // only one hole<br> }<br>@@ -936,7 +936,7 @@<br> nb_cfg_54 = 0;<br> ApicIdCoreIdSize = (cpuid_ecx(0x80000008)>>12 & 0xf);<br> if (ApicIdCoreIdSize) {<br>- siblings = (1<<ApicIdCoreIdSize)-1;<br>+ siblings = (1 << ApicIdCoreIdSize)-1;<br> } else {<br> siblings = 3; //quad core<br> }<br>diff --git a/src/northbridge/amd/agesa/family10/reset_test.h b/src/northbridge/amd/agesa/family10/reset_test.h<br>index 48634ea..61de4d9 100644<br>--- a/src/northbridge/amd/agesa/family10/reset_test.h<br>+++ b/src/northbridge/amd/agesa/family10/reset_test.h<br>@@ -23,9 +23,9 @@<br> <br> #define NODE_ID 0x60<br> #define HT_INIT_CONTROL 0x6c<br>-#define HTIC_ColdR_Detect (1<<4)<br>-#define HTIC_BIOSR_Detect (1<<5)<br>-#define HTIC_INIT_Detect (1<<6)<br>+#define HTIC_ColdR_Detect (1 << 4)<br>+#define HTIC_BIOSR_Detect (1 << 5)<br>+#define HTIC_INIT_Detect (1 << 6)<br> <br> static inline u32 warm_reset_detect(u8 nodeid)<br> {<br>diff --git a/src/northbridge/amd/agesa/family12/amdfam12_conf.c b/src/northbridge/amd/agesa/family12/amdfam12_conf.c<br>index 46af104..4c5ef19 100644<br>--- a/src/northbridge/amd/agesa/family12/amdfam12_conf.c<br>+++ b/src/northbridge/amd/agesa/family12/amdfam12_conf.c<br>@@ -53,12 +53,12 @@<br> device_t dev;<br> <br> /* io range allocation */<br>- tempreg = (nodeid&0xf) | ((nodeid & 0x30)<<(8-4)) | (linkn<<4) | ((io_max&0xf0)<<(12-4)); //limit<br>+ tempreg = (nodeid&0xf) | ((nodeid & 0x30)<<(8-4)) | (linkn << 4) | ((io_max&0xf0)<<(12-4)); //limit<br> for (i = 0; i < nodes; i++) {<br> dev = NODE_PCI(i, 1);<br> pci_write_config32(dev, 0xC4 + ht_c_index * 8, tempreg);<br> }<br>- tempreg = 3 /*| (3<<4)*/ | ((io_min&0xf0)<<(12-4)); //base :ISA and VGA ?<br>+ tempreg = 3 /*| (3 << 4)*/ | ((io_min&0xf0)<<(12-4)); //base :ISA and VGA ?<br> for (i = 0; i < nodes; i++) {<br> dev = NODE_PCI(i, 1);<br> pci_write_config32(dev, 0xC0 + ht_c_index * 8, tempreg);<br>@@ -98,10 +98,10 @@<br> <br> u32 tempreg;<br> /* io range allocation */<br>- tempreg = (nodeid&0xf) | ((nodeid & 0x30)<<(8-4)) | (linkn<<4) | ((io_max&0xf0)<<(12-4)); //limit<br>+ tempreg = (nodeid&0xf) | ((nodeid & 0x30)<<(8-4)) | (linkn << 4) | ((io_max&0xf0)<<(12-4)); //limit<br> pci_write_config32(__f1_dev[0], reg+4, tempreg);<br> <br>- tempreg = 3 /*| (3<<4)*/ | ((io_min&0xf0)<<(12-4)); //base :ISA and VGA ?<br>+ tempreg = 3 /*| (3 << 4)*/ | ((io_min&0xf0)<<(12-4)); //base :ISA and VGA ?<br> pci_write_config32(__f1_dev[0], reg, tempreg);<br> }<br> <br>@@ -111,7 +111,7 @@<br> <br> u32 tempreg;<br> /* io range allocation */<br>- tempreg = (nodeid&0xf) | (linkn<<4) | (mmio_max&0xffffff00); //limit<br>+ tempreg = (nodeid&0xf) | (linkn << 4) | (mmio_max&0xffffff00); //limit<br> pci_write_config32(__f1_dev[0], reg+4, tempreg);<br> tempreg = 3 | (nodeid & 0x30) | (mmio_min&0xffffff00);<br> pci_write_config32(__f1_dev[0], reg, tempreg);<br>diff --git a/src/northbridge/amd/agesa/family12/northbridge.c b/src/northbridge/amd/agesa/family12/northbridge.c<br>index c931bf0..206ae47 100644<br>--- a/src/northbridge/amd/agesa/family12/northbridge.c<br>+++ b/src/northbridge/amd/agesa/family12/northbridge.c<br>@@ -108,7 +108,7 @@<br> u32 val;<br> <br> printk(BIOS_DEBUG, "\nFam12h - northbridge.c - %s - Start.\n",__func__);<br>- val = 1 | (nodeid<<4) | (linkn<<12);<br>+ val = 1 | (nodeid << 4) | (linkn << 12);<br> /* it will routing (1)mmio 0xa0000:0xbffff (2) io 0x3b0:0x3bb,<br> 0x3c0:0x3df */<br> f1_write_config32(0xf4, val);<br>@@ -162,7 +162,7 @@<br> if (!reg) {<br> //because of Extend conf space, we will never run out of reg, but we need one index to differ them. so same node and same link can have multi range<br> u32 index = get_io_addr_index(nodeid, link);<br>- reg = 0x110+ (index<<24) + (4<<20); // index could be 0, 255<br>+ reg = 0x110+ (index << 24) + (4 << 20); // index could be 0, 255<br> }<br> <br> resource = new_resource(dev, IOINDEX(0x1000 + reg, link));<br>@@ -198,7 +198,7 @@<br> // but we need one index to differ them. so same node and<br> // same link can have multi range<br> u32 index = get_mmio_addr_index(nodeid, link);<br>- reg = 0x110+ (index<<24) + (6<<20); // index could be 0, 63<br>+ reg = 0x110+ (index << 24) + (6 << 20); // index could be 0, 63<br> }<br> <br> resource = new_resource(dev, IOINDEX(0x1000 + reg, link));<br>@@ -280,7 +280,7 @@<br> if (d.mask & 1) {<br> hole = pci_read_config32(__f1_dev[0], 0xf0);<br> if (hole & 1) { // we find the hole<br>- mem_hole.hole_startk = (hole & (0xff<<24)) >> 10;<br>+ mem_hole.hole_startk = (hole & (0xff << 24)) >> 10;<br> mem_hole.node_id = 0; // record the node No with hole<br> }<br> }<br>diff --git a/src/northbridge/amd/agesa/family14/amdfam14_conf.c b/src/northbridge/amd/agesa/family14/amdfam14_conf.c<br>index 0e588ad..5de7a05 100644<br>--- a/src/northbridge/amd/agesa/family14/amdfam14_conf.c<br>+++ b/src/northbridge/amd/agesa/family14/amdfam14_conf.c<br>@@ -53,12 +53,12 @@<br> device_t dev;<br> <br> /* io range allocation */<br>- tempreg = (nodeid&0xf) | ((nodeid & 0x30)<<(8-4)) | (linkn<<4) | ((io_max&0xf0)<<(12-4)); //limit<br>+ tempreg = (nodeid&0xf) | ((nodeid & 0x30)<<(8-4)) | (linkn << 4) | ((io_max&0xf0)<<(12-4)); //limit<br> for (i = 0; i < nodes; i++) {<br> dev = NODE_PCI(i, 1);<br> pci_write_config32(dev, 0xC4 + ht_c_index * 8, tempreg);<br> }<br>- tempreg = 3 /*| (3<<4)*/ | ((io_min&0xf0)<<(12-4)); //base :ISA and VGA ?<br>+ tempreg = 3 /*| (3 << 4)*/ | ((io_min&0xf0)<<(12-4)); //base :ISA and VGA ?<br> for (i = 0; i < nodes; i++) {<br> dev = NODE_PCI(i, 1);<br> pci_write_config32(dev, 0xC0 + ht_c_index * 8, tempreg);<br>@@ -98,10 +98,10 @@<br> <br> u32 tempreg;<br> /* io range allocation */<br>- tempreg = (nodeid&0xf) | ((nodeid & 0x30)<<(8-4)) | (linkn<<4) | ((io_max&0xf0)<<(12-4)); //limit<br>+ tempreg = (nodeid&0xf) | ((nodeid & 0x30)<<(8-4)) | (linkn << 4) | ((io_max&0xf0)<<(12-4)); //limit<br> pci_write_config32(__f1_dev[0], reg+4, tempreg);<br> <br>- tempreg = 3 /*| (3<<4)*/ | ((io_min&0xf0)<<(12-4)); //base :ISA and VGA ?<br>+ tempreg = 3 /*| (3 << 4)*/ | ((io_min&0xf0)<<(12-4)); //base :ISA and VGA ?<br> pci_write_config32(__f1_dev[0], reg, tempreg);<br> }<br> <br>@@ -111,7 +111,7 @@<br> <br> u32 tempreg;<br> /* io range allocation */<br>- tempreg = (nodeid&0xf) | (linkn<<4) | (mmio_max&0xffffff00); //limit<br>+ tempreg = (nodeid&0xf) | (linkn << 4) | (mmio_max&0xffffff00); //limit<br> pci_write_config32(__f1_dev[0], reg+4, tempreg);<br> tempreg = 3 | (nodeid & 0x30) | (mmio_min&0xffffff00);<br> pci_write_config32(__f1_dev[0], reg, tempreg);<br>diff --git a/src/northbridge/amd/agesa/family15/northbridge.c b/src/northbridge/amd/agesa/family15/northbridge.c<br>index 5cb0f91..15af024 100644<br>--- a/src/northbridge/amd/agesa/family15/northbridge.c<br>+++ b/src/northbridge/amd/agesa/family15/northbridge.c<br>@@ -67,12 +67,12 @@<br> temp = pci_read_config32(dev, 0x44 + (nodeid << 3)); //[39:24] at [31:16]<br> d.mask = ((temp & 0xfff80000)>>(8+3)); // mask out DramMask [26:24] too<br> temp = pci_read_config32(dev, 0x144 + (nodeid <<3)) & 0xff; //[47:40] at [7:0]<br>- d.mask |= temp<<21;<br>+ d.mask |= temp << 21;<br> temp = pci_read_config32(dev, 0x40 + (nodeid << 3)); //[39:24] at [31:16]<br> d.mask |= (temp & 1); // enable bit<br> d.base = ((temp & 0xfff80000)>>(8+3)); // mask out DramBase [26:24) too<br> temp = pci_read_config32(dev, 0x140 + (nodeid <<3)) & 0xff; //[47:40] at [7:0]<br>- d.base |= temp<<21;<br>+ d.base |= temp << 21;<br> return d;<br> }<br> <br>@@ -82,10 +82,10 @@<br> u32 i;<br> u32 tempreg;<br> /* io range allocation */<br>- tempreg = (nodeid&0xf) | ((nodeid & 0x30)<<(8-4)) | (linkn<<4) | ((io_max&0xf0)<<(12-4)); //limit<br>+ tempreg = (nodeid&0xf) | ((nodeid & 0x30)<<(8-4)) | (linkn << 4) | ((io_max&0xf0)<<(12-4)); //limit<br> for (i = 0; i < node_nums; i++)<br> pci_write_config32(__f1_dev[i], reg+4, tempreg);<br>- tempreg = 3 /*| (3<<4)*/ | ((io_min&0xf0)<<(12-4)); //base :ISA and VGA ?<br>+ tempreg = 3 /*| (3 << 4)*/ | ((io_min&0xf0)<<(12-4)); //base :ISA and VGA ?<br> for (i = 0; i < node_nums; i++)<br> pci_write_config32(__f1_dev[i], reg, tempreg);<br> }<br>@@ -95,7 +95,7 @@<br> u32 i;<br> u32 tempreg;<br> /* io range allocation */<br>- tempreg = (nodeid&0xf) | (linkn<<4) | (mmio_max&0xffffff00); //limit<br>+ tempreg = (nodeid&0xf) | (linkn << 4) | (mmio_max&0xffffff00); //limit<br> for (i = 0; i < nodes; i++)<br> pci_write_config32(__f1_dev[i], reg+4, tempreg);<br> tempreg = 3 | (nodeid & 0x30) | (mmio_min&0xffffff00);<br>@@ -174,7 +174,7 @@<br> {<br> u32 val;<br> <br>- val = 1 | (nodeid<<4) | (linkn<<12);<br>+ val = 1 | (nodeid << 4) | (linkn << 12);<br> /* it will routing<br> * (1)mmio 0xa0000:0xbffff<br> * (2)io 0x3b0:0x3bb, 0x3c0:0x3df<br>@@ -668,7 +668,7 @@<br> if (!(d.mask & 1)) continue; // no memory on this node<br> hole = pci_read_config32(__f1_dev[i], 0xf0);<br> if (hole & 1) { // we find the hole<br>- mem_hole.hole_startk = (hole & (0xff<<24)) >> 10;<br>+ mem_hole.hole_startk = (hole & (0xff << 24)) >> 10;<br> mem_hole.node_id = i; // record the node No with hole<br> break; // only one hole<br> }<br>diff --git a/src/northbridge/amd/agesa/family15rl/northbridge.c b/src/northbridge/amd/agesa/family15rl/northbridge.c<br>index aa24a6a..8cb801b 100644<br>--- a/src/northbridge/amd/agesa/family15rl/northbridge.c<br>+++ b/src/northbridge/amd/agesa/family15rl/northbridge.c<br>@@ -66,12 +66,12 @@<br> temp = pci_read_config32(dev, 0x44 + (nodeid << 3)); //[39:24] at [31:16]<br> d.mask = ((temp & 0xfff80000)>>(8+3)); // mask out DramMask [26:24] too<br> temp = pci_read_config32(dev, 0x144 + (nodeid <<3)) & 0xff; //[47:40] at [7:0]<br>- d.mask |= temp<<21;<br>+ d.mask |= temp << 21;<br> temp = pci_read_config32(dev, 0x40 + (nodeid << 3)); //[39:24] at [31:16]<br> d.mask |= (temp & 1); // enable bit<br> d.base = ((temp & 0xfff80000)>>(8+3)); // mask out DramBase [26:24) too<br> temp = pci_read_config32(dev, 0x140 + (nodeid <<3)) & 0xff; //[47:40] at [7:0]<br>- d.base |= temp<<21;<br>+ d.base |= temp << 21;<br> return d;<br> }<br> <br>@@ -81,10 +81,10 @@<br> u32 i;<br> u32 tempreg;<br> /* io range allocation */<br>- tempreg = (nodeid&0xf) | ((nodeid & 0x30)<<(8-4)) | (linkn<<4) | ((io_max&0xf0)<<(12-4)); //limit<br>+ tempreg = (nodeid&0xf) | ((nodeid & 0x30)<<(8-4)) | (linkn << 4) | ((io_max&0xf0)<<(12-4)); //limit<br> for (i = 0; i < node_nums; i++)<br> pci_write_config32(__f1_dev[i], reg+4, tempreg);<br>- tempreg = 3 /*| (3<<4)*/ | ((io_min&0xf0)<<(12-4)); //base :ISA and VGA ?<br>+ tempreg = 3 /*| (3 << 4)*/ | ((io_min&0xf0)<<(12-4)); //base :ISA and VGA ?<br> for (i = 0; i < node_nums; i++)<br> pci_write_config32(__f1_dev[i], reg, tempreg);<br> }<br>@@ -94,7 +94,7 @@<br> u32 i;<br> u32 tempreg;<br> /* io range allocation */<br>- tempreg = (nodeid&0xf) | (linkn<<4) | (mmio_max&0xffffff00); //limit<br>+ tempreg = (nodeid&0xf) | (linkn << 4) | (mmio_max&0xffffff00); //limit<br> for (i = 0; i < nodes; i++)<br> pci_write_config32(__f1_dev[i], reg+4, tempreg);<br> tempreg = 3 | (nodeid & 0x30) | (mmio_min&0xffffff00);<br>@@ -173,7 +173,7 @@<br> {<br> u32 val;<br> <br>- val = 1 | (nodeid<<4) | (linkn<<12);<br>+ val = 1 | (nodeid << 4) | (linkn << 12);<br> /* it will routing<br> * (1)mmio 0xa0000:0xbffff<br> * (2)io 0x3b0:0x3bb, 0x3c0:0x3df<br>@@ -664,7 +664,7 @@<br> if (!(d.mask & 1)) continue; // no memory on this node<br> hole = pci_read_config32(__f1_dev[i], 0xf0);<br> if (hole & 1) { // we find the hole<br>- mem_hole.hole_startk = (hole & (0xff<<24)) >> 10;<br>+ mem_hole.hole_startk = (hole & (0xff << 24)) >> 10;<br> mem_hole.node_id = i; // record the node No with hole<br> break; // only one hole<br> }<br>diff --git a/src/northbridge/amd/agesa/family15tn/northbridge.c b/src/northbridge/amd/agesa/family15tn/northbridge.c<br>index 95787fc..66da338 100644<br>--- a/src/northbridge/amd/agesa/family15tn/northbridge.c<br>+++ b/src/northbridge/amd/agesa/family15tn/northbridge.c<br>@@ -65,12 +65,12 @@<br> temp = pci_read_config32(dev, 0x44 + (nodeid << 3)); //[39:24] at [31:16]<br> d.mask = ((temp & 0xfff80000)>>(8+3)); // mask out DramMask [26:24] too<br> temp = pci_read_config32(dev, 0x144 + (nodeid <<3)) & 0xff; //[47:40] at [7:0]<br>- d.mask |= temp<<21;<br>+ d.mask |= temp << 21;<br> temp = pci_read_config32(dev, 0x40 + (nodeid << 3)); //[39:24] at [31:16]<br> d.mask |= (temp & 1); // enable bit<br> d.base = ((temp & 0xfff80000)>>(8+3)); // mask out DramBase [26:24) too<br> temp = pci_read_config32(dev, 0x140 + (nodeid <<3)) & 0xff; //[47:40] at [7:0]<br>- d.base |= temp<<21;<br>+ d.base |= temp << 21;<br> return d;<br> }<br> <br>@@ -80,10 +80,10 @@<br> u32 i;<br> u32 tempreg;<br> /* io range allocation */<br>- tempreg = (nodeid&0xf) | ((nodeid & 0x30)<<(8-4)) | (linkn<<4) | ((io_max&0xf0)<<(12-4)); //limit<br>+ tempreg = (nodeid&0xf) | ((nodeid & 0x30)<<(8-4)) | (linkn << 4) | ((io_max&0xf0)<<(12-4)); //limit<br> for (i = 0; i < node_nums; i++)<br> pci_write_config32(__f1_dev[i], reg+4, tempreg);<br>- tempreg = 3 /*| (3<<4)*/ | ((io_min&0xf0)<<(12-4)); //base :ISA and VGA ?<br>+ tempreg = 3 /*| (3 << 4)*/ | ((io_min&0xf0)<<(12-4)); //base :ISA and VGA ?<br> for (i = 0; i < node_nums; i++)<br> pci_write_config32(__f1_dev[i], reg, tempreg);<br> }<br>@@ -93,7 +93,7 @@<br> u32 i;<br> u32 tempreg;<br> /* io range allocation */<br>- tempreg = (nodeid&0xf) | (linkn<<4) | (mmio_max&0xffffff00); //limit<br>+ tempreg = (nodeid&0xf) | (linkn << 4) | (mmio_max&0xffffff00); //limit<br> for (i = 0; i < nodes; i++)<br> pci_write_config32(__f1_dev[i], reg+4, tempreg);<br> tempreg = 3 | (nodeid & 0x30) | (mmio_min&0xffffff00);<br>@@ -172,7 +172,7 @@<br> {<br> u32 val;<br> <br>- val = 1 | (nodeid<<4) | (linkn<<12);<br>+ val = 1 | (nodeid << 4) | (linkn << 12);<br> /* it will routing<br> * (1)mmio 0xa0000:0xbffff<br> * (2)io 0x3b0:0x3bb, 0x3c0:0x3df<br>@@ -663,7 +663,7 @@<br> if (!(d.mask & 1)) continue; // no memory on this node<br> hole = pci_read_config32(__f1_dev[i], 0xf0);<br> if (hole & 1) { // we find the hole<br>- mem_hole.hole_startk = (hole & (0xff<<24)) >> 10;<br>+ mem_hole.hole_startk = (hole & (0xff << 24)) >> 10;<br> mem_hole.node_id = i; // record the node No with hole<br> break; // only one hole<br> }<br>diff --git a/src/northbridge/amd/agesa/family16kb/northbridge.c b/src/northbridge/amd/agesa/family16kb/northbridge.c<br>index f91448a..4545601 100644<br>--- a/src/northbridge/amd/agesa/family16kb/northbridge.c<br>+++ b/src/northbridge/amd/agesa/family16kb/northbridge.c<br>@@ -65,12 +65,12 @@<br> temp = pci_read_config32(dev, 0x44 + (nodeid << 3)); //[39:24] at [31:16]<br> d.mask = ((temp & 0xfff80000)>>(8+3)); // mask out DramMask [26:24] too<br> temp = pci_read_config32(dev, 0x144 + (nodeid <<3)) & 0xff; //[47:40] at [7:0]<br>- d.mask |= temp<<21;<br>+ d.mask |= temp << 21;<br> temp = pci_read_config32(dev, 0x40 + (nodeid << 3)); //[39:24] at [31:16]<br> d.mask |= (temp & 1); // enable bit<br> d.base = ((temp & 0xfff80000)>>(8+3)); // mask out DramBase [26:24) too<br> temp = pci_read_config32(dev, 0x140 + (nodeid <<3)) & 0xff; //[47:40] at [7:0]<br>- d.base |= temp<<21;<br>+ d.base |= temp << 21;<br> return d;<br> }<br> <br>@@ -80,10 +80,10 @@<br> u32 i;<br> u32 tempreg;<br> /* io range allocation */<br>- tempreg = (nodeid&0xf) | ((nodeid & 0x30)<<(8-4)) | (linkn<<4) | ((io_max&0xf0)<<(12-4)); //limit<br>+ tempreg = (nodeid&0xf) | ((nodeid & 0x30)<<(8-4)) | (linkn << 4) | ((io_max&0xf0)<<(12-4)); //limit<br> for (i = 0; i < node_nums; i++)<br> pci_write_config32(__f1_dev[i], reg+4, tempreg);<br>- tempreg = 3 /*| (3<<4)*/ | ((io_min&0xf0)<<(12-4)); //base :ISA and VGA ?<br>+ tempreg = 3 /*| (3 << 4)*/ | ((io_min&0xf0)<<(12-4)); //base :ISA and VGA ?<br> for (i = 0; i < node_nums; i++)<br> pci_write_config32(__f1_dev[i], reg, tempreg);<br> }<br>@@ -93,7 +93,7 @@<br> u32 i;<br> u32 tempreg;<br> /* io range allocation */<br>- tempreg = (nodeid&0xf) | (linkn<<4) | (mmio_max&0xffffff00); //limit<br>+ tempreg = (nodeid&0xf) | (linkn << 4) | (mmio_max&0xffffff00); //limit<br> for (i = 0; i < nodes; i++)<br> pci_write_config32(__f1_dev[i], reg+4, tempreg);<br> tempreg = 3 | (nodeid & 0x30) | (mmio_min&0xffffff00);<br>@@ -172,7 +172,7 @@<br> {<br> u32 val;<br> <br>- val = 1 | (nodeid<<4) | (linkn<<12);<br>+ val = 1 | (nodeid << 4) | (linkn << 12);<br> /* it will routing<br> * (1)mmio 0xa0000:0xbffff<br> * (2)io 0x3b0:0x3bb, 0x3c0:0x3df<br>@@ -678,7 +678,7 @@<br> if (!(d.mask & 1)) continue; // no memory on this node<br> hole = pci_read_config32(__f1_dev[i], 0xf0);<br> if (hole & 2) { // we find the hole<br>- mem_hole.hole_startk = (hole & (0xff<<24)) >> 10;<br>+ mem_hole.hole_startk = (hole & (0xff << 24)) >> 10;<br> mem_hole.node_id = i; // record the node No with hole<br> break; // only one hole<br> }<br>diff --git a/src/northbridge/amd/amdfam10/amdfam10.h b/src/northbridge/amd/amdfam10/amdfam10.h<br>index 611291a..7882da6 100644<br>--- a/src/northbridge/amd/amdfam10/amdfam10.h<br>+++ b/src/northbridge/amd/amdfam10/amdfam10.h<br>@@ -33,9 +33,9 @@<br> <br> #define NODE_ID 0x60<br> #define HT_INIT_CONTROL 0x6c<br>-#define HTIC_ColdR_Detect (1<<4)<br>-#define HTIC_BIOSR_Detect (1<<5)<br>-#define HTIC_INIT_Detect (1<<6)<br>+#define HTIC_ColdR_Detect (1 << 4)<br>+#define HTIC_BIOSR_Detect (1 << 5)<br>+#define HTIC_INIT_Detect (1 << 6)<br> <br> /* Definitions of various FAM10 registers */<br> /* Function 0 */<br>@@ -95,8 +95,8 @@<br> #define DC_Twrwr3_2_MASK 3<br> #define DC_Trdrd3_2_SHIFT 12 /*DDR3 */<br> #define DC_Trdrd3_2_MASK 3<br>-#define DC_AltVidC3MemClkTriEn (1<<16)<br>-#define DC_DqsRcvEnTrain (1<<18)<br>+#define DC_AltVidC3MemClkTriEn (1 << 16)<br>+#define DC_DqsRcvEnTrain (1 << 18)<br> #define DC_MaxRdLatency_SHIFT 22<br> #define DC_MaxRdLatency_MASK 0x3ff<br> <br>@@ -107,14 +107,14 @@<br> #define DI_MrsBank_MASK 7<br> #define DI_MrsChipSel_SHIFT 20<br> #define DI_MrsChipSel_MASK 7<br>-#define DI_SendRchgAll (1<<24)<br>-#define DI_SendAutoRefresh (1<<25)<br>-#define DI_SendMrsCmd (1<<26)<br>-#define DI_DeassertMemRstX (1<<27)<br>-#define DI_AssertCke (1<<28)<br>-#define DI_SendZQCmd (1<<29) /*DDR3 */<br>-#define DI_EnMrsCmd (1<<30)<br>-#define DI_EnDramInit (1<<31)<br>+#define DI_SendRchgAll (1 << 24)<br>+#define DI_SendAutoRefresh (1 << 25)<br>+#define DI_SendMrsCmd (1 << 26)<br>+#define DI_DeassertMemRstX (1 << 27)<br>+#define DI_AssertCke (1 << 28)<br>+#define DI_SendZQCmd (1 << 29) /*DDR3 */<br>+#define DI_EnMrsCmd (1 << 30)<br>+#define DI_EnDramInit (1 << 31)<br> <br> #define DRAM_MRS 0x84<br> #define DM_BurstCtrl_SHIFT 0<br>@@ -130,15 +130,15 @@<br> #define DM_DramTerm_MASK 7<br> #define DM_DramTermDyn_SHIFT 10 /* DDR3 */<br> #define DM_DramTermDyn_MASK 3<br>-#define DM_Ooff (1<<13)<br>-#define DM_ASR (1<<18)<br>-#define DM_SRT (1<<19)<br>+#define DM_Ooff (1 << 13)<br>+#define DM_ASR (1 << 18)<br>+#define DM_SRT (1 << 19)<br> #define DM_Tcwl_SHIFT 20<br> #define DM_Tcwl_MASK 7<br>-#define DM_PchgPDModeSel (1<<23) /* DDR3 */<br>+#define DM_PchgPDModeSel (1 << 23) /* DDR3 */<br> #define DM_MPrLoc_SHIFT 24 /* DDR3 */<br> #define DM_MPrLoc_MASK 3<br>-#define DM_MprEn (1<<26) /* DDR3 */<br>+#define DM_MprEn (1 << 26) /* DDR3 */<br> <br> #define DRAM_TIMING_LOW 0x88<br> #define DTL_TCL_SHIFT 0<br>@@ -223,7 +223,7 @@<br> #define DTH_TREF_MASK 3<br> #define DTH_TREF_7_8_US 2<br> #define DTH_TREF_3_9_US 3<br>-#define DTH_DisAutoRefresh (1<<18)<br>+#define DTH_DisAutoRefresh (1 << 18)<br> #define DTH_TRFC0_SHIFT 20 /* for Logical DIMM0 */<br> #define DTH_TRFC_MASK 7<br> #define DTH_TRFC_75_256M 0<br>@@ -236,8 +236,8 @@<br> #define DTH_TRFC3_SHIFT 29 /*for Logical DIMM3 */<br> <br> #define DRAM_CONFIG_LOW 0x90<br>-#define DCL_InitDram (1<<0)<br>-#define DCL_ExitSelfRef (1<<1)<br>+#define DCL_InitDram (1 << 0)<br>+#define DCL_ExitSelfRef (1 << 1)<br> #define DCL_PllLockTime_SHIFT 2<br> #define DCL_PllLockTime_MASK 3<br> #define DCL_PllLockTime_15US 0<br>@@ -248,25 +248,25 @@<br> #define DCL_DramTerm_75_OH 1<br> #define DCL_DramTerm_150_OH 2<br> #define DCL_DramTerm_50_OH 3<br>-#define DCL_DisDqsBar (1<<6) /* only for DDR2 */<br>-#define DCL_DramDrvWeak (1<<7) /* only for DDR2 */<br>-#define DCL_ParEn (1<<8)<br>-#define DCL_SelfRefRateEn (1<<9) /* only for DDR2 */<br>-#define DCL_BurstLength32 (1<<10) /* only for DDR3 */<br>-#define DCL_Width128 (1<<11)<br>+#define DCL_DisDqsBar (1 << 6) /* only for DDR2 */<br>+#define DCL_DramDrvWeak (1 << 7) /* only for DDR2 */<br>+#define DCL_ParEn (1 << 8)<br>+#define DCL_SelfRefRateEn (1 << 9) /* only for DDR2 */<br>+#define DCL_BurstLength32 (1 << 10) /* only for DDR3 */<br>+#define DCL_Width128 (1 << 11)<br> #define DCL_X4Dimm_SHIFT 12<br> #define DCL_X4Dimm_MASK 0xf<br>-#define DCL_UnBuffDimm (1<<16)<br>-#define DCL_EnPhyDqsRcvEnTr (1<<18)<br>-#define DCL_DimmEccEn (1<<19)<br>-#define DCL_DynPageCloseEn (1<<20)<br>+#define DCL_UnBuffDimm (1 << 16)<br>+#define DCL_EnPhyDqsRcvEnTr (1 << 18)<br>+#define DCL_DimmEccEn (1 << 19)<br>+#define DCL_DynPageCloseEn (1 << 20)<br> #define DCL_IdleCycInit_SHIFT 21<br> #define DCL_IdleCycInit_MASK 3<br> #define DCL_IdleCycInit_16CLK 0<br> #define DCL_IdleCycInit_32CLK 1<br> #define DCL_IdleCycInit_64CLK 2<br> #define DCL_IdleCycInit_96CLK 3<br>-#define DCL_ForceAutoPchg (1<<23)<br>+#define DCL_ForceAutoPchg (1 << 23)<br> <br> #define DRAM_CONFIG_HIGH 0x94<br> #define DCH_MemClkFreq_SHIFT 0<br>@@ -278,27 +278,27 @@<br> #define DCH_MemClkFreq_533MHz 4 /* DDR 3 */<br> #define DCH_MemClkFreq_667MHz 5 /* DDR 3 */<br> #define DCH_MemClkFreq_800MHz 6 /* DDR 3 */<br>-#define DCH_MemClkFreqVal (1<<3)<br>-#define DCH_Ddr3Mode (1<<8)<br>-#define DCH_LegacyBiosMode (1<<9)<br>+#define DCH_MemClkFreqVal (1 << 3)<br>+#define DCH_Ddr3Mode (1 << 8)<br>+#define DCH_LegacyBiosMode (1 << 9)<br> #define DCH_ZqcsInterval_SHIFT 10<br> #define DCH_ZqcsInterval_MASK 3<br> #define DCH_ZqcsInterval_DIS 0<br> #define DCH_ZqcsInterval_64MS 1<br> #define DCH_ZqcsInterval_128MS 2<br> #define DCH_ZqcsInterval_256MS 3<br>-#define DCH_RDqsEn (1<<12) /* only for DDR2 */<br>-#define DCH_DisSimulRdWr (1<<13)<br>-#define DCH_DisDramInterface (1<<14)<br>-#define DCH_PowerDownEn (1<<15)<br>+#define DCH_RDqsEn (1 << 12) /* only for DDR2 */<br>+#define DCH_DisSimulRdWr (1 << 13)<br>+#define DCH_DisDramInterface (1 << 14)<br>+#define DCH_PowerDownEn (1 << 15)<br> #define DCH_PowerDownMode_SHIFT 16<br> #define DCH_PowerDownMode_MASK 1<br> #define DCH_PowerDownMode_Channel_CKE 0<br> #define DCH_PowerDownMode_ChipSelect_CKE 1<br>-#define DCH_FourRankSODimm (1<<17)<br>-#define DCH_FourRankRDimm (1<<18)<br>-#define DCH_SlowAccessMode (1<<20)<br>-#define DCH_BankSwizzleMode (1<<22)<br>+#define DCH_FourRankSODimm (1 << 17)<br>+#define DCH_FourRankRDimm (1 << 18)<br>+#define DCH_SlowAccessMode (1 << 20)<br>+#define DCH_BankSwizzleMode (1 << 22)<br> #define DCH_DcqBypassMax_SHIFT 24<br> #define DCH_DcqBypassMax_MASK 0xf<br> #define DCH_DcqBypassMax_BASE 0<br>@@ -318,8 +318,8 @@<br> #define DRAM_CTRL_ADDI_DATA_OFFSET 0x98<br> #define DCAO_DctOffset_SHIFT 0<br> #define DCAO_DctOffset_MASK 0x3fffffff<br>-#define DCAO_DctAccessWrite (1<<30)<br>-#define DCAO_DctAccessDone (1<<31)<br>+#define DCAO_DctAccessWrite (1 << 30)<br>+#define DCAO_DctAccessDone (1 << 31)<br> <br> #define DRAM_CTRL_ADDI_DATA_PORT 0x9c<br> <br>@@ -414,19 +414,19 @@<br> #define DACTC_CkeFineDelay_BASE 0<br> #define DACTC_CkeFineDelay_MIN 0<br> #define DACTC_CkeFineDelay_MAX 31<br>-#define DACTC_CkeSetup (1<<5)<br>+#define DACTC_CkeSetup (1 << 5)<br> #define DACTC_CsOdtFineDelay_SHIFT 8<br> #define DACTC_CsOdtFineDelay_MASK 0x1f<br> #define DACTC_CsOdtFineDelay_BASE 0<br> #define DACTC_CsOdtFineDelay_MIN 0<br> #define DACTC_CsOdtFineDelay_MAX 31<br>-#define DACTC_CsOdtSetup (1<<13)<br>+#define DACTC_CsOdtSetup (1 << 13)<br> #define DACTC_AddrCmdFineDelay_SHIFT 16<br> #define DACTC_AddrCmdFineDelay_MASK 0x1f<br> #define DACTC_AddrCmdFineDelay_BASE 0<br> #define DACTC_AddrCmdFineDelay_MIN 0<br> #define DACTC_AddrCmdFineDelay_MAX 31<br>-#define DACTC_AddrCmdSetup (1<<21)<br>+#define DACTC_AddrCmdSetup (1 << 21)<br> <br> #define DRAM_READ_DQS_TIMING_CTRL_LOW 0x05<br> #define DRDTC_RdDqsTimeByte0_SHIFT 0<br>@@ -448,17 +448,17 @@<br> #define DRDETC_RdDqsTimeCheck_SHIFT 0<br> <br> #define DRAM_PHY_CTRL 0x08<br>-#define DPC_WrtLvTrEn (1<<0)<br>-#define DPC_WrtLvTrMode (1<<1)<br>-#define DPC_TrNibbleSel (1<<2)<br>+#define DPC_WrtLvTrEn (1 << 0)<br>+#define DPC_WrtLvTrMode (1 << 1)<br>+#define DPC_TrNibbleSel (1 << 2)<br> #define DPC_TrDimmSel_SHIFT 4<br> #define DPC_TrDimmSel_MASK 3 /* 0-->dimm0, 1-->dimm1, 2--->dimm2, 3--->dimm3 */<br> #define DPC_WrLvOdt_SHIFT 8<br> #define DPC_WrLvOdt_MASK 0xf /* bit 0-->odt 0, ...*/<br>-#define DPC_WrLvODtEn (1<<12)<br>-#define DPC_DqsRcvTrEn (1<<13)<br>-#define DPC_DisAutoComp (1<<30)<br>-#define DPC_AsyncCompUpdate (1<<31)<br>+#define DPC_WrLvODtEn (1 << 12)<br>+#define DPC_DqsRcvTrEn (1 << 13)<br>+#define DPC_DisAutoComp (1 << 30)<br>+#define DPC_AsyncCompUpdate (1 << 31)<br> <br> #define DRAM_DQS_RECV_ENABLE_TIME_CTRL_0_0 0x10 //DIMM0 Channel A<br> #define DDRETC_DqsRcvEnFineDelayByte0_SHIFT 0<br>@@ -564,8 +564,8 @@<br> #define DWLE_WrLvErr_MASK 0xff<br> <br> #define DRAM_CTRL_MISC 0xa0<br>-#define DCM_MemCleared (1<<0) /* RD == F2x110 [MemCleared] */<br>-#define DCM_DramEnabled (1<<9) /* RD == F2x110 [DramEnabled] */<br>+#define DCM_MemCleared (1 << 0) /* RD == F2x110 [MemCleared] */<br>+#define DCM_DramEnabled (1 << 9) /* RD == F2x110 [DramEnabled] */<br> <br> #define NB_TIME_STAMP_COUNT_LOW 0xb0<br> #define TscLow_SHIFT 0<br>@@ -578,24 +578,24 @@<br> #define DCT_DEBUG_CTRL 0xf0 /* 0xf0 for DCT0, 0x1f0 is for DCT1*/<br> #define DDC_DllAdjust_SHIFT 0<br> #define DDC_DllAdjust_MASK 0xff<br>-#define DDC_DllSlower (1<<8)<br>-#define DDC_DllFaster (1<<9)<br>+#define DDC_DllSlower (1 << 8)<br>+#define DDC_DllFaster (1 << 9)<br> #define DDC_WrtDqsAdjust_SHIFT 16<br> #define DDC_WrtDqsAdjust_MASK 0x7<br>-#define DDC_WrtDqsAdjustEn (1<<19)<br>+#define DDC_WrtDqsAdjustEn (1 << 19)<br> <br> #define DRAM_CTRL_SEL_LOW 0x110<br>-#define DCSL_DctSelHiRngEn (1<<0)<br>-#define DCSL_DctSelHi (1<<1)<br>-#define DCSL_DctSelIntLvEn (1<<2)<br>-#define DCSL_MemClrInit (1<<3) /* WR only */<br>-#define DCSL_DctGangEn (1<<4)<br>-#define DCSL_DctDataIntLv (1<<5)<br>+#define DCSL_DctSelHiRngEn (1 << 0)<br>+#define DCSL_DctSelHi (1 << 1)<br>+#define DCSL_DctSelIntLvEn (1 << 2)<br>+#define DCSL_MemClrInit (1 << 3) /* WR only */<br>+#define DCSL_DctGangEn (1 << 4)<br>+#define DCSL_DctDataIntLv (1 << 5)<br> #define DCSL_DctSelIntLvAddr_SHIFT<br> #define DCSL_DctSelIntLvAddr_MASK 3<br>-#define DCSL_DramEnable (1<<8) /* RD only */<br>-#define DCSL_MemClrBusy (1<<9) /* RD only */<br>-#define DCSL_MemCleared (1<<10) /* RD only */<br>+#define DCSL_DramEnable (1 << 8) /* RD only */<br>+#define DCSL_MemClrBusy (1 << 9) /* RD only */<br>+#define DCSL_MemCleared (1 << 10) /* RD only */<br> #define DCSL_DctSelBaseAddr_47_27_SHIFT 11<br> #define DCSL_DctSelBaseAddr_47_27_MASK 0x1fffff<br> <br>@@ -604,8 +604,8 @@<br> #define DCSH_DctSelBaseOffset_47_26_MASK 0x3fffff<br> <br> #define MEM_CTRL_CONF_LOW 0x118<br>-#define MCCL_MctPriCpuRd (1<<0)<br>-#define MCCL_MctPriCpuWr (1<<1)<br>+#define MCCL_MctPriCpuRd (1 << 0)<br>+#define MCCL_MctPriCpuWr (1 << 1)<br> #define MCCL_MctPriIsocRd_SHIFT 4<br> #define MCCL_MctPriIsoc_MASK 0x3<br> #define MCCL_MctPriIsocWr_SHIFT 6<br>@@ -634,10 +634,10 @@<br> #define MCCH_MctWrLimit_MASK 0x1f<br> #define MCCH_MctPrefReqLimit_SHIFT 7<br> #define MCCH_MctPrefReqLimit_MASK 0x1f<br>-#define MCCH_PrefCpuDis (1<<12)<br>-#define MCCH_PrefIoDis (1<<13)<br>-#define MCCH_PrefIoFixStrideEn (1<<14)<br>-#define MCCH_PrefFixStrideEn (1<<15)<br>+#define MCCH_PrefCpuDis (1 << 12)<br>+#define MCCH_PrefIoDis (1 << 13)<br>+#define MCCH_PrefIoFixStrideEn (1 << 14)<br>+#define MCCH_PrefFixStrideEn (1 << 15)<br> #define MCCH_PrefFixDist_SHIFT 16<br> #define MCCH_PrefFixDist_MASK 0x3<br> #define MCCH_PrefConfSat_SHIFT 18<br>@@ -648,78 +648,78 @@<br> #define MCCH_PrefTwoConf_MASK 0x7<br> #define MCCH_PrefThreeConf_SHIFT 25<br> #define MCCH_prefThreeConf_MASK 0x7<br>-#define MCCH_PrefDramTrainMode (1<<28)<br>-#define MCCH_FlushWrOnStpGnt (1<<29)<br>-#define MCCH_FlushWr (1<<30)<br>-#define MCCH_MctScrubEn (1<<31)<br>+#define MCCH_PrefDramTrainMode (1 << 28)<br>+#define MCCH_FlushWrOnStpGnt (1 << 29)<br>+#define MCCH_FlushWr (1 << 30)<br>+#define MCCH_MctScrubEn (1 << 31)<br> <br> <br> /* Function 3 */<br> #define MCA_NB_CONTROL 0x40<br>-#define MNCT_CorrEccEn (1<<0)<br>-#define MNCT_UnCorrEccEn (1<<1)<br>-#define MNCT_CrcErr0En (1<<2) /* Link 0 */<br>-#define MNCT_CrcErr1En (1<<3)<br>-#define MNCT_CrcErr2En (1<<4)<br>-#define MBCT_SyncPkt0En (1<<5) /* Link 0 */<br>-#define MBCT_SyncPkt1En (1<<6)<br>-#define MBCT_SyncPkt2En (1<<7)<br>-#define MBCT_MstrAbrtEn (1<<8)<br>-#define MBCT_TgtAbrtEn (1<<9)<br>-#define MBCT_GartTblEkEn (1<<10)<br>-#define MBCT_AtomicRMWEn (1<<11)<br>-#define MBCT_WdogTmrRptEn (1<<12)<br>-#define MBCT_DevErrEn (1<<13)<br>-#define MBCT_L3ArrayCorEn (1<<14)<br>-#define MBCT_L3ArrayUncEn (1<<15)<br>-#define MBCT_HtProtEn (1<<16)<br>-#define MBCT_HtDataEn (1<<17)<br>-#define MBCT_DramParEn (1<<18)<br>-#define MBCT_RtryHt0En (1<<19) /* Link 0 */<br>-#define MBCT_RtryHt1En (1<<20)<br>-#define MBCT_RtryHt2En (1<<21)<br>-#define MBCT_RtryHt3En (1<<22)<br>-#define MBCT_CrcErr3En (1<<23) /* Link 3*/<br>-#define MBCT_SyncPkt3En (1<<24) /* Link 4 */<br>-#define MBCT_McaUsPwDatErrEn (1<<25)<br>-#define MBCT_NbArrayParEn (1<<26)<br>-#define MBCT_TblWlkDatErrEn (1<<27)<br>-#define MBCT_FbDimmCorErrEn (1<<28)<br>-#define MBCT_FbDimmUnCorErrEn (1<<29)<br>+#define MNCT_CorrEccEn (1 << 0)<br>+#define MNCT_UnCorrEccEn (1 << 1)<br>+#define MNCT_CrcErr0En (1 << 2) /* Link 0 */<br>+#define MNCT_CrcErr1En (1 << 3)<br>+#define MNCT_CrcErr2En (1 << 4)<br>+#define MBCT_SyncPkt0En (1 << 5) /* Link 0 */<br>+#define MBCT_SyncPkt1En (1 << 6)<br>+#define MBCT_SyncPkt2En (1 << 7)<br>+#define MBCT_MstrAbrtEn (1 << 8)<br>+#define MBCT_TgtAbrtEn (1 << 9)<br>+#define MBCT_GartTblEkEn (1 << 10)<br>+#define MBCT_AtomicRMWEn (1 << 11)<br>+#define MBCT_WdogTmrRptEn (1 << 12)<br>+#define MBCT_DevErrEn (1 << 13)<br>+#define MBCT_L3ArrayCorEn (1 << 14)<br>+#define MBCT_L3ArrayUncEn (1 << 15)<br>+#define MBCT_HtProtEn (1 << 16)<br>+#define MBCT_HtDataEn (1 << 17)<br>+#define MBCT_DramParEn (1 << 18)<br>+#define MBCT_RtryHt0En (1 << 19) /* Link 0 */<br>+#define MBCT_RtryHt1En (1 << 20)<br>+#define MBCT_RtryHt2En (1 << 21)<br>+#define MBCT_RtryHt3En (1 << 22)<br>+#define MBCT_CrcErr3En (1 << 23) /* Link 3*/<br>+#define MBCT_SyncPkt3En (1 << 24) /* Link 4 */<br>+#define MBCT_McaUsPwDatErrEn (1 << 25)<br>+#define MBCT_NbArrayParEn (1 << 26)<br>+#define MBCT_TblWlkDatErrEn (1 << 27)<br>+#define MBCT_FbDimmCorErrEn (1 << 28)<br>+#define MBCT_FbDimmUnCorErrEn (1 << 29)<br> <br> <br> <br> #define MCA_NB_CONFIG 0x44<br>-#define MNC_CpuRdDatErrEn (1<<1)<br>-#define MNC_SyncOnUcEccEn (1<<2)<br>-#define MNC_SynvPktGenDis (1<<3)<br>-#define MNC_SyncPktPropDis (1<<4)<br>-#define MNC_IoMstAbortDis (1<<5)<br>-#define MNC_CpuErrDis (1<<6)<br>-#define MNC_IoErrDis (1<<7)<br>-#define MNC_WdogTmrDis (1<<8)<br>+#define MNC_CpuRdDatErrEn (1 << 1)<br>+#define MNC_SyncOnUcEccEn (1 << 2)<br>+#define MNC_SynvPktGenDis (1 << 3)<br>+#define MNC_SyncPktPropDis (1 << 4)<br>+#define MNC_IoMstAbortDis (1 << 5)<br>+#define MNC_CpuErrDis (1 << 6)<br>+#define MNC_IoErrDis (1 << 7)<br>+#define MNC_WdogTmrDis (1 << 8)<br> #define MNC_WdogTmrCntSel_2_0_SHIFT 9 /* 3 is ar f3x180 */<br> #define MNC_WdogTmrCntSel_2_0_MASK 0x3<br> #define MNC_WdogTmrBaseSel_SHIFT 12<br> #define MNC_WdogTmrBaseSel_MASK 0x3<br> #define MNC_LdtLinkSel_SHIFT 14<br> #define MNC_LdtLinkSel_MASK 0x3<br>-#define MNC_GenCrcErrByte0 (1<<16)<br>-#define MNC_GenCrcErrByte1 (1<<17)<br>+#define MNC_GenCrcErrByte0 (1 << 16)<br>+#define MNC_GenCrcErrByte1 (1 << 17)<br> #define MNC_SubLinkSel_SHIFT 18<br> #define MNC_SubLinkSel_MASK 0x3<br>-#define MNC_SyncOnWdogEn (1<<20)<br>-#define MNC_SyncOnAnyErrEn (1<<21)<br>-#define MNC_DramEccEn (1<<22)<br>-#define MNC_ChipKillEccEn (1<<23)<br>-#define MNC_IoRdDatErrEn (1<<24)<br>-#define MNC_DisPciCfgCpuErrRsp (1<<25)<br>-#define MNC_CorrMcaExcEn (1<<26)<br>-#define MNC_NbMcaToMstCpuEn (1<<27)<br>-#define MNC_DisTgtAbtCpuErrRsp (1<<28)<br>-#define MNC_DisMstAbtCpuErrRsp (1<<29)<br>-#define MNC_SyncOnDramAdrParErrEn (1<<30)<br>-#define MNC_NbMcaLogEn (1<<31)<br>+#define MNC_SyncOnWdogEn (1 << 20)<br>+#define MNC_SyncOnAnyErrEn (1 << 21)<br>+#define MNC_DramEccEn (1 << 22)<br>+#define MNC_ChipKillEccEn (1 << 23)<br>+#define MNC_IoRdDatErrEn (1 << 24)<br>+#define MNC_DisPciCfgCpuErrRsp (1 << 25)<br>+#define MNC_CorrMcaExcEn (1 << 26)<br>+#define MNC_NbMcaToMstCpuEn (1 << 27)<br>+#define MNC_DisTgtAbtCpuErrRsp (1 << 28)<br>+#define MNC_DisMstAbtCpuErrRsp (1 << 29)<br>+#define MNC_SyncOnDramAdrParErrEn (1 << 30)<br>+#define MNC_NbMcaLogEn (1 << 31)<br> <br> #define MCA_NB_STATUS_LOW 0x48<br> #define MNSL_ErrorCode_SHIFT 0<br>@@ -734,22 +734,22 @@<br> #define MNSH_ErrCPU_MASK 0xf<br> #define MNSH_LDTLink_SHIFT 4<br> #define MNSH_LDTLink_MASK 0xf<br>-#define MNSH_ErrScrub (1<<8)<br>-#define MNSH_SubLink (1<<9)<br>+#define MNSH_ErrScrub (1 << 8)<br>+#define MNSH_SubLink (1 << 9)<br> #define MNSH_McaStatusSubCache_SHIFT 10<br> #define MNSH_McaStatusSubCache_MASK 0x3<br>-#define MNSH_Deffered (1<<12)<br>-#define MNSH_UnCorrECC (1<<13)<br>-#define MNSH_CorrECC (1<<14)<br>+#define MNSH_Deffered (1 << 12)<br>+#define MNSH_UnCorrECC (1 << 13)<br>+#define MNSH_CorrECC (1 << 14)<br> #define MNSH_Syndrome_7_0_SHIFT 15<br> #define MNSH_Syndrome_7_0_MASK 0xff<br>-#define MNSH_PCC (1<<25)<br>-#define MNSH_ErrAddrVal (1<<26)<br>-#define MNSH_ErrMiscVal (1<<27)<br>-#define MNSH_ErrEn (1<<28)<br>-#define MNSH_ErrUnCorr (1<<29)<br>-#define MNSH_ErrOver (1<<30)<br>-#define MNSH_ErrValid (1<<31)<br>+#define MNSH_PCC (1 << 25)<br>+#define MNSH_ErrAddrVal (1 << 26)<br>+#define MNSH_ErrMiscVal (1 << 27)<br>+#define MNSH_ErrEn (1 << 28)<br>+#define MNSH_ErrUnCorr (1 << 29)<br>+#define MNSH_ErrOver (1 << 30)<br>+#define MNSH_ErrValid (1 << 31)<br> <br> #define MCA_NB_ADDR_LOW 0x50<br> #define MNAL_ErrAddr_31_1_SHIFT 1<br>@@ -793,7 +793,7 @@<br> #define DSRC_L3Scrub_MASK 0x1f<br> <br> #define DRAM_SCRUB_ADDR_LOW 0x5C<br>-#define DSAL_ScrubReDirEn (1<<0)<br>+#define DSAL_ScrubReDirEn (1 << 0)<br> #define DSAL_ScrubAddrLo_SHIFT 6<br> #define DSAL_ScrubAddrLo_MASK 0x3ffffff<br> <br>@@ -863,8 +863,8 @@<br> #define NBCAP_DdrMaxRate_8_0G 2<br> #define NBCAP_DdrMaxRate_9_6G 1<br> #define NBCAP_Mem_ctrl_cap (1 << 8)<br>-#define MBCAP_SVMCap (1<<9)<br>-#define NBCAP_HtcCap (1<<10)<br>+#define MBCAP_SVMCap (1 << 9)<br>+#define NBCAP_HtcCap (1 << 10)<br> #define NBCAP_CmpCap_SHIFT 12<br> #define NBCAP_CmpCap_MASK 3<br> #define NBCAP_MpCap_SHIFT 16<br>@@ -876,8 +876,8 @@<br> #define NBCAP_MpCap_32N 0<br> #define NBCAP_UnGangEn_SHIFT 20<br> #define NBCAP_UnGangEn_MASK 0xf<br>-#define NBCAP_L3Cap (1<<25)<br>-#define NBCAP_HtAcCap (1<<26)<br>+#define NBCAP_L3Cap (1 << 25)<br>+#define NBCAP_HtAcCap (1 << 26)<br> <br> /* 04/04/2006 18:00 */<br> <br>diff --git a/src/northbridge/amd/amdfam10/early_ht.c b/src/northbridge/amd/amdfam10/early_ht.c<br>index c3b02d7..bfb7940 100644<br>--- a/src/northbridge/amd/amdfam10/early_ht.c<br>+++ b/src/northbridge/amd/amdfam10/early_ht.c<br>@@ -25,7 +25,7 @@<br> #if CONFIG_EXT_RT_TBL_SUPPORT<br> u32 dword;<br> dword = pci_io_read_config32(PCI_DEV(0, 0x18, 0), 0x68);<br>- dword |= (1<<27) | (1<<25);<br>+ dword |= (1 << 27) | (1 << 25);<br> /* CHtExtNodeCfgEn: coherent link extended node configuration enable,<br> Nodes[31:0] will be 0xff:[31:0], Nodes[63:32] will be 0xfe:[31:0]<br> ---- 32 nodes now only<br>diff --git a/src/northbridge/amd/amdfam10/get_pci1234.c b/src/northbridge/amd/amdfam10/get_pci1234.c<br>index 08698dc..923600c 100644<br>--- a/src/northbridge/amd/amdfam10/get_pci1234.c<br>+++ b/src/northbridge/amd/amdfam10/get_pci1234.c<br>@@ -58,7 +58,7 @@<br> int i,j;<br> u32 dword;<br> <br>- dword = sysconf.sblk<<8;<br>+ dword = sysconf.sblk << 8;<br> dword |= 1;<br> sysconf.pci1234[0] = dword; // sblink<br> sysconf.hcid[0] = 0;<br>diff --git a/src/northbridge/amd/amdfam10/ht_config.c b/src/northbridge/amd/amdfam10/ht_config.c<br>index 916111c..e18a361 100644<br>--- a/src/northbridge/amd/amdfam10/ht_config.c<br>+++ b/src/northbridge/amd/amdfam10/ht_config.c<br>@@ -32,14 +32,14 @@<br> temp = pci_read_config32(dev, 0x44 + (nodeid << 3)); //[39:24] at [31:16]<br> d.mask = ((temp & 0xfff80000)>>(8+3)); // mask out DramMask [26:24] too<br> temp = pci_read_config32(dev, 0x144 + (nodeid <<3)) & 0xff; //[47:40] at [7:0]<br>- d.mask |= temp<<21;<br>+ d.mask |= temp << 21;<br> <br> temp = pci_read_config32(dev, 0x40 + (nodeid << 3)); //[39:24] at [31:16]<br> d.mask |= (temp & 1); // enable bit<br> <br> d.base = ((temp & 0xfff80000)>>(8+3)); // mask out DramBase [26:24) too<br> temp = pci_read_config32(dev, 0x140 + (nodeid <<3)) & 0xff; //[47:40] at [7:0]<br>- d.base |= temp<<21;<br>+ d.base |= temp << 21;<br> return d;<br> }<br> <br>@@ -163,9 +163,9 @@<br> index = (reg-0xc0)>>3;<br> <br> val = (nodeid & 0x3f); // 6 bits used<br>- sysconf.conf_io_addr[index] = val | ((io_max<<8) & 0xfffff000); //limit : with nodeid<br>+ sysconf.conf_io_addr[index] = val | ((io_max << 8) & 0xfffff000); //limit : with nodeid<br> val = 3 | ((linkn & 0x7)<<4); // 8 bits used<br>- sysconf.conf_io_addrx[index] = val | ((io_min<<8) & 0xfffff000); // base : with enable bit<br>+ sysconf.conf_io_addrx[index] = val | ((io_min << 8) & 0xfffff000); // base : with enable bit<br> <br> if (sysconf.io_addr_num < (index+1))<br> sysconf.io_addr_num = index+1;<br>@@ -197,11 +197,11 @@<br> u32 tempreg;<br> <br> /* io range allocation */<br>- tempreg = (nodeid&0xf) | ((nodeid & 0x30)<<(8-4)) | (linkn<<4) | ((io_max&0xf0)<<(12-4)); //limit<br>+ tempreg = (nodeid&0xf) | ((nodeid & 0x30)<<(8-4)) | (linkn << 4) | ((io_max&0xf0)<<(12-4)); //limit<br> for (i = 0; i < sysconf.nodes; i++)<br> pci_write_config32(__f1_dev[i], reg+4, tempreg);<br> <br>- tempreg = 3 /*| (3<<4)*/ | ((io_min&0xf0)<<(12-4)); //base :ISA and VGA ?<br>+ tempreg = 3 /*| (3 << 4)*/ | ((io_min&0xf0)<<(12-4)); //base :ISA and VGA ?<br> for (i = 0; i < sysconf.nodes; i++)<br> pci_write_config32(__f1_dev[i], reg, tempreg);<br> }<br>@@ -212,7 +212,7 @@<br> u32 tempreg;<br> <br> /* io range allocation */<br>- tempreg = (nodeid&0xf) | (linkn<<4) | (mmio_max&0xffffff00); //limit<br>+ tempreg = (nodeid&0xf) | (linkn << 4) | (mmio_max&0xffffff00); //limit<br> for (i = 0; i < nodes; i++)<br> pci_write_config32(__f1_dev[i], reg+4, tempreg);<br> tempreg = 3 | (nodeid & 0x30) | (mmio_min&0xffffff00);<br>diff --git a/src/northbridge/amd/amdfam10/misc_control.c b/src/northbridge/amd/amdfam10/misc_control.c<br>index 7cd9bff..def466a 100644<br>--- a/src/northbridge/amd/amdfam10/misc_control.c<br>+++ b/src/northbridge/amd/amdfam10/misc_control.c<br>@@ -89,7 +89,7 @@<br> resource->flags |= IORESOURCE_STORED;<br> <br> /* Find the size of the GART aperture */<br>- gart_acr = (0<<6)|(0<<5)|(0<<4)|((resource->gran - 25) << 1)|(0<<0);<br>+ gart_acr = (0 << 6)|(0 << 5)|(0 << 4)|((resource->gran - 25) << 1)|(0 << 0);<br> <br> /* Get the base address */<br> gart_base = ((resource->base) >> 25) & 0x00007fff;<br>@@ -194,7 +194,7 @@<br> * This is needed for PC backwards compatibility.<br> */<br> dword = pci_read_config32(dev, 0x44);<br>- dword |= (1<<6) | (1<<25);<br>+ dword |= (1 << 6) | (1 << 25);<br> pci_write_config32(dev, 0x44, dword);<br> <br> boost_limit = 0xf;<br>diff --git a/src/northbridge/amd/amdfam10/northbridge.c b/src/northbridge/amd/amdfam10/northbridge.c<br>index dccd9c6..4be52f7 100644<br>--- a/src/northbridge/amd/amdfam10/northbridge.c<br>+++ b/src/northbridge/amd/amdfam10/northbridge.c<br>@@ -138,7 +138,7 @@<br> {<br> u32 val;<br> <br>- val = 1 | (nodeid<<4) | (linkn<<12);<br>+ val = 1 | (nodeid << 4) | (linkn << 12);<br> /* it will routing (1)mmio 0xa0000:0xbffff (2) io 0x3b0:0x3bb,<br> 0x3c0:0x3df */<br> f1_write_config32(0xf4, val);<br>@@ -426,7 +426,7 @@<br> if (!reg) {<br> //because of Extend conf space, we will never run out of reg, but we need one index to differ them. so same node and same link can have multi range<br> u32 index = get_io_addr_index(nodeid, link);<br>- reg = 0x110+ (index<<24) + (4<<20); // index could be 0, 255<br>+ reg = 0x110+ (index << 24) + (4 << 20); // index could be 0, 255<br> }<br> <br> resource = new_resource(dev, IOINDEX(0x1000 + reg, link));<br>@@ -461,7 +461,7 @@<br> // but we need one index to differ them. so same node and<br> // same link can have multi range<br> u32 index = get_mmio_addr_index(nodeid, link);<br>- reg = 0x110+ (index<<24) + (6<<20); // index could be 0, 63<br>+ reg = 0x110+ (index << 24) + (6 << 20); // index could be 0, 63<br> <br> }<br> resource = new_resource(dev, IOINDEX(0x1000 + reg, link));<br>@@ -852,7 +852,7 @@<br> <br> hole = pci_read_config32(__f1_dev[i], 0xf0);<br> if (hole & 1) { // we find the hole<br>- mem_hole.hole_startk = (hole & (0xff<<24)) >> 10;<br>+ mem_hole.hole_startk = (hole & (0xff << 24)) >> 10;<br> mem_hole.node_id = i; // record the node No with hole<br> break; // only one hole<br> }<br>@@ -1448,7 +1448,7 @@<br> nb_cfg_54 = 0;<br> ApicIdCoreIdSize = (cpuid_ecx(0x80000008)>>12 & 0xf);<br> if (ApicIdCoreIdSize) {<br>- siblings = (1<<ApicIdCoreIdSize)-1;<br>+ siblings = (1 << ApicIdCoreIdSize)-1;<br> } else {<br> siblings = 3; //quad core<br> }<br>diff --git a/src/northbridge/amd/amdfam10/pci.c b/src/northbridge/amd/amdfam10/pci.c<br>index 6c6d717..250ded4 100644<br>--- a/src/northbridge/amd/amdfam10/pci.c<br>+++ b/src/northbridge/amd/amdfam10/pci.c<br>@@ -44,11 +44,11 @@<br> <br> u32 dword;<br> <br>- index &= ~(1<<30);<br>+ index &= ~(1 << 30);<br> pci_write_config32(dev, index_reg, index);<br> do {<br> dword = pci_read_config32(dev, index_reg);<br>- } while (!(dword & (1<<31)));<br>+ } while (!(dword & (1 << 31)));<br> dword = pci_read_config32(dev, index_reg+0x4);<br> return dword;<br> }<br>@@ -61,11 +61,11 @@<br> u32 dword;<br> <br> pci_write_config32(dev, index_reg + 0x4, data);<br>- index |= (1<<30);<br>+ index |= (1 << 30);<br> pci_write_config32(dev, index_reg, index);<br> do {<br> dword = pci_read_config32(dev, index_reg);<br>- } while (!(dword & (1<<31)));<br>+ } while (!(dword & (1 << 31)));<br> <br> }<br> #endif<br>diff --git a/src/northbridge/amd/amdfam10/raminit_sysinfo_in_ram.c b/src/northbridge/amd/amdfam10/raminit_sysinfo_in_ram.c<br>index dce2053..3044095 100644<br>--- a/src/northbridge/amd/amdfam10/raminit_sysinfo_in_ram.c<br>+++ b/src/northbridge/amd/amdfam10/raminit_sysinfo_in_ram.c<br>@@ -21,7 +21,7 @@<br> {<br> u32 dword;<br> dword = pci_read_config32(NODE_PCI(i, 0), HT_INIT_CONTROL);<br>- dword &= ~(1<<bit);<br>+ dword &= ~(1 << bit);<br> dword |= ((val & 1) <<bit);<br> pci_write_config32(NODE_PCI(i, 0), HT_INIT_CONTROL, dword);<br> }<br>@@ -31,7 +31,7 @@<br> {<br> u32 dword;<br> dword = pci_read_config32(NODE_PCI(i, 0), HT_INIT_CONTROL);<br>- dword &= (1<<bit);<br>+ dword &= (1 << bit);<br> return dword;<br> }<br> <br>diff --git a/src/northbridge/amd/amdht/comlib.c b/src/northbridge/amd/amdht/comlib.c<br>index 85cbbc4..d2c85ae 100644<br>--- a/src/northbridge/amd/amdht/comlib.c<br>+++ b/src/northbridge/amd/amdht/comlib.c<br>@@ -38,7 +38,7 @@<br> AmdPCIRead(loc, pValue);<br> *pValue = *pValue >> lowbit; /* Shift */<br> <br>- /* A 1<<32 == 1<<0 due to x86 SHL instruction, so skip if that is the case */<br>+ /* A 1 << 32 == 1 << 0 due to x86 SHL instruction, so skip if that is the case */<br> if ((highbit-lowbit) != 31)<br> *pValue &= (((u32)1 << (highbit-lowbit+1))-1);<br> }<br>@@ -50,7 +50,7 @@<br> <br> ASSERT(highbit < 32 && lowbit < 32 && highbit >= lowbit && (loc & 3) == 0);<br> <br>- /* A 1<<32 == 1<<0 due to x86 SHL instruction, so skip if that is the case */<br>+ /* A 1 << 32 == 1 << 0 due to x86 SHL instruction, so skip if that is the case */<br> if ((highbit-lowbit) != 31)<br> mask = (((u32)1 << (highbit-lowbit+1))-1);<br> else<br>diff --git a/src/northbridge/amd/amdht/h3finit.c b/src/northbridge/amd/amdht/h3finit.c<br>index 6a9d898..fbb2e67 100644<br>--- a/src/northbridge/amd/amdht/h3finit.c<br>+++ b/src/northbridge/amd/amdht/h3finit.c<br>@@ -846,7 +846,7 @@<br> <br> for (k = 0; k < MAX_NODES; k++)<br> {<br>- if (AbstractBcTargetNodes & ((u32)1<<k))<br>+ if (AbstractBcTargetNodes & ((u32)1 << k))<br> {<br> BcTargetLinks |= (u32)1 << convertNodeToLink(i, pDat->ReversePerm[k], pDat);<br> }<br>diff --git a/src/northbridge/amd/amdht/h3ncmn.c b/src/northbridge/amd/amdht/h3ncmn.c<br>index 5f656f5..281566c 100644<br>--- a/src/northbridge/amd/amdht/h3ncmn.c<br>+++ b/src/northbridge/amd/amdht/h3ncmn.c<br>@@ -178,7 +178,7 @@<br> ASSERT((hiBit < 32) && (loBit < 32) && (hiBit >= loBit) && ((reg & 0x3) == 0));<br> ASSERT((hiBit < 8) || (loBit > 9));<br> <br>- /* A 1<<32 == 1<<0 due to x86 SHL instruction, so skip if that is the case */<br>+ /* A 1 << 32 == 1 << 0 due to x86 SHL instruction, so skip if that is the case */<br> if ((hiBit-loBit) != 31)<br> mask = (((u32)1 << (hiBit-loBit+1))-1);<br> else<br>diff --git a/src/northbridge/amd/amdk8/amdk8.h b/src/northbridge/amd/amdk8/amdk8.h<br>index e335a98..3cd8174 100644<br>--- a/src/northbridge/amd/amdk8/amdk8.h<br>+++ b/src/northbridge/amd/amdk8/amdk8.h<br>@@ -11,9 +11,9 @@<br> #include "pre_f.h"<br> #endif<br> <br>-#define HTIC_ColdR_Detect (1<<4)<br>-#define HTIC_BIOSR_Detect (1<<5)<br>-#define HTIC_INIT_Detect (1<<6)<br>+#define HTIC_ColdR_Detect (1 << 4)<br>+#define HTIC_BIOSR_Detect (1 << 5)<br>+#define HTIC_INIT_Detect (1 << 6)<br> <br> #define NODE_HT(x) PCI_DEV(0,24+x,0)<br> #define NODE_MP(x) PCI_DEV(0,24+x,1)<br>diff --git a/src/northbridge/amd/amdk8/coherent_ht.c b/src/northbridge/amd/amdk8/coherent_ht.c<br>index 10ca6ee..e688d4f 100644<br>--- a/src/northbridge/amd/amdk8/coherent_ht.c<br>+++ b/src/northbridge/amd/amdk8/coherent_ht.c<br>@@ -178,7 +178,7 @@<br> printk(BIOS_SPEW, "Enabling routing table for node %d", node);<br> <br> val = pci_read_config32(NODE_HT(node), 0x6c);<br>- val &= ~((1<<1)|(1<<0));<br>+ val &= ~((1 << 1)|(1 << 0));<br> pci_write_config32(NODE_HT(node), 0x6c, val);<br> <br> printk(BIOS_SPEW, " done.\n");<br>@@ -187,7 +187,7 @@<br> #if CONFIG_MAX_PHYSICAL_CPUS > 1<br> static void fill_row(u8 node, u8 row, u32 value)<br> {<br>- pci_write_config32(NODE_HT(node), 0x40+(row<<2), value);<br>+ pci_write_config32(NODE_HT(node), 0x40+(row << 2), value);<br> }<br> <br> static u8 link_to_register(int ldt)<br>@@ -211,7 +211,7 @@<br> <br> static u32 get_row(u8 node, u8 row)<br> {<br>- return pci_read_config32(NODE_HT(node), 0x40+(row<<2));<br>+ return pci_read_config32(NODE_HT(node), 0x40+(row << 2));<br> }<br> <br> static int link_connection(u8 src, u8 dest)<br>@@ -411,7 +411,7 @@<br> //(6,5) (7,4) should be here<br> #endif<br> ) {<br>- val |= (1<<16);<br>+ val |= (1 << 16);<br> } else {<br> /*for CROSS_BAR_47_56 47, 56, should be here too<br> and for 47, 56, 57, 75, 46, 64 we need to substract another link to<br>@@ -559,11 +559,11 @@<br> }<br> #endif<br> val &= 0xff;<br>- val |= (val_s<<8);<br>+ val |= (val_s << 8);<br> }<br> <br> if (diff) { /* cross rung?*/<br>- val |= (1<<16);<br>+ val |= (1 << 16);<br> }<br> else {<br> val_s = get_row(temp, source);<br>@@ -1615,15 +1615,15 @@<br> */<br> cmd = pci_read_config32(dev, 0x70);<br> if ((cmd & (3 << 0)) != 2) {<br>- cmd &= ~(3<<0);<br>- cmd |= (2<<0);<br>+ cmd &= ~(3 << 0);<br>+ cmd |= (2 << 0);<br> pci_write_config32(dev, 0x70, cmd);<br> needs_reset = 1;<br> }<br> cmd = pci_read_config32(dev, 0x7c);<br> if ((cmd & (3 << 4)) != 0) {<br>- cmd &= ~(3<<4);<br>- cmd |= (0<<4);<br>+ cmd &= ~(3 << 4);<br>+ cmd |= (0 << 4);<br> pci_write_config32(dev, 0x7c, cmd);<br> needs_reset = 1;<br> }<br>diff --git a/src/northbridge/amd/amdk8/f.h b/src/northbridge/amd/amdk8/f.h<br>index f3f9c42..cbed691 100644<br>--- a/src/northbridge/amd/amdk8/f.h<br>+++ b/src/northbridge/amd/amdk8/f.h<br>@@ -65,24 +65,24 @@<br> #define DC_RdPadRcvFiloDly_2_5_CLK 4<br> #define DC_RdPadRcvFiloDly_3_CLK 5<br> #define DC_RdPadRcvFiloDly_3_5_CLK 6<br>-#define DC_AltVidC3MemClkTriEn (1<<16)<br>+#define DC_AltVidC3MemClkTriEn (1 << 16)<br> #define DC_DllTempAdjTime_SHIFT 17<br> #define DC_DllTempAdjTime_MASK 1<br> #define DC_DllTempAdjTime_5_MS 0<br> #define DC_DllTempAdjTime_1_MS 1<br>-#define DC_DqsRcvEnTrain (1<<18)<br>+#define DC_DqsRcvEnTrain (1 << 18)<br> <br> #define DRAM_INIT 0x7c<br> #define DI_MrsAddress_SHIFT 0<br> #define DI_MrsAddress_MASK 0xffff<br> #define DI_MrsBank_SHIFT 16<br> #define DI_MrsBank_MASK 7<br>-#define DI_SendRchgAll (1<<24)<br>-#define DI_SendAutoRefresh (1<<25)<br>-#define DI_SendMrsCmd (1<<26)<br>-#define DI_DeassertMemRstX (1<<27)<br>-#define DI_AssertCke (1<<28)<br>-#define DI_EnDramInit (1<<31)<br>+#define DI_SendRchgAll (1 << 24)<br>+#define DI_SendAutoRefresh (1 << 25)<br>+#define DI_SendMrsCmd (1 << 26)<br>+#define DI_DeassertMemRstX (1 << 27)<br>+#define DI_AssertCke (1 << 28)<br>+#define DI_EnDramInit (1 << 31)<br> <br> #define DRAM_TIMING_LOW 0x88<br> #define DTL_TCL_SHIFT 0<br>@@ -178,23 +178,23 @@<br> #define DTH_TRFC3_SHIFT 29 /*for Logical DIMM3 */<br> <br> #define DRAM_CONFIG_LOW 0x90<br>-#define DCL_InitDram (1<<0)<br>-#define DCL_ExitSelfRef (1<<1)<br>+#define DCL_InitDram (1 << 0)<br>+#define DCL_ExitSelfRef (1 << 1)<br> #define DCL_DramTerm_SHIFT 4<br> #define DCL_DramTerm_MASK 3<br> #define DCL_DramTerm_No 0<br> #define DCL_DramTerm_75_OH 1<br> #define DCL_DramTerm_150_OH 2<br> #define DCL_DramTerm_50_OH 3<br>-#define DCL_DrvWeak (1<<7)<br>-#define DCL_ParEn (1<<8)<br>-#define DCL_SelfRefRateEn (1<<9)<br>-#define DCL_BurstLength32 (1<<10)<br>-#define DCL_Width128 (1<<11)<br>+#define DCL_DrvWeak (1 << 7)<br>+#define DCL_ParEn (1 << 8)<br>+#define DCL_SelfRefRateEn (1 << 9)<br>+#define DCL_BurstLength32 (1 << 10)<br>+#define DCL_Width128 (1 << 11)<br> #define DCL_X4Dimm_SHIFT 12<br> #define DCL_X4Dimm_MASK 0xf<br>-#define DCL_UnBuffDimm (1<<16)<br>-#define DCL_DimmEccEn (1<<19)<br>+#define DCL_UnBuffDimm (1 << 16)<br>+#define DCL_DimmEccEn (1 << 19)<br> <br> #define DRAM_CONFIG_HIGH 0x94<br> #define DCH_MemClkFreq_SHIFT 0<br>@@ -203,23 +203,23 @@<br> #define DCH_MemClkFreq_266MHz 1<br> #define DCH_MemClkFreq_333MHz 2<br> #define DCH_MemClkFreq_400MHz 3<br>-#define DCH_MemClkFreqVal (1<<3)<br>+#define DCH_MemClkFreqVal (1 << 3)<br> #define DCH_MaxAsyncLat_SHIFT 4<br> #define DCH_MaxAsyncLat_MASK 0xf<br> #define DCH_MaxAsyncLat_BASE 0<br> #define DCH_MaxAsyncLat_MIN 0<br> #define DCH_MaxAsyncLat_MAX 15<br>-#define DCH_RDqsEn (1<<12)<br>-#define DCH_DisDramInterface (1<<14)<br>-#define DCH_PowerDownEn (1<<15)<br>+#define DCH_RDqsEn (1 << 12)<br>+#define DCH_DisDramInterface (1 << 14)<br>+#define DCH_PowerDownEn (1 << 15)<br> #define DCH_PowerDownMode_SHIFT 16<br> #define DCH_PowerDownMode_MASK 1<br> #define DCH_PowerDownMode_Channel_CKE 0<br> #define DCH_PowerDownMode_ChipSelect_CKE 1<br>-#define DCH_FourRankSODimm (1<<17)<br>-#define DCH_FourRankRDimm (1<<18)<br>-#define DCH_SlowAccessMode (1<<19)<br>-#define DCH_BankSwizzleMode (1<<22)<br>+#define DCH_FourRankSODimm (1 << 17)<br>+#define DCH_FourRankRDimm (1 << 18)<br>+#define DCH_SlowAccessMode (1 << 19)<br>+#define DCH_BankSwizzleMode (1 << 22)<br> #define DCH_DcqBypassMax_SHIFT 24<br> #define DCH_DcqBypassMax_MASK 0xf<br> #define DCH_DcqBypassMax_BASE 0<br>@@ -236,8 +236,8 @@<br> #define DRAM_CTRL_ADDI_DATA_OFFSET 0x98<br> #define DCAO_DctOffset_SHIFT 0<br> #define DCAO_DctOffset_MASK 0x3fffffff<br>-#define DCAO_DctAccessWrite (1<<30)<br>-#define DCAO_DctAccessDone (1<<31)<br>+#define DCAO_DctAccessWrite (1 << 30)<br>+#define DCAO_DctAccessDone (1 << 31)<br> <br> #define DRAM_CTRL_ADDI_DATA_PORT 0x9c<br> <br>@@ -313,19 +313,19 @@<br> #define DATC_CkeFineDelay_BASE 0<br> #define DATC_CkeFineDelay_MIN 0<br> #define DATC_CkeFineDelay_MAX 31<br>-#define DATC_CkeSetup (1<<5)<br>+#define DATC_CkeSetup (1 << 5)<br> #define DATC_CsOdtFineDelay_SHIFT 8<br> #define DATC_CsOdtFineDelay_MASK 0x1f<br> #define DATC_CsOdtFineDelay_BASE 0<br> #define DATC_CsOdtFineDelay_MIN 0<br> #define DATC_CsOdtFineDelay_MAX 31<br>-#define DATC_CsOdtSetup (1<<13)<br>+#define DATC_CsOdtSetup (1 << 13)<br> #define DATC_AddrCmdFineDelay_SHIFT 16<br> #define DATC_AddrCmdFineDelay_MASK 0x1f<br> #define DATC_AddrCmdFineDelay_BASE 0<br> #define DATC_AddrCmdFineDelay_MIN 0<br> #define DATC_AddrCmdFineDelay_MAX 31<br>-#define DATC_AddrCmdSetup (1<<21)<br>+#define DATC_AddrCmdSetup (1 << 21)<br> <br> #define DRAM_READ_DQS_TIMING_CTRL_LOW 0x05<br> #define DRDTCL_RdDqsTimeByte0_SHIFT 0<br>@@ -365,16 +365,16 @@<br> that are corresponding to 0x00, 0x01, 0x02, 0x03, 0x04, 0x05, 0x06, 0x07, 0x10, 0x13, 0x16, 0x19<br> */<br> #define DRAM_CTRL_MISC 0xa0<br>-#define DCM_MemClrStatus (1<<0)<br>-#define DCM_DisableJitter (1<<1)<br>+#define DCM_MemClrStatus (1 << 0)<br>+#define DCM_DisableJitter (1 << 1)<br> #define DCM_RdWrQByp_SHIFT 2<br> #define DCM_RdWrQByp_MASK 3<br> #define DCM_RdWrQByp_2 0<br> #define DCM_RdWrQByp_4 1<br> #define DCM_RdWrQByp_8 2<br> #define DCM_RdWrQByp_16 3<br>-#define DCM_Mode64BitMux (1<<4)<br>-#define DCM_DCC_EN (1<<5)<br>+#define DCM_Mode64BitMux (1 << 4)<br>+#define DCM_DCC_EN (1 << 5)<br> #define DCM_ILD_lmt_SHIFT 6<br> #define DCM_ILD_lmt_MASK 7<br> #define DCM_ILD_lmt_0 0<br>@@ -385,7 +385,7 @@<br> #define DCM_ILD_lmt_64 5<br> #define DCM_ILD_lmt_128 6<br> #define DCM_ILD_lmt_256 7<br>-#define DCM_DramEnabled (1<<9)<br>+#define DCM_DramEnabled (1 << 9)<br> #define DCM_MemClkDis_SHIFT 24 /* Channel B */<br> #define DCM_MemClkDis3 (1 << 26)<br> #define DCM_MemClkDis2 (1 << 27)<br>@@ -446,7 +446,7 @@<br> #define NBCAP_MEMCLK_333MHZ 1<br> #define NBCAP_MEMCLK_NOLIMIT 0<br> #define NBCAP_MEMCTRL (1 << 8)<br>-#define NBCAP_HtcCap (1<<10)<br>+#define NBCAP_HtcCap (1 << 10)<br> #define NBCAP_CmpCap_SHIFT 12<br> #define NBCAP_CmpCap_MASK 3<br> <br>@@ -541,15 +541,15 @@<br> /* Skip everything if I don't have any memory on this controller */<br> if (sysinfo->mem_trained[i]== 0x00) continue;<br> <br>- mask |= (1<<i);<br>+ mask |= (1 << i);<br> <br> }<br> <br> i = 1;<br> while (1) {<br>- if (mask & (1<<i)) {<br>+ if (mask & (1 << i)) {<br> if ((sysinfo->mem_trained[i])!=0x80) {<br>- mask &= ~(1<<i);<br>+ mask &= ~(1 << i);<br> }<br> }<br> <br>diff --git a/src/northbridge/amd/amdk8/f_pci.c b/src/northbridge/amd/amdk8/f_pci.c<br>index 230333a..ac2f2ff 100644<br>--- a/src/northbridge/amd/amdk8/f_pci.c<br>+++ b/src/northbridge/amd/amdk8/f_pci.c<br>@@ -31,12 +31,12 @@<br> {<br> uint32_t dword;<br> <br>- index &= ~(1<<30);<br>+ index &= ~(1 << 30);<br> pci_write_config32(dev, index_reg, index);<br> <br> do {<br> dword = pci_read_config32(dev, index_reg);<br>- } while (!(dword & (1<<31)));<br>+ } while (!(dword & (1 << 31)));<br> <br> dword = pci_read_config32(dev, index_reg+0x4);<br> <br>@@ -50,11 +50,11 @@<br> <br> pci_write_config32(dev, index_reg + 0x4, data);<br> <br>- index |= (1<<30);<br>+ index |= (1 << 30);<br> pci_write_config32(dev, index_reg, index);<br> do {<br> dword = pci_read_config32(dev, index_reg);<br>- } while (!(dword & (1<<31)));<br>+ } while (!(dword & (1 << 31)));<br> }<br> <br> #endif<br>diff --git a/src/northbridge/amd/amdk8/incoherent_ht.c b/src/northbridge/amd/amdk8/incoherent_ht.c<br>index d65af96..ac513aa 100644<br>--- a/src/northbridge/amd/amdk8/incoherent_ht.c<br>+++ b/src/northbridge/amd/amdk8/incoherent_ht.c<br>@@ -624,7 +624,7 @@<br> busn = (reg & 0xff0000)>>16;<br> <br> dword = pci_read_config32(PCI_DEV(0, devpos, 0), regpos);<br>- dword &= ~(0xffff<<8);<br>+ dword &= ~(0xffff << 8);<br> dword |= (reg & 0xffff0000)>>8;<br> pci_write_config32(PCI_DEV(0, devpos,0), regpos , dword);<br> <br>@@ -677,16 +677,16 @@<br> sysinfo->sbbusn = 0;<br> sysinfo->nodes = nodes;<br> #endif<br>- tempreg = 3 | (0<<4) | (((reg>>8) & 3)<<8) | (0<<16)| (0x3f<<24);<br>+ tempreg = 3 | (0 << 4) | (((reg>>8) & 3)<<8) | (0 << 16)| (0x3f << 24);<br> pci_write_config32(PCI_DEV(0, 0x18, 1), 0xe0, tempreg);<br> <br> next_busn = 0x3f+1; /* 0 will be used ht chain with SB we need to keep SB in bus0 in auto stage*/<br> <br> #if CONFIG_K8_ALLOCATE_IO_RANGE<br> /* io range allocation */<br>- tempreg = 0 | (((reg>>8) & 0x3) << 4)| (0x3<<12); //limit<br>+ tempreg = 0 | (((reg>>8) & 0x3) << 4)| (0x3 << 12); //limit<br> pci_write_config32(PCI_DEV(0, 0x18, 1), 0xC4, tempreg);<br>- tempreg = 3 | (3<<4) | (0<<12); //base<br>+ tempreg = 3 | (3 << 4) | (0 << 12); //base<br> pci_write_config32(PCI_DEV(0, 0x18, 1), 0xC0, tempreg);<br> next_io_base = 0x3+0x1;<br> #endif<br>@@ -712,7 +712,7 @@<br> reg = pci_read_config32(dev, regpos);<br> if ((reg & 0x17) != 7) continue; /* it is not non conherent or not connected*/<br> print_linkn_in("NC node|link=", ((nodeid & 0xf)<<4)|(linkn & 0xf));<br>- tempreg = 3 | (nodeid <<4) | (linkn<<8);<br>+ tempreg = 3 | (nodeid <<4) | (linkn << 8);<br> /*compare (temp & 0xffff), with (PCI(0, 0x18, 1) 0xe0 to 0xec & 0xfffff) */<br> for (ht_c_num = 0;ht_c_num < 4; ht_c_num++) {<br> reg = pci_read_config32(PCI_DEV(0, 0x18, 1), 0xe0 + ht_c_num * 4);<br>@@ -724,15 +724,15 @@<br> /*update to 0xe0...*/<br> if ((reg & 0xf) == 3) continue; /*SbLink so don't touch it */<br> print_linkn_in("\tbusn=", next_busn);<br>- tempreg |= (next_busn<<16)|((next_busn+0x3f)<<24);<br>+ tempreg |= (next_busn << 16)|((next_busn+0x3f)<<24);<br> pci_write_config32(PCI_DEV(0, 0x18, 1), 0xe0 + ht_c_num * 4, tempreg);<br> next_busn+=0x3f+1;<br> <br> #if CONFIG_K8_ALLOCATE_IO_RANGE<br> /* io range allocation */<br>- tempreg = nodeid | (linkn<<4) | ((next_io_base+0x3)<<12); //limit<br>+ tempreg = nodeid | (linkn << 4) | ((next_io_base+0x3)<<12); //limit<br> pci_write_config32(PCI_DEV(0, 0x18, 1), 0xC4 + ht_c_num * 8, tempreg);<br>- tempreg = 3 /*| (3<<4)*/ | (next_io_base<<12); //base :ISA and VGA ?<br>+ tempreg = 3 /*| (3 << 4)*/ | (next_io_base << 12); //base :ISA and VGA ?<br> pci_write_config32(PCI_DEV(0, 0x18, 1), 0xC0 + ht_c_num * 8, tempreg);<br> next_io_base += 0x3+0x1;<br> #endif<br>diff --git a/src/northbridge/amd/amdk8/misc_control.c b/src/northbridge/amd/amdk8/misc_control.c<br>index 3cbeb04..9c43156 100644<br>--- a/src/northbridge/amd/amdk8/misc_control.c<br>+++ b/src/northbridge/amd/amdk8/misc_control.c<br>@@ -74,7 +74,7 @@<br> resource->flags |= IORESOURCE_STORED;<br> <br> /* Find the size of the GART aperture */<br>- gart_acr = (0<<6)|(0<<5)|(0<<4)|((resource->gran - 25) << 1)|(0<<0);<br>+ gart_acr = (0 << 6)|(0 << 5)|(0 << 4)|((resource->gran - 25) << 1)|(0 << 0);<br> <br> /* Get the base address */<br> gart_base = ((resource->base) >> 25) & 0x00007fff;<br>@@ -119,7 +119,7 @@<br> * This is needed for PC backwards compatibility.<br> */<br> cmd = pci_read_config32(dev, 0x44);<br>- cmd |= (1<<6) | (1<<25);<br>+ cmd |= (1 << 6) | (1 << 25);<br> pci_write_config32(dev, 0x44, cmd);<br> #if !CONFIG_K8_REV_F_SUPPORT<br> if (is_cpu_pre_c0()) {<br>@@ -128,11 +128,11 @@<br> * Disable CPU low power states C2, C1 and throttling<br> */<br> cmd = pci_read_config32(dev, 0x80);<br>- cmd &= ~(1<<0);<br>+ cmd &= ~(1 << 0);<br> pci_write_config32(dev, 0x80, cmd);<br> cmd = pci_read_config32(dev, 0x84);<br>- cmd &= ~(1<<24);<br>- cmd &= ~(1<<8);<br>+ cmd &= ~(1 << 24);<br>+ cmd &= ~(1 << 8);<br> pci_write_config32(dev, 0x84, cmd);<br> <br> /* Errata 66<br>@@ -140,15 +140,15 @@<br> */<br> cmd = pci_read_config32(dev, 0x70);<br> if ((cmd & (3 << 0)) != 2) {<br>- cmd &= ~(3<<0);<br>- cmd |= (2<<0);<br>+ cmd &= ~(3 << 0);<br>+ cmd |= (2 << 0);<br> pci_write_config32(dev, 0x70, cmd);<br> needs_reset = 1;<br> }<br> cmd = pci_read_config32(dev, 0x7c);<br> if ((cmd & (3 << 4)) != 0) {<br>- cmd &= ~(3<<4);<br>- cmd |= (0<<4);<br>+ cmd &= ~(3 << 4);<br>+ cmd |= (0 << 4);<br> pci_write_config32(dev, 0x7c, cmd);<br> needs_reset = 1;<br> }<br>diff --git a/src/northbridge/amd/amdk8/northbridge.c b/src/northbridge/amd/amdk8/northbridge.c<br>index c957af0..d7386c9 100644<br>--- a/src/northbridge/amd/amdk8/northbridge.c<br>+++ b/src/northbridge/amd/amdk8/northbridge.c<br>@@ -674,13 +674,13 @@<br> u32 base;<br> u32 hole;<br> base = f1_read_config32(0x40 + (i << 3));<br>- if ((base & ((1<<1)|(1<<0))) != ((1<<1)|(1<<0))) {<br>+ if ((base & ((1 << 1)|(1 << 0))) != ((1 << 1)|(1 << 0))) {<br> continue;<br> }<br> <br> hole = pci_read_config32(__f1_dev[i], 0xf0);<br> if (hole & 1) { // we find the hole<br>- mem_hole.hole_startk = (hole & (0xff<<24)) >> 10;<br>+ mem_hole.hole_startk = (hole & (0xff << 24)) >> 10;<br> mem_hole.node_id = i; // record the node No with hole<br> break; // only one hole<br> }<br>@@ -695,7 +695,7 @@<br> u32 base, limit;<br> unsigned base_k, limit_k;<br> base = f1_read_config32(0x40 + (i << 3));<br>- if ((base & ((1<<1)|(1<<0))) != ((1<<1)|(1<<0))) {<br>+ if ((base & ((1 << 1)|(1 << 0))) != ((1 << 1)|(1 << 0))) {<br> continue;<br> }<br> <br>@@ -735,7 +735,7 @@<br> for (i = 7; i > node_id; i--) {<br> <br> base = f1_read_config32(0x40 + (i << 3));<br>- if ((base & ((1<<1)|(1<<0))) != ((1<<1)|(1<<0))) {<br>+ if ((base & ((1 << 1)|(1 << 0))) != ((1 << 1)|(1 << 0))) {<br> continue;<br> }<br> limit = f1_read_config32(0x44 + (i << 3));<br>@@ -772,7 +772,7 @@<br> for (i = 7; i > node_id; i--) {<br> <br> base = f1_read_config32(0x40 + (i << 3));<br>- if ((base & ((1<<1)|(1<<0))) != ((1<<1)|(1<<0))) {<br>+ if ((base & ((1 << 1)|(1 << 0))) != ((1 << 1)|(1 << 0))) {<br> continue;<br> }<br> limit = f1_read_config32(0x44 + (i << 3));<br>@@ -789,7 +789,7 @@<br> //so need to change base reg instead, new basek will be 4*1024*1024<br> base &= 0x0000ffff;<br> base |= (4*1024*1024)<<2;<br>- f1_write_config32(0x40 + (node_id<<3), base);<br>+ f1_write_config32(0x40 + (node_id << 3), base);<br> }<br> else if (dev)<br> {<br>@@ -910,7 +910,7 @@<br> u32 base;<br> u32 basek;<br> base = f1_read_config32(0x40 + (i << 3));<br>- if ((base & ((1<<1)|(1<<0))) != ((1<<1)|(1<<0))) {<br>+ if ((base & ((1 << 1)|(1 << 0))) != ((1 << 1)|(1 << 0))) {<br> continue;<br> }<br> <br>@@ -936,7 +936,7 @@<br> u32 basek, limitk, sizek;<br> base = f1_read_config32(0x40 + (i << 3));<br> limit = f1_read_config32(0x44 + (i << 3));<br>- if ((base & ((1<<1)|(1<<0))) != ((1<<1)|(1<<0))) {<br>+ if ((base & ((1 << 1)|(1 << 0))) != ((1 << 1)|(1 << 0))) {<br> continue;<br> }<br> basek = (base & 0xffff0000) >> 2;<br>diff --git a/src/northbridge/amd/amdk8/pre_f.h b/src/northbridge/amd/amdk8/pre_f.h<br>index abc51b1..479ceb4 100644<br>--- a/src/northbridge/amd/amdk8/pre_f.h<br>+++ b/src/northbridge/amd/amdk8/pre_f.h<br>@@ -125,26 +125,26 @@<br> #define DTH_TWCL_MAX 2<br> <br> #define DRAM_CONFIG_LOW 0x90<br>-#define DCL_DLL_Disable (1<<0)<br>-#define DCL_D_DRV (1<<1)<br>-#define DCL_QFC_EN (1<<2)<br>-#define DCL_DisDqsHys (1<<3)<br>-#define DCL_Burst2Opt (1<<5)<br>-#define DCL_DramInit (1<<8)<br>-#define DCL_DualDIMMen (1<<9)<br>-#define DCL_DramEnable (1<<10)<br>-#define DCL_MemClrStatus (1<<11)<br>-#define DCL_ESR (1<<12)<br>-#define DCL_SRS (1<<13)<br>-#define DCL_128BitEn (1<<16)<br>-#define DCL_DimmEccEn (1<<17)<br>-#define DCL_UnBuffDimm (1<<18)<br>-#define DCL_32ByteEn (1<<19)<br>+#define DCL_DLL_Disable (1 << 0)<br>+#define DCL_D_DRV (1 << 1)<br>+#define DCL_QFC_EN (1 << 2)<br>+#define DCL_DisDqsHys (1 << 3)<br>+#define DCL_Burst2Opt (1 << 5)<br>+#define DCL_DramInit (1 << 8)<br>+#define DCL_DualDIMMen (1 << 9)<br>+#define DCL_DramEnable (1 << 10)<br>+#define DCL_MemClrStatus (1 << 11)<br>+#define DCL_ESR (1 << 12)<br>+#define DCL_SRS (1 << 13)<br>+#define DCL_128BitEn (1 << 16)<br>+#define DCL_DimmEccEn (1 << 17)<br>+#define DCL_UnBuffDimm (1 << 18)<br>+#define DCL_32ByteEn (1 << 19)<br> #define DCL_x4DIMM_SHIFT 20<br>-#define DCL_DisInRcvrs (1<<24)<br>+#define DCL_DisInRcvrs (1 << 24)<br> #define DCL_BypMax_SHIFT 25<br>-#define DCL_En2T (1<<28)<br>-#define DCL_UpperCSMap (1<<29)<br>+#define DCL_En2T (1 << 28)<br>+#define DCL_UpperCSMap (1 << 29)<br> <br> #define DRAM_CONFIG_HIGH 0x94<br> #define DCH_ASYNC_LAT_SHIFT 0<br>@@ -154,9 +154,9 @@<br> #define DCH_ASYNC_LAT_MAX 15<br> #define DCH_RDPREAMBLE_SHIFT 8<br> #define DCH_RDPREAMBLE_MASK 0xf<br>-#define DCH_RDPREAMBLE_BASE ((2<<1)+0) /* 2.0 ns */<br>-#define DCH_RDPREAMBLE_MIN ((2<<1)+0) /* 2.0 ns */<br>-#define DCH_RDPREAMBLE_MAX ((9<<1)+1) /* 9.5 ns */<br>+#define DCH_RDPREAMBLE_BASE ((2 << 1)+0) /* 2.0 ns */<br>+#define DCH_RDPREAMBLE_MIN ((2 << 1)+0) /* 2.0 ns */<br>+#define DCH_RDPREAMBLE_MAX ((9 << 1)+1) /* 9.5 ns */<br> #define DCH_IDLE_LIMIT_SHIFT 16<br> #define DCH_IDLE_LIMIT_MASK 0x7<br> #define DCH_IDLE_LIMIT_0 0<br>diff --git a/src/northbridge/amd/amdk8/raminit.c b/src/northbridge/amd/amdk8/raminit.c<br>index 43229ea..832a04f 100644<br>--- a/src/northbridge/amd/amdk8/raminit.c<br>+++ b/src/northbridge/amd/amdk8/raminit.c<br>@@ -829,7 +829,7 @@<br> limit |= (0 << 8) | (node_id << 0);<br> base = (base_k << 2);<br> base &= 0xffff0000;<br>- base |= (0 << 8) | (1<<1) | (1<<0);<br>+ base |= (0 << 8) | (1 << 1) | (1 << 0);<br> <br> limit_reg = 0x44 + index;<br> base_reg = 0x40 + index;<br>@@ -1320,7 +1320,7 @@<br> [NBCAP_MEMCLK_133MHZ] = {<br> .name = "133MHz",<br> .cycle_time = 0x75,<br>- .divisor = (7<<1)+1,<br>+ .divisor = (7 << 1)+1,<br> .tRC = 0x41,<br> .tRFC = 0x4B,<br> .dch_memclk = DCH_MEMCLK_133MHZ << DCH_MEMCLK_SHIFT,<br>@@ -1334,7 +1334,7 @@<br> [NBCAP_MEMCLK_166MHZ] = {<br> .name = "166MHz",<br> .cycle_time = 0x60,<br>- .divisor = (6<<1),<br>+ .divisor = (6 << 1),<br> .tRC = 0x3C,<br> .tRFC = 0x48,<br> .dch_memclk = DCH_MEMCLK_166MHZ << DCH_MEMCLK_SHIFT,<br>@@ -1348,7 +1348,7 @@<br> [NBCAP_MEMCLK_200MHZ] = {<br> .name = "200MHz",<br> .cycle_time = 0x50,<br>- .divisor = (5<<1),<br>+ .divisor = (5 << 1),<br> .tRC = 0x37,<br> .tRFC = 0x46,<br> .dch_memclk = DCH_MEMCLK_200MHZ << DCH_MEMCLK_SHIFT,<br>@@ -2230,7 +2230,7 @@<br> <br> for (ii = controllers - 1; ii > i; ii--) {<br> base = pci_read_config32(ctrl[0].f1, 0x40 + (ii << 3));<br>- if ((base & ((1<<1)|(1<<0))) != ((1<<1)|(1<<0))) {<br>+ if ((base & ((1 << 1)|(1 << 0))) != ((1 << 1)|(1 << 0))) {<br> continue;<br> }<br> limit = pci_read_config32(ctrl[0].f1, 0x44 + (ii << 3));<br>@@ -2252,7 +2252,7 @@<br> base &= 0x0000ffff;<br> base |= (4*1024*1024)<<2;<br> for (j = 0; j < controllers; j++) {<br>- pci_write_config32(ctrl[j].f1, 0x40 + (i<<3), base);<br>+ pci_write_config32(ctrl[j].f1, 0x40 + (i << 3), base);<br> }<br> }<br> else {<br>@@ -2287,7 +2287,7 @@<br> uint32_t base;<br> unsigned base_k;<br> base = pci_read_config32(ctrl[0].f1, 0x40 + (i << 3));<br>- if ((base & ((1<<1)|(1<<0))) != ((1<<1)|(1<<0))) {<br>+ if ((base & ((1 << 1)|(1 << 0))) != ((1 << 1)|(1 << 0))) {<br> continue;<br> }<br> base_k = (base & 0xffff0000) >> 2;<br>@@ -2308,7 +2308,7 @@<br> uint32_t base, limit;<br> unsigned base_k, limit_k;<br> base = pci_read_config32(ctrl[0].f1, 0x40 + (i << 3));<br>- if ((base & ((1<<1)|(1<<0))) != ((1<<1)|(1<<0))) {<br>+ if ((base & ((1 << 1)|(1 << 0))) != ((1 << 1)|(1 << 0))) {<br> continue;<br> }<br> limit = pci_read_config32(ctrl[0].f1, 0x44 + (i << 3));<br>diff --git a/src/northbridge/amd/amdk8/raminit_f.c b/src/northbridge/amd/amdk8/raminit_f.c<br>index a979896..c508817 100644<br>--- a/src/northbridge/amd/amdk8/raminit_f.c<br>+++ b/src/northbridge/amd/amdk8/raminit_f.c<br>@@ -253,7 +253,7 @@<br> * 1 = DQS receiver enable training mode<br> * [31:19] reserved<br> */<br>- PCI_ADDR(0, 0x18, 2, 0x78), 0xfff80000, (6<<4)|(6<<0),<br>+ PCI_ADDR(0, 0x18, 2, 0x78), 0xfff80000, (6 << 4)|(6 << 0),<br> <br> /* DRAM Initialization Register<br> * F2:0x7C<br>@@ -1005,7 +1005,7 @@<br> limit |= (0 << 8) | (node_id << 0);<br> base = (base_k << 2);<br> base &= 0xffff0000;<br>- base |= (0 << 8) | (1<<1) | (1<<0);<br>+ base |= (0 << 8) | (1 << 1) | (1 << 0);<br> <br> limit_reg = 0x44 + index;<br> base_reg = 0x40 + index;<br>@@ -1329,7 +1329,7 @@<br> value &= 0x3f;<br> if ((value == SPD_DIMM_TYPE_RDIMM) || (value == SPD_DIMM_TYPE_mRDIMM)) {<br> //check SPD_MOD_ATTRIB to verify it is SPD_MOD_ATTRIB_REGADC (0x11)?<br>- registered |= (1<<i);<br>+ registered |= (1 << i);<br> }<br> }<br> <br>@@ -2236,11 +2236,11 @@<br> }<br> <br> if (meminfo->sz[i].rank == 1) {<br>- mask_single_rank |= 1<<i;<br>+ mask_single_rank |= 1 << i;<br> }<br> <br> if (meminfo->sz[i].col == 10) {<br>- mask_page_1k |= 1<<i;<br>+ mask_page_1k |= 1 << i;<br> }<br> <br> <br>@@ -2251,14 +2251,14 @@<br> #endif<br> <br> if (value == 4) {<br>- mask_x4 |= (1<<i);<br>+ mask_x4 |= (1 << i);<br> #if CONFIG_QRANK_DIMM_SUPPORT<br> if (rank == 4) {<br> mask_x4 |= 1<<(i+2);<br> }<br> #endif<br> } else if (value == 16) {<br>- mask_x16 |= (1<<i);<br>+ mask_x16 |= (1 << i);<br> #if CONFIG_QRANK_DIMM_SUPPORT<br> if (rank == 4) {<br> mask_x16 |= 1<<(i+2);<br>@@ -2283,7 +2283,7 @@<br> {<br> uint32_t dcl;<br> dcl = pci_read_config32(ctrl->f2, DRAM_CONFIG_LOW);<br>- dcl &= ~(DCL_X4Dimm_MASK<<DCL_X4Dimm_SHIFT);<br>+ dcl &= ~(DCL_X4Dimm_MASK << DCL_X4Dimm_SHIFT);<br> dcl |= ((meminfo->x4_mask) & 0xf) << (DCL_X4Dimm_SHIFT);<br> pci_write_config32(ctrl->f2, DRAM_CONFIG_LOW, dcl);<br> }<br>@@ -2325,7 +2325,7 @@<br> #endif<br> <br> dcl = pci_read_config32(ctrl->f2, DRAM_CONFIG_LOW);<br>- dcl &= ~(DCL_DramTerm_MASK<<DCL_DramTerm_SHIFT);<br>+ dcl &= ~(DCL_DramTerm_MASK << DCL_DramTerm_SHIFT);<br> dcl |= (odt & DCL_DramTerm_MASK) << (DCL_DramTerm_SHIFT);<br> pci_write_config32(ctrl->f2, DRAM_CONFIG_LOW, dcl);<br> }<br>@@ -2482,7 +2482,7 @@<br> <br> dch = pci_read_config32(ctrl->f2, DRAM_CONFIG_HIGH);<br> <br>- dch |= (1<<20);<br>+ dch |= (1 << 20);<br> <br> pci_write_config32(ctrl->f2, DRAM_CONFIG_HIGH, dch);<br> }<br>@@ -2883,7 +2883,7 @@<br> <br> for (ii = controllers - 1; ii > i; ii--) {<br> base = pci_read_config32(ctrl[0].f1, 0x40 + (ii << 3));<br>- if ((base & ((1<<1)|(1<<0))) != ((1<<1)|(1<<0))) {<br>+ if ((base & ((1 << 1)|(1 << 0))) != ((1 << 1)|(1 << 0))) {<br> continue;<br> }<br> limit = pci_read_config32(ctrl[0].f1, 0x44 + (ii << 3));<br>@@ -2908,7 +2908,7 @@<br> base &= 0x0000ffff;<br> base |= (4*1024*1024)<<2;<br> for (j = 0; j < controllers; j++) {<br>- pci_write_config32(ctrl[j].f1, 0x40 + (i<<3), base);<br>+ pci_write_config32(ctrl[j].f1, 0x40 + (i << 3), base);<br> }<br> } else {<br> hoist = /* hole start address */<br>@@ -2940,7 +2940,7 @@<br> uint32_t base;<br> unsigned base_k;<br> base = pci_read_config32(ctrl[0].f1, 0x40 + (i << 3));<br>- if ((base & ((1<<1)|(1<<0))) != ((1<<1)|(1<<0))) {<br>+ if ((base & ((1 << 1)|(1 << 0))) != ((1 << 1)|(1 << 0))) {<br> continue;<br> }<br> base_k = (base & 0xffff0000) >> 2;<br>@@ -3129,11 +3129,11 @@<br> msr_t msr;<br> //[1M, TOM)<br> msr = rdmsr(TOP_MEM);<br>- sysinfo->tom_k = ((msr.hi<<24) | (msr.lo>>8))>>2;<br>+ sysinfo->tom_k = ((msr.hi << 24) | (msr.lo>>8))>>2;<br> <br> //[4G, TOM2)<br> msr = rdmsr(TOP_MEM2);<br>- sysinfo->tom2_k = ((msr.hi<<24)| (msr.lo>>8))>>2;<br>+ sysinfo->tom2_k = ((msr.hi << 24)| (msr.lo>>8))>>2;<br> }<br> <br> for (i = 0; i < controllers; i++) {<br>diff --git a/src/northbridge/amd/amdk8/raminit_f_dqs.c b/src/northbridge/amd/amdk8/raminit_f_dqs.c<br>index c470b25..dc91598 100644<br>--- a/src/northbridge/amd/amdk8/raminit_f_dqs.c<br>+++ b/src/northbridge/amd/amdk8/raminit_f_dqs.c<br>@@ -122,7 +122,7 @@<br> {<br> unsigned long cr4;<br> cr4 = read_cr4();<br>- cr4 |= (1<<9);<br>+ cr4 |= (1 << 9);<br> write_cr4(cr4);<br> }<br> <br>@@ -130,7 +130,7 @@<br> {<br> unsigned long cr4;<br> cr4 = read_cr4();<br>- cr4 &= ~(1<<9);<br>+ cr4 &= ~(1 << 9);<br> write_cr4(cr4);<br> }<br> <br>@@ -139,7 +139,7 @@<br> msr_t msr;<br> <br> msr = rdmsr(0xc0010015);<br>- msr.lo |= (1<<17);<br>+ msr.lo |= (1 << 17);<br> <br> wrmsr(0xc0010015, msr);<br> <br>@@ -149,7 +149,7 @@<br> msr_t msr;<br> <br> msr = rdmsr(0xc0010015);<br>- msr.lo &= ~(1<<17);<br>+ msr.lo &= ~(1 << 17);<br> <br> wrmsr(0xc0010015, msr);<br> <br>@@ -1713,7 +1713,7 @@<br> if (tom2_k) {<br> //enable tom2 and type<br> msr = rdmsr(SYSCFG_MSR);<br>- msr.lo |= (1<<21) | (1<<22); //MtrrTom2En and Tom2ForceMemTypeWB<br>+ msr.lo |= (1 << 21) | (1 << 22); //MtrrTom2En and Tom2ForceMemTypeWB<br> wrmsr(SYSCFG_MSR, msr);<br> }<br> <br>@@ -1744,7 +1744,7 @@<br> if (tom2_k) {<br> //enable tom2 and type<br> msr = rdmsr(SYSCFG_MSR);<br>- msr.lo &= ~((1<<21) | (1<<22)); //MtrrTom2En and Tom2ForceMemTypeWB<br>+ msr.lo &= ~((1 << 21) | (1 << 22)); //MtrrTom2En and Tom2ForceMemTypeWB<br> wrmsr(SYSCFG_MSR, msr);<br> }<br> }<br>diff --git a/src/northbridge/amd/amdmct/mct/mct_d.c b/src/northbridge/amd/amdmct/mct/mct_d.c<br>index 8bee434..4c1c96f 100644<br>--- a/src/northbridge/amd/amdmct/mct/mct_d.c<br>+++ b/src/northbridge/amd/amdmct/mct/mct_d.c<br>@@ -475,7 +475,7 @@<br> for (Channel = 0; Channel < 2; Channel++) {<br> reg = 0x78 + Channel * 0x100;<br> val = Get_NB32(dev, reg);<br>- val &= ~(0x3ff<<22);<br>+ val &= ~(0x3ff << 22);<br> val |= ((u32) pDCTstat->CH_MaxRdLat[Channel] << 22);<br> val &= ~(1 << DqsRcvEnTrain);<br> Set_NB32(dev, reg, val); /* program MaxRdLatency to correspond with current delay*/<br>@@ -830,7 +830,7 @@<br> }<br> if (stopDCTflag) {<br> u32 reg_off = dct * 0x100;<br>- val = 1<<DisDramInterface;<br>+ val = 1 << DisDramInterface;<br> Set_NB32(pDCTstat->dev_dct, reg_off+0x94, val);<br> /*To maximize power savings when DisDramInterface = 1b,<br> all of the MemClkDis bits should also be set.*/<br>@@ -1048,7 +1048,7 @@<br> <br> val = mctRead_SPD(smbaddr, SPD_TRC);<br> if ((val == 0) || (val == 0xFF)) {<br>- pDCTstat->ErrStatus |= 1<<SB_NoTrcTrfc;<br>+ pDCTstat->ErrStatus |= 1 << SB_NoTrcTrfc;<br> pDCTstat->ErrCode = SC_VarianceErr;<br> val = Get_DefTrc_k_D(pDCTstat->Speed);<br> } else {<br>@@ -1532,7 +1532,7 @@<br> DramControl = Get_NB32 (dev, 0x78 + reg_off); /* Dram Control*/<br> <br> if (mctGet_NVbits(NV_CLKHZAltVidC3))<br>- DramControl |= 1<<16;<br>+ DramControl |= 1 << 16;<br> <br> // FIXME: Add support(skip) for Ax and Cx versions<br> DramControl |= 5; /* RdPtrInit */<br>@@ -1952,7 +1952,7 @@<br> if (pMCTstat->GStatus & 1 << GSB_EnDIMMSpareNW) {<br> word = pDCTstat->CSPresent;<br> val = bsf(word);<br>- word &= ~(1<<val);<br>+ word &= ~(1 << val);<br> if (word)<br> /* Make sure at least two chip-selects are available */<br> _DSpareEn = 1;<br>@@ -2054,13 +2054,13 @@<br> <br> static u16 Get_40Tk_D(u8 k)<br> {<br>- return Tab_40T_k[k]; /* FIXME: k or k<<1 ?*/<br>+ return Tab_40T_k[k]; /* FIXME: k or k << 1 ?*/<br> }<br> <br> <br> static u16 Get_Fk_D(u8 k)<br> {<br>- return Table_F_k[k]; /* FIXME: k or k<<1 ? */<br>+ return Table_F_k[k]; /* FIXME: k or k << 1 ? */<br> }<br> <br> <br>@@ -2270,7 +2270,7 @@<br> if (byte == 2)<br> bytex <<= 1; /*double Addr bus load value for dual rank DIMMs*/<br> <br>- j = i & (1<<0);<br>+ j = i & (1 << 0);<br> pDCTstat->DATAload[j] += byte; /*number of ranks on DATA bus*/<br> pDCTstat->MAload[j] += bytex; /*number of devices on CMD/ADDR bus*/<br> pDCTstat->MAdimms[j]++; /*number of DIMMs on A bus */<br>@@ -3276,7 +3276,7 @@<br> /* Clear Legacy BIOS Mode bit */<br> reg = 0x94;<br> val = Get_NB32(dev, reg);<br>- val &= ~(1<<LegacyBiosMode);<br>+ val &= ~(1 << LegacyBiosMode);<br> Set_NB32(dev, reg, val);<br> }<br> <br>@@ -3846,11 +3846,11 @@<br> <br> addr = HWCR;<br> _RDMSR(addr, &lo, &hi);<br>- if (lo & (1<<17)) { /* save the old value */<br>+ if (lo & (1 << 17)) { /* save the old value */<br> wrap32dis = 1;<br> }<br>- lo |= (1<<17); /* HWCR.wrap32dis */<br>- lo &= ~(1<<15); /* SSEDIS */<br>+ lo |= (1 << 17); /* HWCR.wrap32dis */<br>+ lo &= ~(1 << 15); /* SSEDIS */<br> /* Setting wrap32dis allows 64-bit memory references in 32bit mode */<br> _WRMSR(addr, lo, hi);<br> <br>@@ -3878,7 +3878,7 @@<br> if (!wrap32dis) {<br> addr = HWCR;<br> _RDMSR(addr, &lo, &hi);<br>- lo &= ~(1<<17); /* restore HWCR.wrap32dis */<br>+ lo &= ~(1 << 17); /* restore HWCR.wrap32dis */<br> _WRMSR(addr, lo, hi);<br> }<br> }<br>diff --git a/src/northbridge/amd/amdmct/mct/mct_d_gcc.c b/src/northbridge/amd/amdmct/mct/mct_d_gcc.c<br>index 59618f6..99b0cbc 100644<br>--- a/src/northbridge/amd/amdmct/mct/mct_d_gcc.c<br>+++ b/src/northbridge/amd/amdmct/mct/mct_d_gcc.c<br>@@ -63,7 +63,7 @@<br> u32 ret = 0;<br> <br> for (i = 31; i > 0; i--) {<br>- if (x & (1<<i)) {<br>+ if (x & (1 << i)) {<br> ret = i;<br> break;<br> }<br>@@ -80,7 +80,7 @@<br> u32 ret = 32;<br> <br> for (i = 0; i < 32; i++) {<br>- if (x & (1<<i)) {<br>+ if (x & (1 << i)) {<br> ret = i;<br> break;<br> }<br>@@ -107,7 +107,7 @@<br> "outb %%al, $0xed\n\t" /* _EXECFENCE */<br> "clflush %%fs:(%0)\n\t"<br> "mfence\n\t"<br>- ::"a" (addr_hi<<8)<br>+ ::"a" (addr_hi << 8)<br> );<br> }<br> <br>@@ -285,7 +285,7 @@<br> "movl %%fs:-64(%%esi), %%eax\n\t" //+1<br> "movl %%fs:(%%esi), %%eax\n\t" //+2<br> "mfence\n\t"<br>- :: "a"(0), "S"((addr<<8)+128)<br>+ :: "a"(0), "S"((addr << 8)+128)<br> );<br> <br> }<br>@@ -304,7 +304,7 @@<br> "loop 1b\n\t"<br> "mfence\n\t"<br> <br>- :: "a" (addr<<8), "d" (16), "c" (3 * 4), "b"(buf)<br>+ :: "a" (addr << 8), "d" (16), "c" (3 * 4), "b"(buf)<br> );<br> }<br> <br>@@ -323,7 +323,7 @@<br> "clflush %%fs:(%%esi)\n\t" //+2<br> "mfence\n\t"<br> <br>- :: "S"((addr<<8)+128)<br>+ :: "S"((addr << 8)+128)<br> );<br> }<br> <br>diff --git a/src/northbridge/amd/amdmct/mct/mctdqs_d.c b/src/northbridge/amd/amdmct/mct/mctdqs_d.c<br>index 7140007..ecd8802 100644<br>--- a/src/northbridge/amd/amdmct/mct/mctdqs_d.c<br>+++ b/src/northbridge/amd/amdmct/mct/mctdqs_d.c<br>@@ -280,18 +280,18 @@<br> <br> print_debug_dqs("\nTrainDQSRdWrPos: Node_ID ", pDCTstat->Node_ID, 0);<br> cr4 = read_cr4();<br>- if (cr4 & (1<<9)) {<br>+ if (cr4 & (1 << 9)) {<br> _SSE2 = 1;<br> }<br>- cr4 |= (1<<9); /* OSFXSR enable SSE2 */<br>+ cr4 |= (1 << 9); /* OSFXSR enable SSE2 */<br> write_cr4(cr4);<br> <br> addr = HWCR;<br> _RDMSR(addr, &lo, &hi);<br>- if (lo & (1<<17)) {<br>+ if (lo & (1 << 17)) {<br> _Wrap32Dis = 1;<br> }<br>- lo |= (1<<17); /* HWCR.wrap32dis */<br>+ lo |= (1 << 17); /* HWCR.wrap32dis */<br> _WRMSR(addr, lo, hi); /* allow 64-bit memory references in real mode */<br> <br> /* Disable ECC correction of reads on the dram bus. */<br>@@ -370,12 +370,12 @@<br> if (!_Wrap32Dis) {<br> addr = HWCR;<br> _RDMSR(addr, &lo, &hi);<br>- lo &= ~(1<<17); /* restore HWCR.wrap32dis */<br>+ lo &= ~(1 << 17); /* restore HWCR.wrap32dis */<br> _WRMSR(addr, lo, hi);<br> }<br> if (!_SSE2) {<br> cr4 = read_cr4();<br>- cr4 &= ~(1<<9); /* restore cr4.OSFXSR */<br>+ cr4 &= ~(1 << 9); /* restore cr4.OSFXSR */<br> write_cr4(cr4);<br> }<br> <br>@@ -602,7 +602,7 @@<br> */<br> <br> /* FindDQSDatDimmVal_D is not required since we use an array */<br>- if (pDCTstat->Status & (1<<SB_Over400MHz))<br>+ if (pDCTstat->Status & (1 << SB_Over400MHz))<br> dn = ChipSel >> 1; /*if odd or even logical DIMM */<br> <br> pDCTstat->DQSDelay =<br>@@ -928,17 +928,17 @@<br> dev = pDCTstat->dev_dct;<br> reg = 0x90;<br> val = Get_NB32(dev, reg);<br>- if (val & (1<<DimmEcEn)) {<br>+ if (val & (1 << DimmEcEn)) {<br> _DisableDramECC |= 0x01;<br>- val &= ~(1<<DimmEcEn);<br>+ val &= ~(1 << DimmEcEn);<br> Set_NB32(dev, reg, val);<br> }<br> if (!pDCTstat->GangedMode) {<br> reg = 0x190;<br> val = Get_NB32(dev, reg);<br>- if (val & (1<<DimmEcEn)) {<br>+ if (val & (1 << DimmEcEn)) {<br> _DisableDramECC |= 0x02;<br>- val &= ~(1<<DimmEcEn);<br>+ val &= ~(1 << DimmEcEn);<br> Set_NB32(dev, reg, val);<br> }<br> }<br>@@ -962,13 +962,13 @@<br> if ((_DisableDramECC & 0x01) == 0x01) {<br> reg = 0x90;<br> val = Get_NB32(dev, reg);<br>- val |= (1<<DimmEcEn);<br>+ val |= (1 << DimmEcEn);<br> Set_NB32(dev, reg, val);<br> }<br> if ((_DisableDramECC & 0x02) == 0x02) {<br> reg = 0x190;<br> val = Get_NB32(dev, reg);<br>- val |= (1<<DimmEcEn);<br>+ val |= (1 << DimmEcEn);<br> Set_NB32(dev, reg, val);<br> }<br> }<br>diff --git a/src/northbridge/amd/amdmct/mct/mctecc_d.c b/src/northbridge/amd/amdmct/mct/mctecc_d.c<br>index 9b22c84..2dea737 100644<br>--- a/src/northbridge/amd/amdmct/mct/mctecc_d.c<br>+++ b/src/northbridge/amd/amdmct/mct/mctecc_d.c<br>@@ -181,7 +181,7 @@<br> dev = pDCTstat->dev_nbmisc;<br> val = curBase << 8;<br> if (OB_ECCRedir) {<br>- val |= (1<<0); /* enable redirection */<br>+ val |= (1 << 0); /* enable redirection */<br> }<br> Set_NB32(dev, 0x5C, val); /* Dram Scrub Addr Low */<br> val = curBase >> 24;<br>diff --git a/src/northbridge/amd/amdmct/mct/mctgr.c b/src/northbridge/amd/amdmct/mct/mctgr.c<br>index 41a479b..fdd508b 100644<br>--- a/src/northbridge/amd/amdmct/mct/mctgr.c<br>+++ b/src/northbridge/amd/amdmct/mct/mctgr.c<br>@@ -33,11 +33,11 @@<br> NewDramTimingLo = Get_NB32(dev, 0x88 + reg_off);<br> if (mctGet_NVbits(NV_AllMemClks) == 0) {<br> /*Special Jedec SPD diagnostic bit - "enable all clocks"*/<br>- if (!(pDCTstat->Status & (1<<SB_DiagClks))) {<br>+ if (!(pDCTstat->Status & (1 << SB_DiagClks))) {<br> for (i = 0; i < MAX_DIMMS_SUPPORTED; i++) {<br> val = Tab_GRCLKDis[i];<br> if (val < 8) {<br>- if (!(pDCTstat->DIMMValidDCT[dct] & (1<<val))) {<br>+ if (!(pDCTstat->DIMMValidDCT[dct] & (1 << val))) {<br> /* disable memclk */<br> NewDramTimingLo |= (1<<(i+1));<br> }<br>@@ -45,9 +45,9 @@<br> }<br> }<br> }<br>- DramTimingLo &= ~(0xff<<24);<br>- DramTimingLo |= NewDramTimingLo & (0xff<<24);<br>- DramTimingLo &= (0x4d<<24); /* FIXME - enable all MemClks for now */<br>+ DramTimingLo &= ~(0xff << 24);<br>+ DramTimingLo |= NewDramTimingLo & (0xff << 24);<br>+ DramTimingLo &= (0x4d << 24); /* FIXME - enable all MemClks for now */<br> <br> return DramTimingLo;<br> }<br>@@ -77,7 +77,7 @@<br> base += HoleSize;<br> base >>= 27 - 8;<br> val = Get_NB32(dev, 0x110);<br>- val &= ~(0xfff<<11);<br>+ val &= ~(0xfff << 11);<br> val |= (base & 0xfff)<<11;<br> Set_NB32(dev, 0x110, val);<br> }<br>diff --git a/src/northbridge/amd/amdmct/mct/mcthdi.c b/src/northbridge/amd/amdmct/mct/mcthdi.c<br>index b67282e..1af202e 100644<br>--- a/src/northbridge/amd/amdmct/mct/mcthdi.c<br>+++ b/src/northbridge/amd/amdmct/mct/mcthdi.c<br>@@ -25,6 +25,6 @@<br> /*flag for selecting HW/SW DRAM Init HW DRAM Init */<br> reg = 0x90 + 0x100 * dct; /*DRAM Configuration Low */<br> val = Get_NB32(dev, reg);<br>- val |= (1<<InitDram);<br>+ val |= (1 << InitDram);<br> Set_NB32(dev, reg, val);<br> }<br>diff --git a/src/northbridge/amd/amdmct/mct/mctmtr_d.c b/src/northbridge/amd/amdmct/mct/mctmtr_d.c<br>index deb0f8a..f2d355e 100644<br>--- a/src/northbridge/amd/amdmct/mct/mctmtr_d.c<br>+++ b/src/northbridge/amd/amdmct/mct/mctmtr_d.c<br>@@ -91,15 +91,15 @@<br> /* Limit */<br> /* MtrrAddr */<br> if (addr == -1) /* ran out of MTRRs?*/<br>- pMCTstat->GStatus |= 1<<GSB_MTRRshort;<br>+ pMCTstat->GStatus |= 1 << GSB_MTRRshort;<br> <br>- pMCTstat->Sub4GCacheTop = Cache32bTOP<<8;<br>+ pMCTstat->Sub4GCacheTop = Cache32bTOP << 8;<br> <br> /*======================================================================<br> Set TOP_MEM and TOM2 CPU registers<br> ======================================================================*/<br> addr = TOP_MEM;<br>- lo = Bottom32bIO<<8;<br>+ lo = Bottom32bIO << 8;<br> hi = Bottom32bIO>>24;<br> _WRMSR(addr, lo, hi);<br> print_tx("\t CPUMemTyping: Bottom32bIO:", Bottom32bIO);<br>@@ -115,11 +115,11 @@<br> addr = 0xC0010010; /* SYS_CFG */<br> _RDMSR(addr, &lo, &hi);<br> if (Bottom40bIO) {<br>- lo |= (1<<21); /* MtrrTom2En = 1 */<br>- lo |= (1<<22); /* Tom2ForceMemTypeWB */<br>+ lo |= (1 << 21); /* MtrrTom2En = 1 */<br>+ lo |= (1 << 22); /* Tom2ForceMemTypeWB */<br> } else {<br>- lo &= ~(1<<21); /* MtrrTom2En = 0 */<br>- lo &= ~(1<<22); /* Tom2ForceMemTypeWB */<br>+ lo &= ~(1 << 21); /* MtrrTom2En = 0 */<br>+ lo &= ~(1 << 22); /* Tom2ForceMemTypeWB */<br> }<br> _WRMSR(addr, lo, hi);<br> }<br>@@ -173,7 +173,7 @@<br> valx += curBase;<br> if ((curBase == 0) || (*pLimit < valx)) {<br> /* flop direction to "descending" code path*/<br>- valx = 1<<bsr(*pLimit - curBase);<br>+ valx = 1 << bsr(*pLimit - curBase);<br> curSize = valx;<br> valx += curBase;<br> }<br>@@ -249,6 +249,6 @@<br> print_tx("\t UMAMemTyping_D: Cache32bTOP:", Cache32bTOP);<br> SetMTRRrangeWB_D(0, &Cache32bTOP, &addr);<br> if (addr == -1) /* ran out of MTRRs?*/<br>- pMCTstat->GStatus |= 1<<GSB_MTRRshort;<br>+ pMCTstat->GStatus |= 1 << GSB_MTRRshort;<br> }<br> }<br>diff --git a/src/northbridge/amd/amdmct/mct/mctpro_d.c b/src/northbridge/amd/amdmct/mct/mctpro_d.c<br>index 0acb6f4..16154d5 100644<br>--- a/src/northbridge/amd/amdmct/mct/mctpro_d.c<br>+++ b/src/northbridge/amd/amdmct/mct/mctpro_d.c<br>@@ -44,8 +44,8 @@<br> uint64_t tmp;<br> tmp = pDCTstat->LogicalCPUID;<br> if ((tmp == AMD_DR_A0A) || (tmp == AMD_DR_A1B) || (tmp == AMD_DR_A2)) {<br>- if (!(val & (3<<12)))<br>- val |= 1<<12;<br>+ if (!(val & (3 << 12)))<br>+ val |= 1 << 12;<br> }<br> return val;<br> }<br>@@ -66,9 +66,9 @@<br> reg_off = 0x100 * dct;<br> reg = 0x90 + reg_off; /* Dram Configuration Lo */<br> val = Get_NB32(dev, reg);<br>- val |= 1<<ForceAutoPchg;<br>+ val |= 1 << ForceAutoPchg;<br> if (!pDCTstat->GangedMode)<br>- val |= 1<<BurstLength32;<br>+ val |= 1 << BurstLength32;<br> Set_NB32(dev, reg, val);<br> <br> reg = 0x88 + reg_off; /* cx = Dram Timing Lo */<br>@@ -112,7 +112,7 @@<br> dev = pDCTstat->dev_dct;<br> reg = 0x11c;<br> val = Get_NB32(dev, reg);<br>- val &= ~(1<<PrefDramTrainMode);<br>+ val &= ~(1 << PrefDramTrainMode);<br> Set_NB32(dev, reg, val);<br> }<br> }<br>@@ -212,7 +212,7 @@<br> index_reg = 0x98 + 0x100 * dct;<br> index = 0x0D004201;<br> val = Get_NB32_index_wait(dev, index_reg, index);<br>- value &= ~(1<<27);<br>+ value &= ~(1 << 27);<br> value |= ((val >> 10) & 1) << 27;<br> }<br> return value;<br>diff --git a/src/northbridge/amd/amdmct/mct/mctsrc.c b/src/northbridge/amd/amdmct/mct/mctsrc.c<br>index 60857f4..f46c989 100644<br>--- a/src/northbridge/amd/amdmct/mct/mctsrc.c<br>+++ b/src/northbridge/amd/amdmct/mct/mctsrc.c<br>@@ -445,12 +445,12 @@<br> if (!_Wrap32Dis) {<br> msr = HWCR;<br> _RDMSR(msr, &lo, &hi);<br>- lo &= ~(1<<17); /* restore HWCR.wrap32dis */<br>+ lo &= ~(1 << 17); /* restore HWCR.wrap32dis */<br> _WRMSR(msr, lo, hi);<br> }<br> if (!_SSE2) {<br> cr4 = read_cr4();<br>- cr4 &= ~(1<<9); /* restore cr4.OSFXSR */<br>+ cr4 &= ~(1 << 9); /* restore cr4.OSFXSR */<br> write_cr4(cr4);<br> }<br> <br>@@ -771,7 +771,7 @@<br> SetUpperFSbase(addr);<br> addr <<= 8;<br> <br>- if ((pDCTstat->Status & (1<<SB_128bitmode)) && channel) {<br>+ if ((pDCTstat->Status & (1 << SB_128bitmode)) && channel) {<br> addr += 8; /* second channel */<br> test_buf += 8;<br> }<br>@@ -782,9 +782,9 @@<br> print_debug_dqs_pair("\t\t\t\t\t\t\t\t ", test_buf[i], " | ", value, 4);<br> <br> if (value == test_buf[i]) {<br>- pDCTstat->DqsRcvEn_Pass |= (1<<i);<br>+ pDCTstat->DqsRcvEn_Pass |= (1 << i);<br> } else {<br>- pDCTstat->DqsRcvEn_Pass &= ~(1<<i);<br>+ pDCTstat->DqsRcvEn_Pass &= ~(1 << i);<br> }<br> }<br> <br>diff --git a/src/northbridge/amd/amdmct/mct/mctsrc2p.c b/src/northbridge/amd/amdmct/mct/mctsrc2p.c<br>index ab278e9..562954f 100644<br>--- a/src/northbridge/amd/amdmct/mct/mctsrc2p.c<br>+++ b/src/northbridge/amd/amdmct/mct/mctsrc2p.c<br>@@ -112,7 +112,7 @@<br> }<br> }<br> if (!valid) {<br>- pDCTstat->ErrStatus |= 1<<SB_NORCVREN;<br>+ pDCTstat->ErrStatus |= 1 << SB_NORCVREN;<br> } else {<br> pDCTstat->DimmTrainFail &= ~(1<<(Receiver + Channel));<br> }<br>diff --git a/src/northbridge/amd/amdmct/mct/mcttmrl.c b/src/northbridge/amd/amdmct/mct/mcttmrl.c<br>index 4c6d8e6..3d57571 100644<br>--- a/src/northbridge/amd/amdmct/mct/mcttmrl.c<br>+++ b/src/northbridge/amd/amdmct/mct/mcttmrl.c<br>@@ -126,19 +126,19 @@<br> u32 pattern_buf;<br> <br> cr4 = read_cr4();<br>- if (cr4 & (1<<9)) { /* save the old value */<br>+ if (cr4 & (1 << 9)) { /* save the old value */<br> _SSE2 = 1;<br> }<br>- cr4 |= (1<<9); /* OSFXSR enable SSE2 */<br>+ cr4 |= (1 << 9); /* OSFXSR enable SSE2 */<br> write_cr4(cr4);<br> <br> addr = HWCR;<br> _RDMSR(addr, &lo, &hi);<br>- if (lo & (1<<17)) { /* save the old value */<br>+ if (lo & (1 << 17)) { /* save the old value */<br> _Wrap32Dis = 1;<br> }<br>- lo |= (1<<17); /* HWCR.wrap32dis */<br>- lo &= ~(1<<15); /* SSEDIS */<br>+ lo |= (1 << 17); /* HWCR.wrap32dis */<br>+ lo &= ~(1 << 15); /* SSEDIS */<br> /* Setting wrap32dis allows 64-bit memory references in<br> real mode */<br> _WRMSR(addr, lo, hi);<br>@@ -184,12 +184,12 @@<br> if (!_Wrap32Dis) {<br> addr = HWCR;<br> _RDMSR(addr, &lo, &hi);<br>- lo &= ~(1<<17); /* restore HWCR.wrap32dis */<br>+ lo &= ~(1 << 17); /* restore HWCR.wrap32dis */<br> _WRMSR(addr, lo, hi);<br> }<br> if (!_SSE2) {<br> cr4 = read_cr4();<br>- cr4 &= ~(1<<9); /* restore cr4.OSFXSR */<br>+ cr4 &= ~(1 << 9); /* restore cr4.OSFXSR */<br> write_cr4(cr4);<br> }<br> <br>@@ -224,7 +224,7 @@<br> dev = pDCTstat->dev_dct;<br> reg = 0x78 + Channel * 0x100;<br> val = Get_NB32(dev, reg);<br>- val &= ~(0x3ff<<22);<br>+ val &= ~(0x3ff << 22);<br> val |= MaxRdLatVal << 22;<br> /* program MaxRdLatency to correspond with current delay */<br> Set_NB32(dev, reg, val);<br>diff --git a/src/northbridge/amd/amdmct/mct_ddr3/mct_d.c b/src/northbridge/amd/amdmct/mct_ddr3/mct_d.c<br>index 1ac91a1..30520e0 100644<br>--- a/src/northbridge/amd/amdmct/mct_ddr3/mct_d.c<br>+++ b/src/northbridge/amd/amdmct/mct_ddr3/mct_d.c<br>@@ -3790,9 +3790,9 @@<br> for (Channel = 0; Channel < 2; Channel++) {<br> reg = 0x78;<br> val = Get_NB32_DCT(dev, Channel, reg);<br>- val &= ~(0x3ff<<22);<br>+ val &= ~(0x3ff << 22);<br> val |= ((u32) pDCTstat->CH_MaxRdLat[Channel][0] << 22);<br>- val &= ~(1<<DqsRcvEnTrain);<br>+ val &= ~(1 << DqsRcvEnTrain);<br> Set_NB32_DCT(dev, Channel, reg, val); /* program MaxRdLatency to correspond with current delay*/<br> }<br> }<br>@@ -3873,9 +3873,9 @@<br> limit = pDCTstat->DCTSysLimit;<br> } else if (base == BottomIO) {<br> /* SW Node Hoist */<br>- pMCTstat->GStatus |= 1<<GSB_SpIntRemapHole;<br>- pDCTstat->Status |= 1<<SB_SWNodeHole;<br>- pMCTstat->GStatus |= 1<<GSB_SoftHole;<br>+ pMCTstat->GStatus |= 1 << GSB_SpIntRemapHole;<br>+ pDCTstat->Status |= 1 << SB_SWNodeHole;<br>+ pMCTstat->GStatus |= 1 << GSB_SoftHole;<br> pMCTstat->HoleBase = base;<br> limit -= base;<br> base = _4GB_RJ8;<br>@@ -4218,7 +4218,7 @@<br> <br> dev = pDCTstat->dev_dct;<br> val = Get_NB32_DCT(dev, dct, 0x94);<br>- if (val & (1<<MemClkFreqVal)) {<br>+ if (val & (1 << MemClkFreqVal)) {<br> mctHookBeforeDramInit(); /* generalized Hook */<br> if (!(pMCTstat->GStatus & (1 << GSB_EnDIMMSpareNW)))<br> mct_DramInit(pMCTstat, pDCTstat, dct);<br>@@ -4616,30 +4616,30 @@<br> DramTimingLo |= val;<br> <br> val = pDCTstat->Trcd - Bias_TrcdT;<br>- DramTimingLo |= val<<4;<br>+ DramTimingLo |= val << 4;<br> <br> val = pDCTstat->Trp - Bias_TrpT;<br> val = mct_AdjustSPDTimings(pMCTstat, pDCTstat, val);<br>- DramTimingLo |= val<<7;<br>+ DramTimingLo |= val << 7;<br> <br> val = pDCTstat->Trtp - Bias_TrtpT;<br>- DramTimingLo |= val<<10;<br>+ DramTimingLo |= val << 10;<br> <br> val = pDCTstat->Tras - Bias_TrasT;<br>- DramTimingLo |= val<<12;<br>+ DramTimingLo |= val << 12;<br> <br> val = pDCTstat->Trc - Bias_TrcT;<br>- DramTimingLo |= val<<16;<br>+ DramTimingLo |= val << 16;<br> <br> val = pDCTstat->Trrd - Bias_TrrdT;<br>- DramTimingLo |= val<<22;<br>+ DramTimingLo |= val << 22;<br> <br> DramTimingHi = 0; /* Dram Timing High init */<br> val = pDCTstat->Twtr - Bias_TwtrT;<br>- DramTimingHi |= val<<8;<br>+ DramTimingHi |= val << 8;<br> <br> val = 2; /* Tref = 7.8us */<br>- DramTimingHi |= val<<16;<br>+ DramTimingHi |= val << 16;<br> <br> val = 0;<br> for (i = 4; i > 0; i--) {<br>@@ -5060,7 +5060,7 @@<br> DramControl |= val; /* RdPtrInit = 6 for Cx CPU */<br> <br> if (mctGet_NVbits(NV_CLKHZAltVidC3))<br>- DramControl |= 1<<16; /* check */<br>+ DramControl |= 1 << 16; /* check */<br> <br> DramControl |= 0x00002A00;<br> <br>@@ -5158,7 +5158,7 @@<br> DramTimingLo = Get_NB32_DCT(dev, dct, 0x88);<br> if (mctGet_NVbits(NV_AllMemClks) == 0) {<br> /* Special Jedec SPD diagnostic bit - "enable all clocks" */<br>- if (!(pDCTstat->Status & (1<<SB_DiagClks))) {<br>+ if (!(pDCTstat->Status & (1 << SB_DiagClks))) {<br> const u8 *p;<br> const u32 *q;<br> p = Tab_ManualCLKDis;<br>@@ -5181,7 +5181,7 @@<br> dword = 0;<br> byte = 0xFF;<br> while (dword < MAX_CS_SUPPORTED) {<br>- if (pDCTstat->CSPresent & (1<<dword)) {<br>+ if (pDCTstat->CSPresent & (1 << dword)) {<br> /* re-enable clocks for the enabled CS */<br> val = p[dword];<br> byte &= ~val;<br>@@ -5256,7 +5256,7 @@<br> if ((pDCTstat->Status & (1 << SB_64MuxedMode)) && ChipSel >=4)<br> byte -= 3;<br> <br>- if (pDCTstat->DIMMValid & (1<<byte)) {<br>+ if (pDCTstat->DIMMValid & (1 << byte)) {<br> byte = pDCTstat->spd_data.spd_bytes[ChipSel + dct][SPD_Addressing];<br> Rows = (byte >> 3) & 0x7; /* Rows:0b = 12-bit,... */<br> Cols = byte & 0x7; /* Cols:0b = 9-bit,... */<br>@@ -5288,7 +5288,7 @@<br> continue;<br> <br> /* bit no. of CS field in address mapping reg.*/<br>- dword <<= (ChipSel<<1);<br>+ dword <<= (ChipSel << 1);<br> BankAddrReg |= dword;<br> <br> /* Mask value=(2pow(rows+cols+banks+3)-1)>>8,<br>@@ -5306,18 +5306,18 @@<br> csMask--;<br> <br> /*set ChipSelect population indicator even bits*/<br>- pDCTstat->CSPresent |= (1<<ChipSel);<br>+ pDCTstat->CSPresent |= (1 << ChipSel);<br> if (Ranks >= 2)<br> /*set ChipSelect population indicator odd bits*/<br> pDCTstat->CSPresent |= 1 << (ChipSel + 1);<br> <br>- reg = 0x60+(ChipSel<<1); /*Dram CS Mask Register */<br>+ reg = 0x60+(ChipSel << 1); /*Dram CS Mask Register */<br> val = csMask;<br> val &= 0x1FF83FE0; /* Mask out reserved bits.*/<br> Set_NB32_DCT(dev, dct, reg, val);<br> } else {<br>- if (pDCTstat->DIMMSPDCSE & (1<<ChipSel))<br>- pDCTstat->CSTestFail |= (1<<ChipSel);<br>+ if (pDCTstat->DIMMSPDCSE & (1 << ChipSel))<br>+ pDCTstat->CSTestFail |= (1 << ChipSel);<br> } /* if DIMMValid*/<br> } /* while ChipSel*/<br> <br>@@ -5368,35 +5368,35 @@<br> byte = pDCTstat->spd_data.spd_bytes[i][SPD_Addressing] & 0x7;<br> byte1 = pDCTstat->spd_data.spd_bytes[i + 1][SPD_Addressing] & 0x7;<br> if (byte != byte1) {<br>- pDCTstat->ErrStatus |= (1<<SB_DimmMismatchO);<br>+ pDCTstat->ErrStatus |= (1 << SB_DimmMismatchO);<br> break;<br> }<br> <br> byte = pDCTstat->spd_data.spd_bytes[i][SPD_Density] & 0x0f;<br> byte1 = pDCTstat->spd_data.spd_bytes[i + 1][SPD_Density] & 0x0f;<br> if (byte != byte1) {<br>- pDCTstat->ErrStatus |= (1<<SB_DimmMismatchO);<br>+ pDCTstat->ErrStatus |= (1 << SB_DimmMismatchO);<br> break;<br> }<br> <br> byte = pDCTstat->spd_data.spd_bytes[i][SPD_Organization] & 0x7;<br> byte1 = pDCTstat->spd_data.spd_bytes[i + 1][SPD_Organization] & 0x7;<br> if (byte != byte1) {<br>- pDCTstat->ErrStatus |= (1<<SB_DimmMismatchO);<br>+ pDCTstat->ErrStatus |= (1 << SB_DimmMismatchO);<br> break;<br> }<br> <br> byte = (pDCTstat->spd_data.spd_bytes[i][SPD_Organization] >> 3) & 0x7;<br> byte1 = (pDCTstat->spd_data.spd_bytes[i + 1][SPD_Organization] >> 3) & 0x7;<br> if (byte != byte1) {<br>- pDCTstat->ErrStatus |= (1<<SB_DimmMismatchO);<br>+ pDCTstat->ErrStatus |= (1 << SB_DimmMismatchO);<br> break;<br> }<br> <br> byte = pDCTstat->spd_data.spd_bytes[i][SPD_DMBANKS] & 7; /* #ranks-1 */<br> byte1 = pDCTstat->spd_data.spd_bytes[i + 1][SPD_DMBANKS] & 7; /* #ranks-1 */<br> if (byte != byte1) {<br>- pDCTstat->ErrStatus |= (1<<SB_DimmMismatchO);<br>+ pDCTstat->ErrStatus |= (1 << SB_DimmMismatchO);<br> break;<br> }<br> <br>@@ -5433,7 +5433,7 @@<br> if (pMCTstat->GStatus & 1 << GSB_EnDIMMSpareNW) {<br> word = pDCTstat->CSPresent;<br> val = bsf(word);<br>- word &= ~(1<<val);<br>+ word &= ~(1 << val);<br> if (word)<br> /* Make sure at least two chip-selects are available */<br> _DSpareEn = 1;<br>@@ -5530,7 +5530,7 @@<br> <br> static u16 Get_Fk_D(u8 k)<br> {<br>- return Table_F_k[k]; /* FIXME: k or k<<1 ? */<br>+ return Table_F_k[k]; /* FIXME: k or k << 1 ? */<br> }<br> <br> static u8 DIMMPresence_D(struct MCTStatStruc *pMCTstat,<br>@@ -5604,7 +5604,7 @@<br> pDCTstat->ErrCode = SC_StopError;<br> } else {<br> /*if NV_SPDCHK_RESTRT is set to 1, ignore faulty SPD checksum*/<br>- pDCTstat->ErrStatus |= 1<<SB_DIMMChkSum;<br>+ pDCTstat->ErrStatus |= 1 << SB_DIMMChkSum;<br> byte = pDCTstat->spd_data.spd_bytes[i][SPD_TYPE];<br> if (byte == JED_DDR3SDRAM)<br> pDCTstat->DIMMValid |= 1 << i;<br>@@ -5699,7 +5699,7 @@<br> if (byte == 2)<br> bytex <<= 1; /*double Addr bus load value for dual rank DIMMs*/<br> <br>- j = i & (1<<0);<br>+ j = i & (1 << 0);<br> pDCTstat->DATAload[j] += byte; /*number of ranks on DATA bus*/<br> pDCTstat->MAload[j] += bytex; /*number of devices on CMD/ADDR bus*/<br> pDCTstat->MAdimms[j]++; /*number of DIMMs on A bus */<br>@@ -5757,38 +5757,38 @@<br> if (RegDIMMPresent != 0) {<br> if ((RegDIMMPresent ^ pDCTstat->DIMMValid) !=0) {<br> /* module type DIMM mismatch (reg'ed, unbuffered) */<br>- pDCTstat->ErrStatus |= 1<<SB_DimmMismatchM;<br>+ pDCTstat->ErrStatus |= 1 << SB_DimmMismatchM;<br> pDCTstat->ErrCode = SC_StopError;<br> } else{<br> /* all DIMMs are registered */<br>- pDCTstat->Status |= 1<<SB_Registered;<br>+ pDCTstat->Status |= 1 << SB_Registered;<br> }<br> }<br> if (LRDIMMPresent != 0) {<br> if ((LRDIMMPresent ^ pDCTstat->DIMMValid) !=0) {<br> /* module type DIMM mismatch (reg'ed, unbuffered) */<br>- pDCTstat->ErrStatus |= 1<<SB_DimmMismatchM;<br>+ pDCTstat->ErrStatus |= 1 << SB_DimmMismatchM;<br> pDCTstat->ErrCode = SC_StopError;<br> } else{<br> /* all DIMMs are registered */<br>- pDCTstat->Status |= 1<<SB_LoadReduced;<br>+ pDCTstat->Status |= 1 << SB_LoadReduced;<br> }<br> }<br> if (pDCTstat->DimmECCPresent != 0) {<br> if ((pDCTstat->DimmECCPresent ^ pDCTstat->DIMMValid) == 0) {<br> /* all DIMMs are ECC capable */<br>- pDCTstat->Status |= 1<<SB_ECCDIMMs;<br>+ pDCTstat->Status |= 1 << SB_ECCDIMMs;<br> }<br> }<br> if (pDCTstat->DimmPARPresent != 0) {<br> if ((pDCTstat->DimmPARPresent ^ pDCTstat->DIMMValid) == 0) {<br> /*all DIMMs are Parity capable */<br>- pDCTstat->Status |= 1<<SB_PARDIMMs;<br>+ pDCTstat->Status |= 1 << SB_PARDIMMs;<br> }<br> }<br> } else {<br> /* no DIMMs present or no DIMMs that qualified. */<br>- pDCTstat->ErrStatus |= 1<<SB_NoDimms;<br>+ pDCTstat->ErrStatus |= 1 << SB_NoDimms;<br> pDCTstat->ErrCode = SC_StopError;<br> }<br> <br>@@ -6851,11 +6851,11 @@<br> /* Clear Legacy BIOS Mode bit */<br> reg = 0x94;<br> val = Get_NB32_DCT(dev, 0, reg);<br>- val &= ~(1<<LegacyBiosMode);<br>+ val &= ~(1 << LegacyBiosMode);<br> Set_NB32_DCT(dev, 0, reg, val);<br> <br> val = Get_NB32_DCT(dev, 1, reg);<br>- val &= ~(1<<LegacyBiosMode);<br>+ val &= ~(1 << LegacyBiosMode);<br> Set_NB32_DCT(dev, 1, reg, val);<br> }<br> <br>@@ -7788,7 +7788,7 @@<br> msr = BU_CFG2;<br> _RDMSR(msr, &lo, &hi);<br> if (!pDCTstat->ClToNB_flag)<br>- lo &= ~(1<<ClLinesToNbDis);<br>+ lo &= ~(1 << ClLinesToNbDis);<br> _WRMSR(msr, lo, hi);<br> <br> }<br>@@ -8048,10 +8048,10 @@<br> <br> addr = HWCR;<br> _RDMSR(addr, &lo, &hi);<br>- if (lo & (1<<17)) { /* save the old value */<br>+ if (lo & (1 << 17)) { /* save the old value */<br> wrap32dis = 1;<br> }<br>- lo |= (1<<17); /* HWCR.wrap32dis */<br>+ lo |= (1 << 17); /* HWCR.wrap32dis */<br> /* Setting wrap32dis allows 64-bit memory references in 32bit mode */<br> _WRMSR(addr, lo, hi);<br> <br>@@ -8079,7 +8079,7 @@<br> if (!wrap32dis) {<br> addr = HWCR;<br> _RDMSR(addr, &lo, &hi);<br>- lo &= ~(1<<17); /* restore HWCR.wrap32dis */<br>+ lo &= ~(1 << 17); /* restore HWCR.wrap32dis */<br> _WRMSR(addr, lo, hi);<br> }<br> }<br>diff --git a/src/northbridge/amd/amdmct/mct_ddr3/mct_d_gcc.c b/src/northbridge/amd/amdmct/mct_ddr3/mct_d_gcc.c<br>index 82911c0..252ad4e 100644<br>--- a/src/northbridge/amd/amdmct/mct_ddr3/mct_d_gcc.c<br>+++ b/src/northbridge/amd/amdmct/mct_ddr3/mct_d_gcc.c<br>@@ -62,7 +62,7 @@<br> u32 ret = 0;<br> <br> for (i = 31; i > 0; i--) {<br>- if (x & (1<<i)) {<br>+ if (x & (1 << i)) {<br> ret = i;<br> break;<br> }<br>@@ -78,7 +78,7 @@<br> u32 ret = 32;<br> <br> for (i = 0; i < 32; i++) {<br>- if (x & (1<<i)) {<br>+ if (x & (1 << i)) {<br> ret = i;<br> break;<br> }<br>@@ -105,7 +105,7 @@<br> "outb %%al, $0xed\n\t" /* _EXECFENCE */<br> "clflush %%fs:(%0)\n\t"<br> "mfence\n\t"<br>- ::"a" (addr_hi<<8)<br>+ ::"a" (addr_hi << 8)<br> );<br> }<br> <br>@@ -226,7 +226,7 @@<br> "movl %%fs:-64(%%esi), %%eax\n\t" /* +1 */<br> "movl %%fs:(%%esi), %%eax\n\t" /* +2 */<br> "mfence\n\t"<br>- :: "a"(0), "S"((addr<<8)+128)<br>+ :: "a"(0), "S"((addr << 8)+128)<br> );<br> <br> }<br>@@ -268,7 +268,7 @@<br> "clflush %%fs:(%%esi)\n\t" /* +2 */<br> "mfence\n\t"<br> <br>- :: "S"((addr<<8)+128)<br>+ :: "S"((addr << 8)+128)<br> );<br> }<br> <br>diff --git a/src/northbridge/amd/amdmct/mct_ddr3/mctcsi_d.c b/src/northbridge/amd/amdmct/mct_ddr3/mctcsi_d.c<br>index 716e419..5e03497 100644<br>--- a/src/northbridge/amd/amdmct/mct_ddr3/mctcsi_d.c<br>+++ b/src/northbridge/amd/amdmct/mct_ddr3/mctcsi_d.c<br>@@ -49,9 +49,9 @@<br> <br> ChipSel = 0; /* Find out if current configuration is capable */<br> while (DoIntlv && (ChipSel < MAX_CS_SUPPORTED)) {<br>- reg = 0x40+(ChipSel<<2); /* Dram CS Base 0 */<br>+ reg = 0x40+(ChipSel << 2); /* Dram CS Base 0 */<br> val = Get_NB32_DCT(dev, dct, reg);<br>- if (val & (1<<CSEnable)) {<br>+ if (val & (1 << CSEnable)) {<br> EnChipSels++;<br> reg = 0x60+((ChipSel>>1)<<2); /*Dram CS Mask 0 */<br> val = Get_NB32_DCT(dev, dct, reg);<br>@@ -84,14 +84,14 @@<br> <br> if (DoIntlv) {<br> if (!_CsIntCap) {<br>- pDCTstat->ErrStatus |= 1<<SB_BkIntDis;<br>+ pDCTstat->ErrStatus |= 1 << SB_BkIntDis;<br> DoIntlv = 0;<br> }<br> }<br> <br> if (DoIntlv) {<br> val = Tab_int_D[BankEncd];<br>- if (pDCTstat->Status & (1<<SB_128bitmode))<br>+ if (pDCTstat->Status & (1 << SB_128bitmode))<br> val++;<br> <br> AddrLoMask = (EnChipSels - 1) << val;<br>@@ -104,7 +104,7 @@<br> BitDelta = bsf(AddrHiMask) - bsf(AddrLoMask);<br> <br> for (ChipSel = 0; ChipSel < MAX_CS_SUPPORTED; ChipSel++) {<br>- reg = 0x40 + (ChipSel<<2); /* Dram CS Base 0 */<br>+ reg = 0x40 + (ChipSel << 2); /* Dram CS Base 0 */<br> val = Get_NB32_DCT(dev, dct, reg);<br> if (val & 3) {<br> val_lo = val & AddrLoMask;<br>diff --git a/src/northbridge/amd/amdmct/mct_ddr3/mctdqs_d.c b/src/northbridge/amd/amdmct/mct_ddr3/mctdqs_d.c<br>index 10d4206..1f5be60 100644<br>--- a/src/northbridge/amd/amdmct/mct_ddr3/mctdqs_d.c<br>+++ b/src/northbridge/amd/amdmct/mct_ddr3/mctdqs_d.c<br>@@ -425,18 +425,18 @@<br> <br> print_debug_dqs("\nTrainDQSRdWrPos: Node_ID ", pDCTstat->Node_ID, 0);<br> cr4 = read_cr4();<br>- if (cr4 & (1<<9)) {<br>+ if (cr4 & (1 << 9)) {<br> _SSE2 = 1;<br> }<br>- cr4 |= (1<<9); /* OSFXSR enable SSE2 */<br>+ cr4 |= (1 << 9); /* OSFXSR enable SSE2 */<br> write_cr4(cr4);<br> <br> addr = HWCR;<br> _RDMSR(addr, &lo, &hi);<br>- if (lo & (1<<17)) {<br>+ if (lo & (1 << 17)) {<br> _Wrap32Dis = 1;<br> }<br>- lo |= (1<<17); /* HWCR.wrap32dis */<br>+ lo |= (1 << 17); /* HWCR.wrap32dis */<br> _WRMSR(addr, lo, hi); /* allow 64-bit memory references in real mode */<br> <br> /* Disable ECC correction of reads on the dram bus. */<br>@@ -832,12 +832,12 @@<br> if (!_Wrap32Dis) {<br> addr = HWCR;<br> _RDMSR(addr, &lo, &hi);<br>- lo &= ~(1<<17); /* restore HWCR.wrap32dis */<br>+ lo &= ~(1 << 17); /* restore HWCR.wrap32dis */<br> _WRMSR(addr, lo, hi);<br> }<br> if (!_SSE2) {<br> cr4 = read_cr4();<br>- cr4 &= ~(1<<9); /* restore cr4.OSFXSR */<br>+ cr4 &= ~(1 << 9); /* restore cr4.OSFXSR */<br> write_cr4(cr4);<br> }<br> <br>@@ -1642,18 +1642,18 @@<br> <br> print_debug_dqs("\nTrainDQSReceiverEnCyc: Node_ID ", pDCTstat->Node_ID, 0);<br> cr4 = read_cr4();<br>- if (cr4 & (1<<9)) {<br>+ if (cr4 & (1 << 9)) {<br> _SSE2 = 1;<br> }<br>- cr4 |= (1<<9); /* OSFXSR enable SSE2 */<br>+ cr4 |= (1 << 9); /* OSFXSR enable SSE2 */<br> write_cr4(cr4);<br> <br> addr = HWCR;<br> _RDMSR(addr, &lo, &hi);<br>- if (lo & (1<<17)) {<br>+ if (lo & (1 << 17)) {<br> _Wrap32Dis = 1;<br> }<br>- lo |= (1<<17); /* HWCR.wrap32dis */<br>+ lo |= (1 << 17); /* HWCR.wrap32dis */<br> _WRMSR(addr, lo, hi); /* allow 64-bit memory references in real mode */<br> <br> /* Disable ECC correction of reads on the dram bus. */<br>@@ -1863,12 +1863,12 @@<br> if (!_Wrap32Dis) {<br> addr = HWCR;<br> _RDMSR(addr, &lo, &hi);<br>- lo &= ~(1<<17); /* restore HWCR.wrap32dis */<br>+ lo &= ~(1 << 17); /* restore HWCR.wrap32dis */<br> _WRMSR(addr, lo, hi);<br> }<br> if (!_SSE2) {<br> cr4 = read_cr4();<br>- cr4 &= ~(1<<9); /* restore cr4.OSFXSR */<br>+ cr4 &= ~(1 << 9); /* restore cr4.OSFXSR */<br> write_cr4(cr4);<br> }<br> <br>@@ -1891,7 +1891,7 @@<br> u16 i;<br> <br> buf = (u32 *)(((u32)buffer + 0x10) & (0xfffffff0));<br>- if (pDCTstat->Status & (1<<SB_128bitmode)) {<br>+ if (pDCTstat->Status & (1 << SB_128bitmode)) {<br> pDCTstat->Pattern = 1; /* 18 cache lines, alternating qwords */<br> for (i = 0; i < 16*18; i++)<br> buf[i] = TestPatternJD1b_D[i];<br>@@ -2222,16 +2222,16 @@<br> dev = pDCTstat->dev_dct;<br> reg = 0x90;<br> val = Get_NB32_DCT(dev, 0, reg);<br>- if (val & (1<<DimmEcEn)) {<br>+ if (val & (1 << DimmEcEn)) {<br> _DisableDramECC |= 0x01;<br>- val &= ~(1<<DimmEcEn);<br>+ val &= ~(1 << DimmEcEn);<br> Set_NB32_DCT(dev, 0, reg, val);<br> }<br> if (!pDCTstat->GangedMode) {<br> val = Get_NB32_DCT(dev, 1, reg);<br>- if (val & (1<<DimmEcEn)) {<br>+ if (val & (1 << DimmEcEn)) {<br> _DisableDramECC |= 0x02;<br>- val &= ~(1<<DimmEcEn);<br>+ val &= ~(1 << DimmEcEn);<br> Set_NB32_DCT(dev, 1, reg, val);<br> }<br> }<br>@@ -2249,12 +2249,12 @@<br> <br> if ((_DisableDramECC & 0x01) == 0x01) {<br> val = Get_NB32_DCT(dev, 0, 0x90);<br>- val |= (1<<DimmEcEn);<br>+ val |= (1 << DimmEcEn);<br> Set_NB32_DCT(dev, 0, 0x90, val);<br> }<br> if ((_DisableDramECC & 0x02) == 0x02) {<br> val = Get_NB32_DCT(dev, 1, 0x90);<br>- val |= (1<<DimmEcEn);<br>+ val |= (1 << DimmEcEn);<br> Set_NB32_DCT(dev, 1, 0x90, val);<br> }<br> }<br>diff --git a/src/northbridge/amd/amdmct/mct_ddr3/mcthdi.c b/src/northbridge/amd/amdmct/mct_ddr3/mcthdi.c<br>index 2038af9..32d99ce 100644<br>--- a/src/northbridge/amd/amdmct/mct_ddr3/mcthdi.c<br>+++ b/src/northbridge/amd/amdmct/mct_ddr3/mcthdi.c<br>@@ -28,6 +28,6 @@<br> /*flag for selecting HW/SW DRAM Init HW DRAM Init */<br> reg = 0x90; /*DRAM Configuration Low */<br> val = Get_NB32_DCT(dev, dct, reg);<br>- val |= (1<<InitDram);<br>+ val |= (1 << InitDram);<br> Set_NB32_DCT(dev, dct, reg, val);<br> }<br>diff --git a/src/northbridge/amd/amdmct/mct_ddr3/mctmtr_d.c b/src/northbridge/amd/amdmct/mct_ddr3/mctmtr_d.c<br>index 8a1f736..11f4877 100644<br>--- a/src/northbridge/amd/amdmct/mct_ddr3/mctmtr_d.c<br>+++ b/src/northbridge/amd/amdmct/mct_ddr3/mctmtr_d.c<br>@@ -95,15 +95,15 @@<br> /* Limit */<br> /* MtrrAddr */<br> if (addr == -1) /* ran out of MTRRs?*/<br>- pMCTstat->GStatus |= 1<<GSB_MTRRshort;<br>+ pMCTstat->GStatus |= 1 << GSB_MTRRshort;<br> <br>- pMCTstat->Sub4GCacheTop = Cache32bTOP<<8;<br>+ pMCTstat->Sub4GCacheTop = Cache32bTOP << 8;<br> <br> /*======================================================================<br> Set TOP_MEM and TOM2 CPU registers<br> ======================================================================*/<br> addr = TOP_MEM;<br>- lo = Bottom32bIO<<8;<br>+ lo = Bottom32bIO << 8;<br> hi = Bottom32bIO>>24;<br> _WRMSR(addr, lo, hi);<br> printk(BIOS_DEBUG, "\t CPUMemTyping: Bottom32bIO:%x\n", Bottom32bIO);<br>@@ -117,11 +117,11 @@<br> addr = 0xC0010010; /* SYS_CFG */<br> _RDMSR(addr, &lo, &hi);<br> if (Bottom40bIO) {<br>- lo |= (1<<21); /* MtrrTom2En = 1 */<br>- lo |= (1<<22); /* Tom2ForceMemTypeWB */<br>+ lo |= (1 << 21); /* MtrrTom2En = 1 */<br>+ lo |= (1 << 22); /* Tom2ForceMemTypeWB */<br> } else {<br>- lo &= ~(1<<21); /* MtrrTom2En = 0 */<br>- lo &= ~(1<<22); /* Tom2ForceMemTypeWB */<br>+ lo &= ~(1 << 21); /* MtrrTom2En = 0 */<br>+ lo &= ~(1 << 22); /* Tom2ForceMemTypeWB */<br> }<br> _WRMSR(addr, lo, hi);<br> }<br>@@ -173,7 +173,7 @@<br> valx += curBase;<br> if ((curBase == 0) || (*pLimit < valx)) {<br> /* flop direction to "descending" code path*/<br>- valx = 1<<bsr(*pLimit - curBase);<br>+ valx = 1 << bsr(*pLimit - curBase);<br> curSize = valx;<br> valx += curBase;<br> }<br>@@ -250,6 +250,6 @@<br> printk(BIOS_DEBUG, "\t UMAMemTyping_D: Cache32bTOP:%x\n", Cache32bTOP);<br> SetMTRRrangeWB_D(0, &Cache32bTOP, &addr);<br> if (addr == -1) /* ran out of MTRRs?*/<br>- pMCTstat->GStatus |= 1<<GSB_MTRRshort;<br>+ pMCTstat->GStatus |= 1 << GSB_MTRRshort;<br> }<br> }<br>diff --git a/src/northbridge/amd/amdmct/mct_ddr3/mctsrc.c b/src/northbridge/amd/amdmct/mct_ddr3/mctsrc.c<br>index 984f604..2776051 100644<br>--- a/src/northbridge/amd/amdmct/mct_ddr3/mctsrc.c<br>+++ b/src/northbridge/amd/amdmct/mct_ddr3/mctsrc.c<br>@@ -579,7 +579,7 @@<br> SetUpperFSbase(testaddr);<br> testaddr <<= 8;<br> <br>- if ((pDCTstat->Status & (1<<SB_128bitmode)) && channel) {<br>+ if ((pDCTstat->Status & (1 << SB_128bitmode)) && channel) {<br> testaddr += 8; /* second channel */<br> }<br> <br>@@ -997,12 +997,12 @@<br> <br> if (!_Wrap32Dis) {<br> msr = rdmsr(HWCR);<br>- msr.lo &= ~(1<<17); /* restore HWCR.wrap32dis */<br>+ msr.lo &= ~(1 << 17); /* restore HWCR.wrap32dis */<br> wrmsr(HWCR, msr);<br> }<br> if (!_SSE2) {<br> cr4 = read_cr4();<br>- cr4 &= ~(1<<9); /* restore cr4.OSFXSR */<br>+ cr4 &= ~(1 << 9); /* restore cr4.OSFXSR */<br> write_cr4(cr4);<br> }<br> <br>@@ -1500,12 +1500,12 @@<br> if (!_Wrap32Dis) {<br> msr = HWCR;<br> _RDMSR(msr, &lo, &hi);<br>- lo &= ~(1<<17); /* restore HWCR.wrap32dis */<br>+ lo &= ~(1 << 17); /* restore HWCR.wrap32dis */<br> _WRMSR(msr, lo, hi);<br> }<br> if (!_SSE2) {<br> cr4 = read_cr4();<br>- cr4 &= ~(1<<9); /* restore cr4.OSFXSR */<br>+ cr4 &= ~(1 << 9); /* restore cr4.OSFXSR */<br> write_cr4(cr4);<br> }<br> <br>@@ -1720,12 +1720,12 @@<br> if (!_Wrap32Dis) {<br> msr = HWCR;<br> _RDMSR(msr, &lo, &hi);<br>- lo &= ~(1<<17); /* restore HWCR.wrap32dis */<br>+ lo &= ~(1 << 17); /* restore HWCR.wrap32dis */<br> _WRMSR(msr, lo, hi);<br> }<br> if (!_SSE2) {<br> cr4 = read_cr4();<br>- cr4 &= ~(1<<9); /* restore cr4.OSFXSR */<br>+ cr4 &= ~(1 << 9); /* restore cr4.OSFXSR */<br> write_cr4(cr4);<br> }<br> <br>diff --git a/src/northbridge/amd/amdmct/mct_ddr3/mctsrc1p.c b/src/northbridge/amd/amdmct/mct_ddr3/mctsrc1p.c<br>index 2592eed..5853fd2 100644<br>--- a/src/northbridge/amd/amdmct/mct_ddr3/mctsrc1p.c<br>+++ b/src/northbridge/amd/amdmct/mct_ddr3/mctsrc1p.c<br>@@ -81,7 +81,7 @@<br> <br> p[i] = val;<br> }<br>- /* pDCTstat->DimmTrainFail &= ~(1<<Receiver+Channel); */<br>+ /* pDCTstat->DimmTrainFail &= ~(1 << Receiver+Channel); */<br> <br> return MaxValue;<br> }<br>diff --git a/src/northbridge/amd/amdmct/mct_ddr3/mctsrc2p.c b/src/northbridge/amd/amdmct/mct_ddr3/mctsrc2p.c<br>index 8eeb93f..29dccf6 100644<br>--- a/src/northbridge/amd/amdmct/mct_ddr3/mctsrc2p.c<br>+++ b/src/northbridge/amd/amdmct/mct_ddr3/mctsrc2p.c<br>@@ -106,7 +106,7 @@<br> }<br> }<br> if (!valid) {<br>- pDCTstat->ErrStatus |= 1<<SB_NORCVREN;<br>+ pDCTstat->ErrStatus |= 1 << SB_NORCVREN;<br> } else {<br> pDCTstat->DimmTrainFail &= ~(1<<(Receiver + Channel));<br> }<br>diff --git a/src/northbridge/amd/amdmct/mct_ddr3/mcttmrl.c b/src/northbridge/amd/amdmct/mct_ddr3/mcttmrl.c<br>index 039a747..46c59ea 100644<br>--- a/src/northbridge/amd/amdmct/mct_ddr3/mcttmrl.c<br>+++ b/src/northbridge/amd/amdmct/mct_ddr3/mcttmrl.c<br>@@ -125,19 +125,19 @@<br> u32 pattern_buf;<br> <br> cr4 = read_cr4();<br>- if (cr4 & (1<<9)) { /* save the old value */<br>+ if (cr4 & (1 << 9)) { /* save the old value */<br> _SSE2 = 1;<br> }<br>- cr4 |= (1<<9); /* OSFXSR enable SSE2 */<br>+ cr4 |= (1 << 9); /* OSFXSR enable SSE2 */<br> write_cr4(cr4);<br> <br> addr = HWCR;<br> _RDMSR(addr, &lo, &hi);<br>- if (lo & (1<<17)) { /* save the old value */<br>+ if (lo & (1 << 17)) { /* save the old value */<br> _Wrap32Dis = 1;<br> }<br>- lo |= (1<<17); /* HWCR.wrap32dis */<br>- lo &= ~(1<<15); /* SSEDIS */<br>+ lo |= (1 << 17); /* HWCR.wrap32dis */<br>+ lo &= ~(1 << 15); /* SSEDIS */<br> /* Setting wrap32dis allows 64-bit memory references in<br> real mode */<br> _WRMSR(addr, lo, hi);<br>@@ -183,12 +183,12 @@<br> if (!_Wrap32Dis) {<br> addr = HWCR;<br> _RDMSR(addr, &lo, &hi);<br>- lo &= ~(1<<17); /* restore HWCR.wrap32dis */<br>+ lo &= ~(1 << 17); /* restore HWCR.wrap32dis */<br> _WRMSR(addr, lo, hi);<br> }<br> if (!_SSE2) {<br> cr4 = read_cr4();<br>- cr4 &= ~(1<<9); /* restore cr4.OSFXSR */<br>+ cr4 &= ~(1 << 9); /* restore cr4.OSFXSR */<br> write_cr4(cr4);<br> }<br> <br>@@ -222,8 +222,8 @@<br> dev = pDCTstat->dev_dct;<br> reg = 0x78;<br> val = Get_NB32_DCT(dev, Channel, reg);<br>- val &= ~(0x3ff<<22);<br>- val |= MaxRdLatVal<<22;<br>+ val &= ~(0x3ff << 22);<br>+ val |= MaxRdLatVal << 22;<br> /* program MaxRdLatency to correspond with current delay */<br> Set_NB32_DCT(dev, Channel, reg, val);<br> }<br>@@ -242,7 +242,7 @@<br> u8 ret = DQS_PASS;<br> <br> SetUpperFSbase(addr);<br>- addr_lo = addr<<8;<br>+ addr_lo = addr << 8;<br> <br> _EXECFENCE;<br> for (i = 0; i < 16*3; i++) {<br>diff --git a/src/northbridge/amd/amdmct/mct_ddr3/mctwl.c b/src/northbridge/amd/amdmct/mct_ddr3/mctwl.c<br>index 53c4a2d..b16121f 100644<br>--- a/src/northbridge/amd/amdmct/mct_ddr3/mctwl.c<br>+++ b/src/northbridge/amd/amdmct/mct_ddr3/mctwl.c<br>@@ -480,7 +480,7 @@<br> while (reg < 0x60) {<br> val = Get_NB32_DCT(pDCTstat->dev_dct, dct, reg);<br> if (val & (1 << CSEnable))<br>- set ? (val |= 1 << onDimmMirror) : (val &= ~(1<<onDimmMirror));<br>+ set ? (val |= 1 << onDimmMirror) : (val &= ~(1 << onDimmMirror));<br> Set_NB32_DCT(pDCTstat->dev_dct, dct, reg, val);<br> reg += 8;<br> }<br>diff --git a/src/northbridge/amd/amdmct/mct_ddr3/mutilc_d.c b/src/northbridge/amd/amdmct/mct_ddr3/mutilc_d.c<br>index f17e4d6..aa68c93 100644<br>--- a/src/northbridge/amd/amdmct/mct_ddr3/mutilc_d.c<br>+++ b/src/northbridge/amd/amdmct/mct_ddr3/mutilc_d.c<br>@@ -44,7 +44,7 @@<br> AmdMemPCIRead(loc, pValue);<br> *pValue = *pValue >> lowbit; /* Shift */<br> <br>- /* A 1<<32 == 1<<0 due to x86 SHL instruction, so skip if that is the case */<br>+ /* A 1 << 32 == 1 << 0 due to x86 SHL instruction, so skip if that is the case */<br> if ((highbit-lowbit) != 31)<br> *pValue &= (((u32)1 << (highbit-lowbit+1))-1);<br> }<br>@@ -55,7 +55,7 @@<br> <br> /* ASSERT(highbit < 32 && lowbit < 32 && highbit >= lowbit && (loc & 3) == 0); */<br> <br>- /* A 1<<32 == 1<<0 due to x86 SHL instruction, so skip if that is the case */<br>+ /* A 1 << 32 == 1 << 0 due to x86 SHL instruction, so skip if that is the case */<br> if ((highbit-lowbit) != 31)<br> mask = (((u32)1 << (highbit-lowbit+1))-1);<br> else<br>diff --git a/src/northbridge/amd/lx/northbridge.c b/src/northbridge/amd/lx/northbridge.c<br>index 93ec350..ae8110d 100644<br>--- a/src/northbridge/amd/lx/northbridge.c<br>+++ b/src/northbridge/amd/lx/northbridge.c<br>@@ -35,16 +35,16 @@<br> /* here is programming for the various MSRs.*/<br> #define IM_QWAIT 0x100000<br> <br>-#define DMCF_WRITE_SERIALIZE_REQUEST (2<<12) /* 2 outstanding */ /* in high */<br>+#define DMCF_WRITE_SERIALIZE_REQUEST (2 << 12) /* 2 outstanding */ /* in high */<br> #define DMCF_SERIAL_LOAD_MISSES (2) /* enabled */<br> <br> /* these are the 8-bit attributes for controlling RCONF registers */<br>-#define CACHE_DISABLE (1<<0)<br>-#define WRITE_ALLOCATE (1<<1)<br>-#define WRITE_PROTECT (1<<2)<br>-#define WRITE_THROUGH (1<<3)<br>-#define WRITE_COMBINE (1<<4)<br>-#define WRITE_SERIALIZE (1<<5)<br>+#define CACHE_DISABLE (1 << 0)<br>+#define WRITE_ALLOCATE (1 << 1)<br>+#define WRITE_PROTECT (1 << 2)<br>+#define WRITE_THROUGH (1 << 3)<br>+#define WRITE_COMBINE (1 << 4)<br>+#define WRITE_SERIALIZE (1 << 5)<br> <br> /* RAM has none of this stuff */<br> #define RAM_PROPERTIES (0)<br>@@ -56,17 +56,17 @@<br> /* the are region configuration range registers, or RRCF */<br> /* in msr terms, the are a straight base, top address assign, since they are 4k aligned. */<br> /* so no left-shift needed for top or base */<br>-#define RRCF_LOW(base,properties) (base|(1<<8)|properties)<br>+#define RRCF_LOW(base,properties) (base|(1 << 8)|properties)<br> #define RRCF_LOW_CD(base) RRCF_LOW(base, CACHE_DISABLE)<br> <br> /* build initializer for P2D MSR */<br>-#define P2D_BM(msr, pdid1, bizarro, pbase, pmask) {msr, {.hi=(pdid1<<29)|(bizarro<<28)|(pbase>>24), .lo=(pbase<<8)|pmask}}<br>-#define P2D_BMO(msr, pdid1, bizarro, poffset, pbase, pmask) {msr, {.hi=(pdid1<<29)|(bizarro<<28)|(poffset<<8)|(pbase>>24), .lo=(pbase<<8)|pmask}}<br>-#define P2D_R(msr, pdid1, bizarro, pmax, pmin) {msr, {.hi=(pdid1<<29)|(bizarro<<28)|(pmax>>12), .lo=(pmax<<20)|pmin}}<br>-#define P2D_RO(msr, pdid1, bizarro, poffset, pmax, pmin) {msr, {.hi=(pdid1<<29)|(bizarro<<28)|(poffset<<8)|(pmax>>12), .lo=(pmax<<20)|pmin}}<br>-#define P2D_SC(msr, pdid1, bizarro, wen, ren,pscbase) {msr, {.hi=(pdid1<<29)|(bizarro<<28)|(wen), .lo=(ren<<16)|(pscbase>>18)}}<br>-#define IOD_BM(msr, pdid1, bizarro, ibase, imask) {msr, {.hi=(pdid1<<29)|(bizarro<<28)|(ibase>>12), .lo=(ibase<<20)|imask}}<br>-#define IOD_SC(msr, pdid1, bizarro, en, wen, ren, ibase) {msr, {.hi=(pdid1<<29)|(bizarro<<28), .lo=(en<<24)|(wen<<21)|(ren<<20)|(ibase<<3)}}<br>+#define P2D_BM(msr, pdid1, bizarro, pbase, pmask) {msr, {.hi=(pdid1 << 29)|(bizarro << 28)|(pbase>>24), .lo=(pbase << 8)|pmask}}<br>+#define P2D_BMO(msr, pdid1, bizarro, poffset, pbase, pmask) {msr, {.hi=(pdid1 << 29)|(bizarro << 28)|(poffset << 8)|(pbase>>24), .lo=(pbase << 8)|pmask}}<br>+#define P2D_R(msr, pdid1, bizarro, pmax, pmin) {msr, {.hi=(pdid1 << 29)|(bizarro << 28)|(pmax>>12), .lo=(pmax << 20)|pmin}}<br>+#define P2D_RO(msr, pdid1, bizarro, poffset, pmax, pmin) {msr, {.hi=(pdid1 << 29)|(bizarro << 28)|(poffset << 8)|(pmax>>12), .lo=(pmax << 20)|pmin}}<br>+#define P2D_SC(msr, pdid1, bizarro, wen, ren,pscbase) {msr, {.hi=(pdid1 << 29)|(bizarro << 28)|(wen), .lo=(ren << 16)|(pscbase>>18)}}<br>+#define IOD_BM(msr, pdid1, bizarro, ibase, imask) {msr, {.hi=(pdid1 << 29)|(bizarro << 28)|(ibase>>12), .lo=(ibase << 20)|imask}}<br>+#define IOD_SC(msr, pdid1, bizarro, en, wen, ren, ibase) {msr, {.hi=(pdid1 << 29)|(bizarro << 28), .lo=(en << 24)|(wen << 21)|(ren << 20)|(ibase << 3)}}<br> <br> void print_conf(void);<br> void graphics_init(void);<br>diff --git a/src/northbridge/amd/pi/00630F01/northbridge.c b/src/northbridge/amd/pi/00630F01/northbridge.c<br>index 5ba0e44..3cd84d5 100644<br>--- a/src/northbridge/amd/pi/00630F01/northbridge.c<br>+++ b/src/northbridge/amd/pi/00630F01/northbridge.c<br>@@ -72,12 +72,12 @@<br> temp = pci_read_config32(dev, 0x44 + (nodeid << 3)); //[39:24] at [31:16]<br> d.mask = ((temp & 0xfff80000)>>(8+3)); // mask out DramMask [26:24] too<br> temp = pci_read_config32(dev, 0x144 + (nodeid <<3)) & 0xff; //[47:40] at [7:0]<br>- d.mask |= temp<<21;<br>+ d.mask |= temp << 21;<br> temp = pci_read_config32(dev, 0x40 + (nodeid << 3)); //[39:24] at [31:16]<br> d.mask |= (temp & 1); // enable bit<br> d.base = ((temp & 0xfff80000)>>(8+3)); // mask out DramBase [26:24) too<br> temp = pci_read_config32(dev, 0x140 + (nodeid <<3)) & 0xff; //[47:40] at [7:0]<br>- d.base |= temp<<21;<br>+ d.base |= temp << 21;<br> return d;<br> }<br> <br>@@ -87,10 +87,10 @@<br> u32 i;<br> u32 tempreg;<br> /* io range allocation */<br>- tempreg = (nodeid&0xf) | ((nodeid & 0x30)<<(8-4)) | (linkn<<4) | ((io_max&0xf0)<<(12-4)); //limit<br>+ tempreg = (nodeid&0xf) | ((nodeid & 0x30)<<(8-4)) | (linkn << 4) | ((io_max&0xf0)<<(12-4)); //limit<br> for (i = 0; i < node_nums; i++)<br> pci_write_config32(__f1_dev[i], reg+4, tempreg);<br>- tempreg = 3 /*| (3<<4)*/ | ((io_min&0xf0)<<(12-4)); //base :ISA and VGA ?<br>+ tempreg = 3 /*| (3 << 4)*/ | ((io_min&0xf0)<<(12-4)); //base :ISA and VGA ?<br> for (i = 0; i < node_nums; i++)<br> pci_write_config32(__f1_dev[i], reg, tempreg);<br> }<br>@@ -100,7 +100,7 @@<br> u32 i;<br> u32 tempreg;<br> /* io range allocation */<br>- tempreg = (nodeid&0xf) | (linkn<<4) | (mmio_max&0xffffff00); //limit<br>+ tempreg = (nodeid&0xf) | (linkn << 4) | (mmio_max&0xffffff00); //limit<br> for (i = 0; i < nodes; i++)<br> pci_write_config32(__f1_dev[i], reg+4, tempreg);<br> tempreg = 3 | (nodeid & 0x30) | (mmio_min&0xffffff00);<br>@@ -171,7 +171,7 @@<br> {<br> u32 val;<br> <br>- val = 1 | (nodeid<<4) | (linkn<<12);<br>+ val = 1 | (nodeid << 4) | (linkn << 12);<br> /* it will routing<br> * (1)mmio 0xa0000:0xbffff<br> * (2)io 0x3b0:0x3bb, 0x3c0:0x3df<br>@@ -660,7 +660,7 @@<br> if (!(d.mask & 1)) continue; // no memory on this node<br> hole = pci_read_config32(__f1_dev[i], 0xf0);<br> if (hole & 1) { // we find the hole<br>- mem_hole.hole_startk = (hole & (0xff<<24)) >> 10;<br>+ mem_hole.hole_startk = (hole & (0xff << 24)) >> 10;<br> mem_hole.node_id = i; // record the node No with hole<br> break; // only one hole<br> }<br>diff --git a/src/northbridge/amd/pi/00660F01/northbridge.c b/src/northbridge/amd/pi/00660F01/northbridge.c<br>index bd4884c..899ed0d 100644<br>--- a/src/northbridge/amd/pi/00660F01/northbridge.c<br>+++ b/src/northbridge/amd/pi/00660F01/northbridge.c<br>@@ -99,7 +99,7 @@<br> u32 i;<br> u32 tempreg;<br> /* io range allocation */<br>- tempreg = (nodeid&0xf) | (linkn<<4) | (mmio_max&0xffffff00); //limit<br>+ tempreg = (nodeid&0xf) | (linkn << 4) | (mmio_max&0xffffff00); //limit<br> for (i = 0; i < nodes; i++)<br> pci_write_config32(__f1_dev[i], reg+4, tempreg);<br> tempreg = 3 | (nodeid & 0x30) | (mmio_min&0xffffff00);<br>@@ -178,7 +178,7 @@<br> {<br> u32 val;<br> <br>- val = 1 | (nodeid << 4) | (linkn<<12);<br>+ val = 1 | (nodeid << 4) | (linkn << 12);<br> /* it will routing<br> * (1)mmio 0xa0000:0xbffff<br> * (2)io 0x3b0:0x3bb, 0x3c0:0x3df<br>@@ -663,7 +663,7 @@<br> hole = pci_read_config32(__f1_dev[i], 0xf0);<br> if (hole & 2) {<br> /* we find the hole */<br>- mem_hole.hole_startk = (hole & (0xff<<24)) >> 10;<br>+ mem_hole.hole_startk = (hole & (0xff << 24)) >> 10;<br> mem_hole.node_id = i; // record the node No with hole<br> break; // only one hole<br> }<br>diff --git a/src/northbridge/amd/pi/00670F00/northbridge.c b/src/northbridge/amd/pi/00670F00/northbridge.c<br>index f8be67d..a912ec4 100644<br>--- a/src/northbridge/amd/pi/00670F00/northbridge.c<br>+++ b/src/northbridge/amd/pi/00670F00/northbridge.c<br>@@ -99,7 +99,7 @@<br> u32 i;<br> u32 tempreg;<br> /* io range allocation */<br>- tempreg = (nodeid&0xf) | (linkn<<4) | (mmio_max&0xffffff00); //limit<br>+ tempreg = (nodeid&0xf) | (linkn << 4) | (mmio_max&0xffffff00); //limit<br> for (i=0; i<nodes; i++)<br> pci_write_config32(__f1_dev[i], reg+4, tempreg);<br> tempreg = 3 | (nodeid & 0x30) | (mmio_min&0xffffff00);<br>@@ -178,7 +178,7 @@<br> {<br> u32 val;<br> <br>- val = 1 | (nodeid << 4) | (linkn<<12);<br>+ val = 1 | (nodeid << 4) | (linkn << 12);<br> /* it will routing<br> * (1)mmio 0xa0000:0xbffff<br> * (2)io 0x3b0:0x3bb, 0x3c0:0x3df<br>@@ -664,7 +664,7 @@<br> hole = pci_read_config32(__f1_dev[i], 0xf0);<br> if (hole & 2) {<br> /* we find the hole */<br>- mem_hole.hole_startk = (hole & (0xff<<24)) >> 10;<br>+ mem_hole.hole_startk = (hole & (0xff << 24)) >> 10;<br> mem_hole.node_id = i; // record the node No with hole<br> break; // only one hole<br> }<br>diff --git a/src/northbridge/amd/pi/00730F01/northbridge.c b/src/northbridge/amd/pi/00730F01/northbridge.c<br>index 960078e..4d01dda 100644<br>--- a/src/northbridge/amd/pi/00730F01/northbridge.c<br>+++ b/src/northbridge/amd/pi/00730F01/northbridge.c<br>@@ -67,12 +67,12 @@<br> temp = pci_read_config32(dev, 0x44 + (nodeid << 3)); //[39:24] at [31:16]<br> d.mask = ((temp & 0xfff80000)>>(8+3)); // mask out DramMask [26:24] too<br> temp = pci_read_config32(dev, 0x144 + (nodeid <<3)) & 0xff; //[47:40] at [7:0]<br>- d.mask |= temp<<21;<br>+ d.mask |= temp << 21;<br> temp = pci_read_config32(dev, 0x40 + (nodeid << 3)); //[39:24] at [31:16]<br> d.mask |= (temp & 1); // enable bit<br> d.base = ((temp & 0xfff80000)>>(8+3)); // mask out DramBase [26:24) too<br> temp = pci_read_config32(dev, 0x140 + (nodeid <<3)) & 0xff; //[47:40] at [7:0]<br>- d.base |= temp<<21;<br>+ d.base |= temp << 21;<br> return d;<br> }<br> <br>@@ -82,10 +82,10 @@<br> u32 i;<br> u32 tempreg;<br> /* io range allocation */<br>- tempreg = (nodeid&0xf) | ((nodeid & 0x30)<<(8-4)) | (linkn<<4) | ((io_max&0xf0)<<(12-4)); //limit<br>+ tempreg = (nodeid&0xf) | ((nodeid & 0x30)<<(8-4)) | (linkn << 4) | ((io_max&0xf0)<<(12-4)); //limit<br> for (i = 0; i < node_nums; i++)<br> pci_write_config32(__f1_dev[i], reg+4, tempreg);<br>- tempreg = 3 /*| (3<<4)*/ | ((io_min&0xf0)<<(12-4)); //base :ISA and VGA ?<br>+ tempreg = 3 /*| (3 << 4)*/ | ((io_min&0xf0)<<(12-4)); //base :ISA and VGA ?<br> for (i = 0; i < node_nums; i++)<br> pci_write_config32(__f1_dev[i], reg, tempreg);<br> }<br>@@ -95,7 +95,7 @@<br> u32 i;<br> u32 tempreg;<br> /* io range allocation */<br>- tempreg = (nodeid&0xf) | (linkn<<4) | (mmio_max&0xffffff00); //limit<br>+ tempreg = (nodeid&0xf) | (linkn << 4) | (mmio_max&0xffffff00); //limit<br> for (i = 0; i < nodes; i++)<br> pci_write_config32(__f1_dev[i], reg+4, tempreg);<br> tempreg = 3 | (nodeid & 0x30) | (mmio_min&0xffffff00);<br>@@ -174,7 +174,7 @@<br> {<br> u32 val;<br> <br>- val = 1 | (nodeid<<4) | (linkn<<12);<br>+ val = 1 | (nodeid << 4) | (linkn << 12);<br> /* it will routing<br> * (1)mmio 0xa0000:0xbffff<br> * (2)io 0x3b0:0x3bb, 0x3c0:0x3df<br>@@ -676,7 +676,7 @@<br> if (!(d.mask & 1)) continue; // no memory on this node<br> hole = pci_read_config32(__f1_dev[i], 0xf0);<br> if (hole & 2) { // we find the hole<br>- mem_hole.hole_startk = (hole & (0xff<<24)) >> 10;<br>+ mem_hole.hole_startk = (hole & (0xff << 24)) >> 10;<br> mem_hole.node_id = i; // record the node No with hole<br> break; // only one hole<br> }<br>diff --git a/src/northbridge/intel/e7505/e7505.h b/src/northbridge/intel/e7505/e7505.h<br>index 9c9171d..c3dc70a 100644<br>--- a/src/northbridge/intel/e7505/e7505.h<br>+++ b/src/northbridge/intel/e7505/e7505.h<br>@@ -50,17 +50,17 @@<br> #define MCHTST 0xF4 /* MCH Test Register, 32 bit? (if similar to 855PM) */<br> <br> // CAS# Latency bits in the DRAM Timing (DRT) register<br>-#define DRT_CAS_2_5 (0<<4)<br>-#define DRT_CAS_2_0 (1<<4)<br>-#define DRT_CAS_MASK (3<<4)<br>+#define DRT_CAS_2_5 (0 << 4)<br>+#define DRT_CAS_2_0 (1 << 4)<br>+#define DRT_CAS_MASK (3 << 4)<br> <br> // Mode Select (SMS) bits in the DRAM Controller Mode (DRC) register<br>-#define RAM_COMMAND_NOP (1<<4)<br>-#define RAM_COMMAND_PRECHARGE (2<<4)<br>-#define RAM_COMMAND_MRS (3<<4)<br>-#define RAM_COMMAND_EMRS (4<<4)<br>-#define RAM_COMMAND_CBR (6<<4)<br>-#define RAM_COMMAND_NORMAL (7<<4)<br>+#define RAM_COMMAND_NOP (1 << 4)<br>+#define RAM_COMMAND_PRECHARGE (2 << 4)<br>+#define RAM_COMMAND_MRS (3 << 4)<br>+#define RAM_COMMAND_EMRS (4 << 4)<br>+#define RAM_COMMAND_CBR (6 << 4)<br>+#define RAM_COMMAND_NORMAL (7 << 4)<br> <br> #define DRC_DONE (1 << 29)<br> <br>diff --git a/src/northbridge/intel/e7505/raminit.c b/src/northbridge/intel/e7505/raminit.c<br>index b38132a..1d5ab6e 100644<br>--- a/src/northbridge/intel/e7505/raminit.c<br>+++ b/src/northbridge/intel/e7505/raminit.c<br>@@ -1827,14 +1827,14 @@<br> pci_write_config8(MCHDEV, PAM_0 + i, 0x33);<br> <br> /* Conservatively say each row has 64MB of ram, we will fix this up later<br>- * Initial TOLM 8 rows 64MB each (1<<3 * 1<<26) >> 16 = 1<<13<br>+ * Initial TOLM 8 rows 64MB each (1 << 3 * 1 << 26) >> 16 = 1 << 13<br> *<br> * FIXME: Hard-coded limit to first four rows to prevent overlap!<br> */<br> pci_write_config32(MCHDEV, DRB_ROW_0, 0x04030201);<br> pci_write_config32(MCHDEV, DRB_ROW_4, 0x04040404);<br> //pci_write_config32(MCHDEV, DRB_ROW_4, 0x08070605);<br>- pci_write_config16(MCHDEV, TOLM, (1<<13));<br>+ pci_write_config16(MCHDEV, TOLM, (1 << 13));<br> <br> /* DIMM clocks off */<br> pci_write_config8(MCHDEV, CKDIS, 0xff);<br>@@ -1846,7 +1846,7 @@<br> // Back-to-Back Write-Read Turnaround. All others are configured based on SPD.<br> dword = pci_read_config32(MCHDEV, DRT);<br> dword &= 0xC7F8FFFF;<br>- dword |= (0x28<<24)|(0x03<<16);<br>+ dword |= (0x28 << 24)|(0x03 << 16);<br> pci_write_config32(MCHDEV, DRT, dword);<br> <br> dword = pci_read_config32(MCHDEV, DRC);<br>diff --git a/src/northbridge/intel/gm45/iommu.c b/src/northbridge/intel/gm45/iommu.c<br>index 77aba94..f25347a 100644<br>--- a/src/northbridge/intel/gm45/iommu.c<br>+++ b/src/northbridge/intel/gm45/iommu.c<br>@@ -57,7 +57,7 @@<br> void* bar = (void*)pci_read_config32(igd, PCI_BASE_ADDRESS_0);<br> <br> /* clear GTT, 2MB is enough (and should be safe) */<br>- memset(bar, 0, 2<<20);<br>+ memset(bar, 0, 2 << 20);<br> <br> /* and now disable again */<br> cmd &= ~(PCI_COMMAND_MASTER | PCI_COMMAND_MEMORY);<br>diff --git a/src/northbridge/intel/gm45/pm.c b/src/northbridge/intel/gm45/pm.c<br>index 7a3b498..af4cf5c 100644<br>--- a/src/northbridge/intel/gm45/pm.c<br>+++ b/src/northbridge/intel/gm45/pm.c<br>@@ -215,9 +215,9 @@<br> }<br> if (stepping > STEPPING_B0) {<br> if (fsb != FSB_CLOCK_667MHz)<br>- MCHBAR32(0x70) = (MCHBAR32(0x70) & ~(3<<21)) | (1 << 21);<br>+ MCHBAR32(0x70) = (MCHBAR32(0x70) & ~(3 << 21)) | (1 << 21);<br> else<br>- MCHBAR32(0x70) = (MCHBAR32(0x70) & ~(3<<21));<br>+ MCHBAR32(0x70) = (MCHBAR32(0x70) & ~(3 << 21));<br> }<br> if (stepping > STEPPING_B2)<br> MCHBAR32(0x44) |= 1 << 30;<br>diff --git a/src/northbridge/intel/gm45/raminit.c b/src/northbridge/intel/gm45/raminit.c<br>index d2da3b0..df756e1 100644<br>--- a/src/northbridge/intel/gm45/raminit.c<br>+++ b/src/northbridge/intel/gm45/raminit.c<br>@@ -1467,14 +1467,14 @@<br> "system-memory i/o initialization.\n");<br> <br> tmp = MCHBAR32(0x1400);<br>- tmp &= ~(3<<13);<br>- tmp |= (1<<9) | (1<<13);<br>+ tmp &= ~(3 << 13);<br>+ tmp |= (1 << 9) | (1 << 13);<br> MCHBAR32(0x1400) = tmp;<br> <br> tmp = MCHBAR32(0x140c);<br>- tmp &= ~(0xff | (1<<11) | (1<<12) |<br>- (1<<16) | (1<<18) | (1<<27) | (0xf<<28));<br>- tmp |= (1<<7) | (1<<11) | (1<<16);<br>+ tmp &= ~(0xff | (1 << 11) | (1 << 12) |<br>+ (1 << 16) | (1 << 18) | (1 << 27) | (0xf << 28));<br>+ tmp |= (1 << 7) | (1 << 11) | (1 << 16);<br> switch (ddr3clock) {<br> case MEM_CLOCK_667MT:<br> tmp |= 9 << 28;<br>@@ -1491,8 +1491,8 @@<br> MCHBAR32(0x1440) &= ~1;<br> <br> tmp = MCHBAR32(0x1414);<br>- tmp &= ~((1<<20) | (7<<11) | (0xf << 24) | (0xf << 16));<br>- tmp |= (3<<11);<br>+ tmp &= ~((1 << 20) | (7 << 11) | (0xf << 24) | (0xf << 16));<br>+ tmp |= (3 << 11);<br> switch (ddr3clock) {<br> case MEM_CLOCK_667MT:<br> tmp |= (2 << 24) | (10 << 16);<br>@@ -1506,11 +1506,11 @@<br> }<br> MCHBAR32(0x1414) = tmp;<br> <br>- MCHBAR32(0x1418) &= ~((1<<3) | (1<<11) | (1<<19) | (1<<27));<br>+ MCHBAR32(0x1418) &= ~((1 << 3) | (1 << 11) | (1 << 19) | (1 << 27));<br> <br>- MCHBAR32(0x141c) &= ~((1<<3) | (1<<11) | (1<<19) | (1<<27));<br>+ MCHBAR32(0x141c) &= ~((1 << 3) | (1 << 11) | (1 << 19) | (1 << 27));<br> <br>- MCHBAR32(0x1428) |= 1<<14;<br>+ MCHBAR32(0x1428) |= 1 << 14;<br> <br> tmp = MCHBAR32(0x142c);<br> tmp &= ~((0xf << 8) | (0x7 << 20) | 0xf | (0xf << 24));<br>diff --git a/src/northbridge/intel/haswell/northbridge.c b/src/northbridge/intel/haswell/northbridge.c<br>index a8c8015..79434b3 100644<br>--- a/src/northbridge/intel/haswell/northbridge.c<br>+++ b/src/northbridge/intel/haswell/northbridge.c<br>@@ -202,7 +202,7 @@<br> uint64_t mask;<br> <br> /* All registers are on a 1MiB granularity. */<br>- mask = ((1ULL<<20)-1);<br>+ mask = ((1ULL << 20)-1);<br> mask = ~mask;<br> <br> value = 0;<br>diff --git a/src/northbridge/intel/i3100/memory_initialized.c b/src/northbridge/intel/i3100/memory_initialized.c<br>index 6af7b9b..d39593f 100644<br>--- a/src/northbridge/intel/i3100/memory_initialized.c<br>+++ b/src/northbridge/intel/i3100/memory_initialized.c<br>@@ -20,5 +20,5 @@<br> {<br> u32 drc;<br> drc = pci_read_config32(NB_DEV, DRC);<br>- return (drc & (1<<29));<br>+ return (drc & (1 << 29));<br> }<br>diff --git a/src/northbridge/intel/i3100/pciexp_porta.c b/src/northbridge/intel/i3100/pciexp_porta.c<br>index 3f4939c..3bad28c 100644<br>--- a/src/northbridge/intel/i3100/pciexp_porta.c<br>+++ b/src/northbridge/intel/i3100/pciexp_porta.c<br>@@ -49,15 +49,15 @@<br> do {<br> val = pci_read_config16(dev, 0x76);<br> printk(BIOS_DEBUG, "pcie porta 0x76: %02x\n", val);<br>- if ((val & (1<<10)) && (!flag)) { /* training error */<br>+ if ((val & (1 << 10)) && (!flag)) { /* training error */<br> ctl = pci_read_config16(dev, 0x74);<br>- pci_write_config16(dev, 0x74, (ctl | (1<<5)));<br>+ pci_write_config16(dev, 0x74, (ctl | (1 << 5)));<br> val = pci_read_config16(dev, 0x76);<br> printk(BIOS_DEBUG, "pcie porta reset 0x76: %02x\n", val);<br> flag = 1;<br> hard_reset();<br> }<br>- } while (val & (3<<10));<br>+ } while (val & (3 << 10));<br> <br> pciexp_scan_bridge(dev);<br> }<br>diff --git a/src/northbridge/intel/i3100/pciexp_porta_ep80579.c b/src/northbridge/intel/i3100/pciexp_porta_ep80579.c<br>index 62f485d..df755e7 100644<br>--- a/src/northbridge/intel/i3100/pciexp_porta_ep80579.c<br>+++ b/src/northbridge/intel/i3100/pciexp_porta_ep80579.c<br>@@ -42,8 +42,8 @@<br> <br> printk(BIOS_SPEW, "configure PCIe port as \"Slot Implemented\"\n");<br> val = pci_read_config16(dev, 0x66);<br>- val &= ~(1<<8);<br>- val |= 1<<8;<br>+ val &= ~(1 << 8);<br>+ val |= 1 << 8;<br> pci_write_config16(dev, 0x66, val);<br> <br> /* Todo configure the PCIe bootstrap mode (covered by Intel NDA) */<br>@@ -71,15 +71,15 @@<br> do {<br> val = pci_read_config16(dev, 0x76);<br> printk(BIOS_DEBUG, "pcie porta 0x76: %02x\n", val);<br>- if ((val & (1<<11)) && (!flag)) { /* training error */<br>+ if ((val & (1 << 11)) && (!flag)) { /* training error */<br> ctl = pci_read_config16(dev, 0x74);<br>- pci_write_config16(dev, 0x74, (ctl | (1<<5)));<br>+ pci_write_config16(dev, 0x74, (ctl | (1 << 5)));<br> val = pci_read_config16(dev, 0x76);<br> printk(BIOS_DEBUG, "pcie porta reset 0x76: %02x\n", val);<br> flag = 1;<br> hard_reset();<br> }<br>- } while (val & (3<<10));<br>+ } while (val & (3 << 10));<br> <br> pciexp_scan_bridge(dev);<br> }<br>diff --git a/src/northbridge/intel/i3100/raminit.c b/src/northbridge/intel/i3100/raminit.c<br>index aebe4e8..edadbb9 100644<br>--- a/src/northbridge/intel/i3100/raminit.c<br>+++ b/src/northbridge/intel/i3100/raminit.c<br>@@ -54,7 +54,7 @@<br> PCI_ADDR(0, 0x00, 0, PAM+3), 0xcccccccc, 0x33333333,<br> <br> /* 0xf4 */<br>- PCI_ADDR(0, 0x00, 0, DEVPRES1), 0xffbffff, (1<<22)|(6<<2) | DEVPRES1_CONFIG,<br>+ PCI_ADDR(0, 0x00, 0, DEVPRES1), 0xffbffff, (1 << 22)|(6 << 2) | DEVPRES1_CONFIG,<br> <br> /* 0x14 */<br> PCI_ADDR(0, 0x00, 0, IURBASE), 0x00000fff, (uintptr_t)(MCBAR + 0),<br>@@ -309,9 +309,9 @@<br> break;<br> }<br> <br>- drt |= (1<<6); /* back to back write turn around */<br>+ drt |= (1 << 6); /* back to back write turn around */<br> <br>- drt |= (3<<18); /* Trasmax */<br>+ drt |= (3 << 18); /* Trasmax */<br> <br> for (cnt = 0; cnt < 4; cnt++) {<br> if (!(dimm_mask & (1 << cnt))) {<br>@@ -355,22 +355,22 @@<br> reg = spd_read_byte(ctrl->channel0[cnt], 28)&0x0ff;<br> if (((index>>16) & 0x0ff) < reg) {<br> index &= ~(0x0ff << 16);<br>- index |= (reg<<16);<br>+ index |= (reg << 16);<br> }<br> reg = spd_read_byte(ctrl->channel0[cnt], 29)&0x0ff;<br> if (((index2>>0) & 0x0ff) < reg) {<br> index2 &= ~(0x0ff << 0);<br>- index2 |= (reg<<0);<br>+ index2 |= (reg << 0);<br> }<br> reg = spd_read_byte(ctrl->channel0[cnt], 41)&0x0ff;<br> if (((index2>>8) & 0x0ff) < reg) {<br> index2 &= ~(0x0ff << 8);<br>- index2 |= (reg<<8);<br>+ index2 |= (reg << 8);<br> }<br> reg = spd_read_byte(ctrl->channel0[cnt], 42)&0x0ff;<br> if (((index2>>16) & 0x0ff) < reg) {<br> index2 &= ~(0x0ff << 16);<br>- index2 |= (reg<<16);<br>+ index2 |= (reg << 16);<br> }<br> }<br> <br>@@ -378,151 +378,151 @@<br> value = cycle_time[drc & 3];<br> if (value <= 0x50) { /* 200 MHz */<br> if ((index & 7) > 2) {<br>- drt |= (2<<2); /* CAS latency 4 */<br>+ drt |= (2 << 2); /* CAS latency 4 */<br> cas_latency = 40;<br> } else {<br>- drt |= (1<<2); /* CAS latency 3 */<br>+ drt |= (1 << 2); /* CAS latency 3 */<br> cas_latency = 30;<br> }<br> if ((index & 0x0ff00) <= 0x03c00) {<br>- drt |= (1<<8); /* Trp RAS Precharge */<br>+ drt |= (1 << 8); /* Trp RAS Precharge */<br> } else {<br>- drt |= (2<<8); /* Trp RAS Precharge */<br>+ drt |= (2 << 8); /* Trp RAS Precharge */<br> }<br> <br> /* Trcd RAS to CAS delay */<br> if ((index2 & 0x0ff) <= 0x03c) {<br>- drt |= (0<<10);<br>+ drt |= (0 << 10);<br> } else {<br>- drt |= (1<<10);<br>+ drt |= (1 << 10);<br> }<br> <br> /* Tdal Write auto precharge recovery delay */<br>- drt |= (1<<12);<br>+ drt |= (1 << 12);<br> <br> /* Trc TRS min */<br> if ((index2 & 0x0ff00) <= 0x03700)<br>- drt |= (0<<14);<br>+ drt |= (0 << 14);<br> else if ((index2 & 0xff00) <= 0x03c00)<br>- drt |= (1<<14);<br>+ drt |= (1 << 14);<br> else<br>- drt |= (2<<14); /* spd 41 */<br>+ drt |= (2 << 14); /* spd 41 */<br> <br>- drt |= (2<<16); /* Twr not defined for DDR docs say use 2 */<br>+ drt |= (2 << 16); /* Twr not defined for DDR docs say use 2 */<br> <br> /* Trrd Row Delay */<br> if ((index & 0x0ff0000) <= 0x0140000) {<br>- drt |= (0<<20);<br>+ drt |= (0 << 20);<br> } else if ((index & 0x0ff0000) <= 0x0280000) {<br>- drt |= (1<<20);<br>+ drt |= (1 << 20);<br> } else if ((index & 0x0ff0000) <= 0x03c0000) {<br>- drt |= (2<<20);<br>+ drt |= (2 << 20);<br> } else {<br>- drt |= (3<<20);<br>+ drt |= (3 << 20);<br> }<br> <br> /* Trfc Auto refresh cycle time */<br> if ((index2 & 0x0ff0000) <= 0x04b0000) {<br>- drt |= (0<<22);<br>+ drt |= (0 << 22);<br> } else if ((index2 & 0x0ff0000) <= 0x0690000) {<br>- drt |= (1<<22);<br>+ drt |= (1 << 22);<br> } else {<br>- drt |= (2<<22);<br>+ drt |= (2 << 22);<br> }<br> /* Docs say use 55 for all 200MHz */<br>- drt |= (0x055<<24);<br>+ drt |= (0x055 << 24);<br> }<br> else if (value <= 0x60) { /* 167 MHz */<br> /* according to new documentation CAS latency is 00<br> * for bits 3:2 for all 167 MHz<br> drt |= ((index & 3)<<2); */ /* set CAS latency */<br> if ((index & 0x0ff00) <= 0x03000) {<br>- drt |= (1<<8); /* Trp RAS Precharge */<br>+ drt |= (1 << 8); /* Trp RAS Precharge */<br> } else {<br>- drt |= (2<<8); /* Trp RAS Precharge */<br>+ drt |= (2 << 8); /* Trp RAS Precharge */<br> }<br> <br> /* Trcd RAS to CAS delay */<br> if ((index2 & 0x0ff) <= 0x030) {<br>- drt |= (0<<10);<br>+ drt |= (0 << 10);<br> } else {<br>- drt |= (1<<10);<br>+ drt |= (1 << 10);<br> }<br> <br> /* Tdal Write auto precharge recovery delay */<br>- drt |= (2<<12);<br>+ drt |= (2 << 12);<br> <br> /* Trc TRS min */<br>- drt |= (2<<14); /* spd 41, but only one choice */<br>+ drt |= (2 << 14); /* spd 41, but only one choice */<br> <br>- drt |= (2<<16); /* Twr not defined for DDR docs say 2 */<br>+ drt |= (2 << 16); /* Twr not defined for DDR docs say 2 */<br> <br> /* Trrd Row Delay */<br> if ((index & 0x0ff0000) <= 0x0180000) {<br>- drt |= (0<<20);<br>+ drt |= (0 << 20);<br> } else if ((index & 0x0ff0000) <= 0x0300000) {<br>- drt |= (1<<20);<br>+ drt |= (1 << 20);<br> } else {<br>- drt |= (2<<20);<br>+ drt |= (2 << 20);<br> }<br> <br> /* Trfc Auto refresh cycle time */<br> if ((index2 & 0x0ff0000) <= 0x0480000) {<br>- drt |= (0<<22);<br>+ drt |= (0 << 22);<br> } else if ((index2 & 0x0ff0000) <= 0x0780000) {<br>- drt |= (2<<22);<br>+ drt |= (2 << 22);<br> } else {<br>- drt |= (2<<22);<br>+ drt |= (2 << 22);<br> }<br> /* Docs state to use 99 for all 167 MHz */<br>- drt |= (0x099<<24);<br>+ drt |= (0x099 << 24);<br> }<br> else if (value <= 0x75) { /* 133 MHz */<br> drt |= ((index & 3)<<2); /* set CAS latency */<br> if ((index & 0x0ff00) <= 0x03c00) {<br>- drt |= (1<<8); /* Trp RAS Precharge */<br>+ drt |= (1 << 8); /* Trp RAS Precharge */<br> } else {<br>- drt |= (2<<8); /* Trp RAS Precharge */<br>+ drt |= (2 << 8); /* Trp RAS Precharge */<br> }<br> <br> /* Trcd RAS to CAS delay */<br> if ((index2 & 0x0ff) <= 0x03c) {<br>- drt |= (0<<10);<br>+ drt |= (0 << 10);<br> } else {<br>- drt |= (1<<10);<br>+ drt |= (1 << 10);<br> }<br> <br> /* Tdal Write auto precharge recovery delay */<br>- drt |= (1<<12);<br>+ drt |= (1 << 12);<br> <br> /* Trc TRS min */<br>- drt |= (2<<14); /* spd 41, but only one choice */<br>+ drt |= (2 << 14); /* spd 41, but only one choice */<br> <br>- drt |= (1<<16); /* Twr not defined for DDR docs say 1 */<br>+ drt |= (1 << 16); /* Twr not defined for DDR docs say 1 */<br> <br> /* Trrd Row Delay */<br> if ((index & 0x0ff0000) <= 0x01e0000) {<br>- drt |= (0<<20);<br>+ drt |= (0 << 20);<br> } else if ((index & 0x0ff0000) <= 0x03c0000) {<br>- drt |= (1<<20);<br>+ drt |= (1 << 20);<br> } else {<br>- drt |= (2<<20);<br>+ drt |= (2 << 20);<br> }<br> <br> /* Trfc Auto refresh cycle time */<br> if ((index2 & 0x0ff0000) <= 0x04b0000) {<br>- drt |= (0<<22);<br>+ drt |= (0 << 22);<br> } else if ((index2 & 0x0ff0000) <= 0x0780000) {<br>- drt |= (2<<22);<br>+ drt |= (2 << 22);<br> } else {<br>- drt |= (2<<22);<br>+ drt |= (2 << 22);<br> }<br> <br> /* Based on CAS latency */<br> if (index & 7)<br>- drt |= (0x099<<24);<br>+ drt |= (0x099 << 24);<br> else<br>- drt |= (0x055<<24);<br>+ drt |= (0x055 << 24);<br> <br> }<br> else {<br>@@ -693,7 +693,7 @@<br> <br> for (i = 0; i < 1001; i++) {<br> data32 = read32(MCBAR+DCALCSR);<br>- if (!(data32 & (1<<31)))<br>+ if (!(data32 & (1 << 31)))<br> break;<br> }<br> }<br>@@ -725,7 +725,7 @@<br> <br> for (i = 0; i < 1001; i++) {<br> data32 = read32(MCBAR+DCALCSR);<br>- if (!(data32 & (1<<31)))<br>+ if (!(data32 & (1 << 31)))<br> break;<br> }<br> if (i >= 1000)<br>@@ -753,7 +753,7 @@<br> work32l = dcal_data32_1,work32h = dcal_data32_3;<br> (i < 4) && bit; i++) {<br> for (;;bit--,cnt--) {<br>- if (work32l & (1<<cnt))<br>+ if (work32l & (1 << cnt))<br> break;<br> if (!cnt) {<br> work32l = dcal_data32_0;<br>@@ -763,7 +763,7 @@<br> if (!bit) break;<br> }<br> for (;;bit--,cnt--) {<br>- if (!(work32l & (1<<cnt)))<br>+ if (!(work32l & (1 << cnt)))<br> break;<br> if (!cnt) {<br> work32l = dcal_data32_0;<br>@@ -776,7 +776,7 @@<br> break;<br> }<br> data32 = ((bit%8) << 1);<br>- if (work32h & (1<<cnt))<br>+ if (work32h & (1 << cnt))<br> data32 += 1;<br> if (data32 < 4) {<br> if (!edge) {<br>@@ -808,10 +808,10 @@<br> recen = recen>>2;<br> for (cnt = 5; cnt < 24;) {<br> for (;; cnt++)<br>- if (!(work32l & (1<<cnt)))<br>+ if (!(work32l & (1 << cnt)))<br> break;<br> for (;; cnt++) {<br>- if (work32l & (1<<cnt))<br>+ if (work32l & (1 << cnt))<br> break;<br> }<br> data32 = (((cnt-1)%8)<<1);<br>@@ -866,16 +866,16 @@<br> if (cnt > 1) {<br> for (i = 0; i < 32; i+=8) {<br> if (((recena>>i)&0x0f)>7) {<br>- recena &= ~(0x0f<<i);<br>- recena |= (7<<i);<br>+ recena &= ~(0x0f << i);<br>+ recena |= (7 << i);<br> }<br> }<br> }<br> else {<br> for (i = 0; i < 32; i+=8) {<br> if (((recena>>i)&0x0f)<8) {<br>- recena &= ~(0x0f<<i);<br>- recena |= (8<<i);<br>+ recena &= ~(0x0f << i);<br>+ recena |= (8 << i);<br> }<br> }<br> }<br>@@ -895,16 +895,16 @@<br> if (cnt > 1) {<br> for (i = 0; i < 32; i+=8) {<br> if (((recenb>>i)&0x0f)>7) {<br>- recenb &= ~(0x0f<<i);<br>- recenb |= (7<<i);<br>+ recenb &= ~(0x0f << i);<br>+ recenb |= (7 << i);<br> }<br> }<br> }<br> else {<br> for (i = 0; i < 32; i+=8) {<br> if (((recenb>>8)&0x0f)<8) {<br>- recenb &= ~(0x0f<<i);<br>- recenb |= (8<<i);<br>+ recenb &= ~(0x0f << i);<br>+ recenb |= (8 << i);<br> }<br> }<br> }<br>@@ -1016,8 +1016,8 @@<br> /* Apply NOP */<br> do_delay();<br> <br>- write32(MCBAR+DCALCSR, (0x01000000 | (i<<20)));<br>- write32(MCBAR+DCALCSR, (0x81000000 | (i<<20)));<br>+ write32(MCBAR+DCALCSR, (0x01000000 | (i << 20)));<br>+ write32(MCBAR+DCALCSR, (0x81000000 | (i << 20)));<br> <br> do data32 = read32(MCBAR+DCALCSR);<br> while (data32 & 0x80000000);<br>@@ -1027,7 +1027,7 @@<br> do_delay();<br> <br> for (cs = 0; cs < 8; cs+=2) {<br>- write32(MCBAR + DCALCSR, (0x81000000 | (cs<<20)));<br>+ write32(MCBAR + DCALCSR, (0x81000000 | (cs << 20)));<br> do data32 = read32(MCBAR+DCALCSR);<br> while (data32 & 0x80000000);<br> }<br>@@ -1036,7 +1036,7 @@<br> do_delay();<br> for (cs = 0; cs < 8; cs+=2) {<br> write32(MCBAR+DCALADDR, 0x04000000);<br>- write32(MCBAR+DCALCSR, (0x81000002 | (cs<<20)));<br>+ write32(MCBAR+DCALCSR, (0x81000002 | (cs << 20)));<br> do data32 = read32(MCBAR+DCALCSR);<br> while (data32 & 0x80000000);<br> }<br>@@ -1046,7 +1046,7 @@<br> for (cs = 0; cs < 8; cs+=2) {<br> /* fixme hard code AL additive latency */<br> write32(MCBAR+DCALADDR, 0x0b940001);<br>- write32(MCBAR+DCALCSR, (0x81000003 | (cs<<20)));<br>+ write32(MCBAR+DCALCSR, (0x81000003 | (cs << 20)));<br> do data32 = read32(MCBAR+DCALCSR);<br> while (data32 & 0x80000000);<br> }<br>@@ -1058,7 +1058,7 @@<br> mode_reg = 0x054a0000;<br> for (cs = 0; cs < 8; cs+=2) {<br> write32(MCBAR+DCALADDR, mode_reg);<br>- write32(MCBAR+DCALCSR, (0x81000003 | (cs<<20)));<br>+ write32(MCBAR+DCALCSR, (0x81000003 | (cs << 20)));<br> do data32 = read32(MCBAR+DCALCSR);<br> while (data32 & 0x80000000);<br> }<br>@@ -1069,7 +1069,7 @@<br> do_delay();<br> for (cs = 0; cs < 8; cs+=2) {<br> write32(MCBAR+DCALADDR, 0x04000000);<br>- write32(MCBAR+DCALCSR, (0x81000002 | (cs<<20)));<br>+ write32(MCBAR+DCALCSR, (0x81000002 | (cs << 20)));<br> do data32 = read32(MCBAR+DCALCSR);<br> while (data32 & 0x80000000);<br> }<br>@@ -1077,47 +1077,47 @@<br> /* Do 2 refreshes */<br> do_delay();<br> for (cs = 0; cs < 8; cs+=2) {<br>- write32(MCBAR+DCALCSR, (0x81000001 | (cs<<20)));<br>+ write32(MCBAR+DCALCSR, (0x81000001 | (cs << 20)));<br> do data32 = read32(MCBAR+DCALCSR);<br> while (data32 & 0x80000000);<br> }<br> do_delay();<br> for (cs = 0; cs < 8; cs+=2) {<br>- write32(MCBAR+DCALCSR, (0x81000001 | (cs<<20)));<br>+ write32(MCBAR+DCALCSR, (0x81000001 | (cs << 20)));<br> do data32 = read32(MCBAR+DCALCSR);<br> while (data32 & 0x80000000);<br> }<br> do_delay();<br> /* for good luck do 6 more */<br> for (cs = 0; cs < 8; cs+=2) {<br>- write32(MCBAR+DCALCSR, (0x81000001 | (cs<<20)));<br>+ write32(MCBAR+DCALCSR, (0x81000001 | (cs << 20)));<br> }<br> do_delay();<br> for (cs = 0; cs < 8; cs+=2) {<br>- write32(MCBAR+DCALCSR, (0x81000001 | (cs<<20)));<br>+ write32(MCBAR+DCALCSR, (0x81000001 | (cs << 20)));<br> }<br> do_delay();<br> for (cs = 0; cs < 8; cs+=2) {<br>- write32(MCBAR+DCALCSR, (0x81000001 | (cs<<20)));<br>+ write32(MCBAR+DCALCSR, (0x81000001 | (cs << 20)));<br> }<br> do_delay();<br> for (cs = 0; cs < 8; cs+=2) {<br>- write32(MCBAR+DCALCSR, (0x81000001 | (cs<<20)));<br>+ write32(MCBAR+DCALCSR, (0x81000001 | (cs << 20)));<br> }<br> do_delay();<br> for (cs = 0; cs < 8; cs+=2) {<br>- write32(MCBAR+DCALCSR, (0x81000001 | (cs<<20)));<br>+ write32(MCBAR+DCALCSR, (0x81000001 | (cs << 20)));<br> }<br> do_delay();<br> for (cs = 0; cs < 8; cs+=2) {<br>- write32(MCBAR+DCALCSR, (0x81000001 | (cs<<20)));<br>+ write32(MCBAR+DCALCSR, (0x81000001 | (cs << 20)));<br> }<br> do_delay();<br> /* MRS reset dll's normal */<br> do_delay();<br> for (cs = 0; cs < 8; cs+=2) {<br>- write32(MCBAR+DCALADDR, (mode_reg & ~(1<<24)));<br>- write32(MCBAR+DCALCSR, (0x81000003 | (cs<<20)));<br>+ write32(MCBAR+DCALADDR, (mode_reg & ~(1 << 24)));<br>+ write32(MCBAR+DCALCSR, (0x81000003 | (cs << 20)));<br> do data32 = read32(MCBAR+DCALCSR);<br> while (data32 & 0x80000000);<br> }<br>@@ -1126,7 +1126,7 @@<br> do_delay();<br> for (cs = 0; cs < 8; cs+=2) {<br> write32(MCBAR+DCALADDR, (0x0b940001));<br>- write32(MCBAR+DCALCSR, (0x81000003 | (cs<<20)));<br>+ write32(MCBAR+DCALCSR, (0x81000003 | (cs << 20)));<br> do data32 = read32(MCBAR+DCALCSR);<br> while (data32 & 0x80000000);<br> }<br>@@ -1161,7 +1161,7 @@<br> }<br> <br> for (cs = 0; cs < 8; cs+=2) {<br>- write32(MCBAR+DCALCSR, (0x810831d8 | (cs<<20)));<br>+ write32(MCBAR+DCALCSR, (0x810831d8 | (cs << 20)));<br> do data32 = read32(MCBAR+DCALCSR);<br> while (data32 & 0x80000000);<br> }<br>@@ -1174,7 +1174,7 @@<br> printk(BIOS_DEBUG, "Waiting for mem complete\n");<br> while (1) {<br> data32 = pci_read_config32(ctrl->f0, 0x98);<br>- if ( (data32 & (1<<31)) == 0)<br>+ if ( (data32 & (1 << 31)) == 0)<br> break;<br> }<br> printk(BIOS_DEBUG, "Done\n");<br>diff --git a/src/northbridge/intel/i3100/raminit_ep80579.c b/src/northbridge/intel/i3100/raminit_ep80579.c<br>index fa557da..bbd8237 100644<br>--- a/src/northbridge/intel/i3100/raminit_ep80579.c<br>+++ b/src/northbridge/intel/i3100/raminit_ep80579.c<br>@@ -604,7 +604,7 @@<br> udelay(16);<br> for (cs = 0; cs < 2; cs++) {<br> printk(BIOS_DEBUG, "MRS CS%d\n", cs);<br>- write32(BAR+DCALADDR, (mode_reg & ~(1<<24)));<br>+ write32(BAR+DCALADDR, (mode_reg & ~(1 << 24)));<br> write32(BAR+DCALCSR, (0x80000003 | ((cs+1)<<21)));<br> do data32 = read32(BAR+DCALCSR);<br> while (data32 & 0x80000000);<br>@@ -656,10 +656,10 @@<br> <br> /* Clear memory and init ECC */<br> for (cs = 0; cs < 2; cs++) {<br>- if (!(mask & (1<<cs)))<br>+ if (!(mask & (1 << cs)))<br> continue;<br> printk(BIOS_DEBUG, "clear memory CS%d\n", cs);<br>- write32(BAR+MBCSR, 0xa00000f0 | ((cs+1)<<20) | (0<<16));<br>+ write32(BAR+MBCSR, 0xa00000f0 | ((cs+1)<<20) | (0 << 16));<br> do data32 = read32(BAR+MBCSR);<br> while (data32 & 0x80000000);<br> if (data32 & 0x40000000)<br>@@ -668,9 +668,9 @@<br> <br> /* Clear read/write FIFO pointers */<br> printk(BIOS_DEBUG, "clear read/write fifo pointers\n");<br>- write32(BAR+DDRIOMC2, read32(BAR+DDRIOMC2) | (1<<15));<br>+ write32(BAR+DDRIOMC2, read32(BAR+DDRIOMC2) | (1 << 15));<br> udelay(16);<br>- write32(BAR+DDRIOMC2, read32(BAR+DDRIOMC2) & ~(1<<15));<br>+ write32(BAR+DDRIOMC2, read32(BAR+DDRIOMC2) & ~(1 << 15));<br> udelay(16);<br> <br> dump_dcal_regs();<br>diff --git a/src/northbridge/intel/i82830/memory_initialized.c b/src/northbridge/intel/i82830/memory_initialized.c<br>index 7ccc1a6..f77de3c 100644<br>--- a/src/northbridge/intel/i82830/memory_initialized.c<br>+++ b/src/northbridge/intel/i82830/memory_initialized.c<br>@@ -22,5 +22,5 @@<br> {<br> u32 drc;<br> drc = pci_read_config32(NB_DEV, DRC);<br>- return (drc & (1<<29));<br>+ return (drc & (1 << 29));<br> }<br>diff --git a/src/northbridge/intel/i945/gma.c b/src/northbridge/intel/i945/gma.c<br>index 3c5cee5..104b958 100644<br>--- a/src/northbridge/intel/i945/gma.c<br>+++ b/src/northbridge/intel/i945/gma.c<br>@@ -37,10 +37,10 @@<br> #define LVDS_CLOCK_A_POWERUP_ALL (3 << 8)<br> #define LVDS_CLOCK_B_POWERUP_ALL (3 << 4)<br> #define LVDS_CLOCK_BOTH_POWERUP_ALL (3 << 2)<br>-#define DISPPLANE_BGRX888 (0x6<<26)<br>+#define DISPPLANE_BGRX888 (0x6 << 26)<br> #define DPLLB_LVDS_P2_CLOCK_DIV_7 (1 << 24) /* i915 */<br> <br>-#define DPLL_INTEGRATED_CRI_CLK_VLV (1<<14)<br>+#define DPLL_INTEGRATED_CRI_CLK_VLV (1 << 14)<br> <br> #define PGETBL_CTL 0x2020<br> #define PGETBL_ENABLED 0x00000001<br>diff --git a/src/northbridge/intel/i945/raminit.c b/src/northbridge/intel/i945/raminit.c<br>index b4c7d13..d311958 100644<br>--- a/src/northbridge/intel/i945/raminit.c<br>+++ b/src/northbridge/intel/i945/raminit.c<br>@@ -70,7 +70,7 @@<br> u32 reg32;<br> <br> reg32 = MCHBAR32(DCC);<br>- reg32 &= ~((3<<21) | (1<<20) | (1<<19) | (7 << 16));<br>+ reg32 &= ~((3 << 21) | (1 << 20) | (1 << 19) | (7 << 16));<br> reg32 |= command;<br> <br> /* Also set Init Complete */<br>@@ -248,8 +248,8 @@<br> <br> reg8 = pci_read_config8(PCI_DEV(0, 0x1f, 0), 0xa2);<br> <br>- if (reg8 & ((1<<7)|(1<<2))) {<br>- if (reg8 & (1<<2)) {<br>+ if (reg8 & ((1 << 7)|(1 << 2))) {<br>+ if (reg8 & (1 << 2)) {<br> printk(BIOS_DEBUG, "SLP S4# Assertion Width Violation.\n");<br> /* Write back clears bit 2 */<br> pci_write_config8(PCI_DEV(0, 0x1f, 0), 0xa2, reg8);<br>@@ -257,9 +257,9 @@<br> <br> }<br> <br>- if (reg8 & (1<<7)) {<br>+ if (reg8 & (1 << 7)) {<br> printk(BIOS_DEBUG, "DRAM initialization was interrupted.\n");<br>- reg8 &= ~(1<<7);<br>+ reg8 &= ~(1 << 7);<br> pci_write_config8(PCI_DEV(0, 0x1f, 0), 0xa2, reg8);<br> do_reset = 1;<br> }<br>@@ -279,7 +279,7 @@<br> <br> /* Set DRAM initialization bit in ICH7 */<br> reg8 = pci_read_config8(PCI_DEV(0, 0x1f, 0), 0xa2);<br>- reg8 |= (1<<7);<br>+ reg8 |= (1 << 7);<br> pci_write_config8(PCI_DEV(0, 0x1f, 0), 0xa2, reg8);<br> <br> /* clear self refresh status if check is disabled or not a resume */<br>@@ -289,12 +289,12 @@<br> /* Validate self refresh config */<br> if (((sysinfo->dimm[0] != SYSINFO_DIMM_NOT_POPULATED) ||<br> (sysinfo->dimm[1] != SYSINFO_DIMM_NOT_POPULATED)) &&<br>- !(MCHBAR8(SLFRCS) & (1<<0))) {<br>+ !(MCHBAR8(SLFRCS) & (1 << 0))) {<br> do_reset = 1;<br> }<br> if (((sysinfo->dimm[2] != SYSINFO_DIMM_NOT_POPULATED) ||<br> (sysinfo->dimm[3] != SYSINFO_DIMM_NOT_POPULATED)) &&<br>- !(MCHBAR8(SLFRCS) & (1<<1))) {<br>+ !(MCHBAR8(SLFRCS) & (1 << 1))) {<br> do_reset = 1;<br> }<br> }<br>@@ -2065,7 +2065,7 @@<br> <br> /* Gate graphics hardware for frequency change */<br> reg8 = pci_read_config16(PCI_DEV(0, 2, 0), GCFC + 1);<br>- reg8 = (1<<3) | (1<<1); /* disable crclk, gate cdclk */<br>+ reg8 = (1 << 3) | (1 << 1); /* disable crclk, gate cdclk */<br> pci_write_config8(PCI_DEV(0, 2, 0), GCFC + 1, reg8);<br> <br> /* Get graphics frequency capabilities */<br>@@ -2142,7 +2142,7 @@<br> <br> /* Graphics Core Display Clock */<br> reg8 = pci_read_config8(PCI_DEV(0, 2, 0), GCFC);<br>- reg8 &= ~((1<<7) | (7<<4));<br>+ reg8 &= ~((1 << 7) | (7 << 4));<br> <br> if (voltage == VOLTAGE_1_05) {<br> reg8 |= CDCLK_200MHz;<br>@@ -2155,7 +2155,7 @@<br> <br> reg8 = pci_read_config8(PCI_DEV(0, 2, 0), GCFC + 1);<br> <br>- reg8 |= (1<<3) | (1<<1);<br>+ reg8 |= (1 << 3) | (1 << 1);<br> pci_write_config8(PCI_DEV(0, 2, 0), GCFC + 1, reg8);<br> <br> reg8 |= 0x0f;<br>diff --git a/src/northbridge/intel/pineview/raminit.c b/src/northbridge/intel/pineview/raminit.c<br>index 8bf685d..2fc26e7 100644<br>--- a/src/northbridge/intel/pineview/raminit.c<br>+++ b/src/northbridge/intel/pineview/raminit.c<br>@@ -71,9 +71,9 @@<br> for (idx = 0; idx < TOTAL_DIMMS; ++idx)<br> #define FOR_EACH_POPULATED_DIMM(dimms, idx) \<br> FOR_EACH_DIMM(idx) IF_DIMM_POPULATED(dimms, idx)<br>-#define CHANNEL_IS_POPULATED(dimms, idx) ((dimms[idx<<1].card_type != 0) || (dimms[(idx<<1) + 1].card_type != 0))<br>-#define CHANNEL_IS_CARDF(dimms, idx) ((dimms[idx<<1].card_type == 0xf) || (dimms[(idx<<1) + 1].card_type == 0xf))<br>-#define IF_CHANNEL_POPULATED(dimms, idx) if ((dimms[idx<<1].card_type != 0) || (dimms[(idx<<1) + 1].card_type != 0))<br>+#define CHANNEL_IS_POPULATED(dimms, idx) ((dimms[idx << 1].card_type != 0) || (dimms[(idx << 1) + 1].card_type != 0))<br>+#define CHANNEL_IS_CARDF(dimms, idx) ((dimms[idx << 1].card_type == 0xf) || (dimms[(idx << 1) + 1].card_type == 0xf))<br>+#define IF_CHANNEL_POPULATED(dimms, idx) if ((dimms[idx << 1].card_type != 0) || (dimms[(idx << 1) + 1].card_type != 0))<br> #define FOR_EACH_CHANNEL(idx) \<br> for (idx = 0; idx < TOTAL_CHANNELS; ++idx)<br> #define FOR_EACH_POPULATED_CHANNEL(dimms, idx) \<br>@@ -92,10 +92,10 @@<br> <br> static bool rank_is_populated(struct dimminfo dimms[], u8 ch, u8 r)<br> {<br>- return ((dimms[ch<<1].card_type && ((r) < dimms[ch<<1].ranks))<br>- || (dimms[(ch<<1) + 1].card_type<br>+ return ((dimms[ch << 1].card_type && ((r) < dimms[ch << 1].ranks))<br>+ || (dimms[(ch << 1) + 1].card_type<br> && ((r) >= 2)<br>- && ((r) < (dimms[(ch<<1) + 1].ranks + 2))));<br>+ && ((r) < (dimms[(ch << 1) + 1].ranks + 2))));<br> }<br> <br> static inline void barrier(void)<br>diff --git a/src/northbridge/intel/sandybridge/raminit_common.h b/src/northbridge/intel/sandybridge/raminit_common.h<br>index ab6e592..54570b2 100644<br>--- a/src/northbridge/intel/sandybridge/raminit_common.h<br>+++ b/src/northbridge/intel/sandybridge/raminit_common.h<br>@@ -145,7 +145,7 @@<br> #define MAX_CAS 18<br> #define MIN_CAS 4<br> <br>-#define MAKE_ERR ((channel<<16)|(slotrank<<8)|1)<br>+#define MAKE_ERR ((channel << 16)|(slotrank << 8)|1)<br> #define GET_ERR_CHANNEL(x) (x>>16)<br> <br> #define MC_BIOS_REQ 0x5e00<br>diff --git a/src/northbridge/intel/x4x/raminit_ddr2.c b/src/northbridge/intel/x4x/raminit_ddr2.c<br>index a4a830d..4d10549 100644<br>--- a/src/northbridge/intel/x4x/raminit_ddr2.c<br>+++ b/src/northbridge/intel/x4x/raminit_ddr2.c<br>@@ -1118,7 +1118,7 @@<br> <br> MCHBAR8(0x271) = (MCHBAR8(0x271) & ~0x3e) | cmd;<br> MCHBAR8(0x671) = (MCHBAR8(0x671) & ~0x3e) | cmd;<br>- rubbish = read32((void *)((val<<3) | addr));<br>+ rubbish = read32((void *)((val << 3) | addr));<br> udelay(10);<br> MCHBAR8(0x271) = (MCHBAR8(0x271) & ~0x3e) | NORMALOP_CMD;<br> MCHBAR8(0x671) = (MCHBAR8(0x671) & ~0x3e) | NORMALOP_CMD;<br>@@ -1582,8 +1582,8 @@<br> rankpop0 = 0;<br> rankpop1 = 0;<br> FOR_EACH_POPULATED_RANK(s->dimms, ch, r) {<br>- if (s->dimms[ch<<1].card_type != RAW_CARD_UNPOPULATED<br>- && (r) < s->dimms[ch<<1].ranks)<br>+ if (s->dimms[ch << 1].card_type != RAW_CARD_UNPOPULATED<br>+ && (r) < s->dimms[ch << 1].ranks)<br> i = ch << 1;<br> else<br> i = (ch << 1) + 1;<br>@@ -1616,8 +1616,8 @@<br> <br> // DRB<br> FOR_EACH_POPULATED_RANK(s->dimms, ch, r) {<br>- if (s->dimms[ch<<1].card_type != RAW_CARD_UNPOPULATED<br>- && (r) < s->dimms[ch<<1].ranks)<br>+ if (s->dimms[ch << 1].card_type != RAW_CARD_UNPOPULATED<br>+ && (r) < s->dimms[ch << 1].ranks)<br> i = ch << 1;<br> else<br> i = (ch << 1) + 1;<br>diff --git a/src/northbridge/intel/x4x/x4x.h b/src/northbridge/intel/x4x/x4x.h<br>index 7d8f5cc..4c16d17 100644<br>--- a/src/northbridge/intel/x4x/x4x.h<br>+++ b/src/northbridge/intel/x4x/x4x.h<br>@@ -165,14 +165,14 @@<br> #define FOR_EACH_POPULATED_DIMM_IN_CHANNEL(dimms, ch, idx) \<br> FOR_EACH_DIMM_IN_CHANNEL(ch, idx) IF_DIMM_POPULATED(dimms, idx)<br> #define CHANNEL_IS_POPULATED(dimms, idx) \<br>- ((dimms[idx<<1].card_type != RAW_CARD_UNPOPULATED) \<br>- || (dimms[(idx<<1) + 1].card_type != RAW_CARD_UNPOPULATED))<br>+ ((dimms[idx << 1].card_type != RAW_CARD_UNPOPULATED) \<br>+ || (dimms[(idx << 1) + 1].card_type != RAW_CARD_UNPOPULATED))<br> #define CHANNEL_IS_CARDF(dimms, idx) \<br>- ((dimms[idx<<1].card_type == 0xf) \<br>- || (dimms[(idx<<1) + 1].card_type == 0xf))<br>+ ((dimms[idx << 1].card_type == 0xf) \<br>+ || (dimms[(idx << 1) + 1].card_type == 0xf))<br> #define IF_CHANNEL_POPULATED(dimms, idx) \<br>- if ((dimms[idx<<1].card_type != RAW_CARD_UNPOPULATED) \<br>- || (dimms[(idx<<1) + 1].card_type != RAW_CARD_UNPOPULATED))<br>+ if ((dimms[idx << 1].card_type != RAW_CARD_UNPOPULATED) \<br>+ || (dimms[(idx << 1) + 1].card_type != RAW_CARD_UNPOPULATED))<br> #define FOR_EACH_CHANNEL(idx) \<br> for (idx = 0; idx < TOTAL_CHANNELS; ++idx)<br> #define FOR_EACH_POPULATED_CHANNEL(dimms, idx) \<br>@@ -180,13 +180,13 @@<br> <br> #define RANKS_PER_CHANNEL 4<br> #define RANK_IS_POPULATED(dimms, ch, r) \<br>- (((dimms[ch<<1].card_type != RAW_CARD_UNPOPULATED) && ((r) < dimms[ch<<1].ranks)) || \<br>- ((dimms[(ch<<1) + 1].card_type != RAW_CARD_UNPOPULATED) && ((r) >= 2) && ((r) < (dimms[(ch<<1) + 1].ranks + 2))))<br>+ (((dimms[ch << 1].card_type != RAW_CARD_UNPOPULATED) && ((r) < dimms[ch << 1].ranks)) || \<br>+ ((dimms[(ch << 1) + 1].card_type != RAW_CARD_UNPOPULATED) && ((r) >= 2) && ((r) < (dimms[(ch << 1) + 1].ranks + 2))))<br> #define IF_RANK_POPULATED(dimms, ch, r) \<br>- if (((dimms[ch<<1].card_type != RAW_CARD_UNPOPULATED) \<br>- && ((r) < dimms[ch<<1].ranks)) \<br>- || ((dimms[(ch<<1) + 1].card_type != RAW_CARD_UNPOPULATED) \<br>- && ((r) >= 2) && ((r) < (dimms[(ch<<1) + 1].ranks + 2))))<br>+ if (((dimms[ch << 1].card_type != RAW_CARD_UNPOPULATED) \<br>+ && ((r) < dimms[ch << 1].ranks)) \<br>+ || ((dimms[(ch << 1) + 1].card_type != RAW_CARD_UNPOPULATED) \<br>+ && ((r) >= 2) && ((r) < (dimms[(ch << 1) + 1].ranks + 2))))<br> #define FOR_EACH_RANK_IN_CHANNEL(r) \<br> for (r = 0; r < RANKS_PER_CHANNEL; ++r)<br> #define FOR_EACH_POPULATED_RANK_IN_CHANNEL(dimms, ch, r) \<br></pre><p>To view, visit <a href="https://review.coreboot.org/20398">change 20398</a>. To unsubscribe, visit <a href="https://review.coreboot.org/settings">settings</a>.</p><div itemscope itemtype="http://schema.org/EmailMessage"><div itemscope itemprop="action" itemtype="http://schema.org/ViewAction"><link itemprop="url" href="https://review.coreboot.org/20398"/><meta itemprop="name" content="View Change"/></div></div>
<div style="display:none"> Gerrit-Project: coreboot </div>
<div style="display:none"> Gerrit-Branch: master </div>
<div style="display:none"> Gerrit-MessageType: newchange </div>
<div style="display:none"> Gerrit-Change-Id: I0bf2653c08c4955bf95dcbec2d5a0c891339866b </div>
<div style="display:none"> Gerrit-Change-Number: 20398 </div>
<div style="display:none"> Gerrit-PatchSet: 1 </div>
<div style="display:none"> Gerrit-Owner: HAOUAS Elyes <ehaouas@noos.fr> </div>