<p>HAOUAS Elyes has uploaded this change for <strong>review</strong>.</p><p><a href="https://review.coreboot.org/20399">View Change</a></p><pre style="font-family: monospace,monospace; white-space: pre-wrap;">northbridge/amd/agesa/*: Add whitespace around '<<'<br><br>Change-Id: I56cb941d07ac48f8209a892ec18af8f5090765f7<br>Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr><br>---<br>M src/northbridge/amd/agesa/family10/northbridge.c<br>M src/northbridge/amd/agesa/family10/reset_test.h<br>M src/northbridge/amd/agesa/family12/amdfam12_conf.c<br>M src/northbridge/amd/agesa/family12/northbridge.c<br>M src/northbridge/amd/agesa/family14/amdfam14_conf.c<br>M src/northbridge/amd/agesa/family15/northbridge.c<br>M src/northbridge/amd/agesa/family15rl/northbridge.c<br>M src/northbridge/amd/agesa/family15tn/northbridge.c<br>M src/northbridge/amd/agesa/family16kb/northbridge.c<br>9 files changed, 59 insertions(+), 59 deletions(-)<br><br></pre><pre style="font-family: monospace,monospace; white-space: pre-wrap;">git pull ssh://review.coreboot.org:29418/coreboot refs/changes/99/20399/1</pre><pre style="font-family: monospace,monospace; white-space: pre-wrap;">diff --git a/src/northbridge/amd/agesa/family10/northbridge.c b/src/northbridge/amd/agesa/family10/northbridge.c<br>index 6f7a053..15693b7 100644<br>--- a/src/northbridge/amd/agesa/family10/northbridge.c<br>+++ b/src/northbridge/amd/agesa/family10/northbridge.c<br>@@ -63,14 +63,14 @@<br> temp = pci_read_config32(dev, 0x44 + (nodeid << 3)); //[39:24] at [31:16]<br> d.mask = ((temp & 0xfff80000)>>(8+3)); // mask out DramMask [26:24] too<br> temp = pci_read_config32(dev, 0x144 + (nodeid <<3)) & 0xff; //[47:40] at [7:0]<br>- d.mask |= temp<<21;<br>+ d.mask |= temp << 21;<br> <br> temp = pci_read_config32(dev, 0x40 + (nodeid << 3)); //[39:24] at [31:16]<br> d.mask |= (temp & 1); // enable bit<br> <br> d.base = ((temp & 0xfff80000)>>(8+3)); // mask out DramBase [26:24) too<br> temp = pci_read_config32(dev, 0x140 + (nodeid <<3)) & 0xff; //[47:40] at [7:0]<br>- d.base |= temp<<21;<br>+ d.base |= temp << 21;<br> return d;<br> }<br> <br>@@ -82,12 +82,12 @@<br> if ((segbusn & 0xff)>(0xe0-1)) {// use next segn<br> u32 segn = (segbusn >> 8) & 0x0f;<br> segn++;<br>- segbusn = segn<<8;<br>+ segbusn = segn << 8;<br> }<br> if (segbusn>>8) {<br> u32 val;<br> val = pci_read_config32(dev, 0x160);<br>- val &= ~(0xf<<25);<br>+ val &= ~(0xf << 25);<br> val |= (segbusn & 0xf00)<<(25-8);<br> pci_write_config32(dev, 0x160, val);<br> }<br>@@ -135,9 +135,9 @@<br> index = (reg-0xc0)>>3;<br> <br> val = (nodeid & 0x3f); // 6 bits used<br>- sysconf.conf_io_addr[index] = val | ((io_max<<8) & 0xfffff000); //limit : with nodeid<br>+ sysconf.conf_io_addr[index] = val | ((io_max << 8) & 0xfffff000); //limit : with nodeid<br> val = 3 | ((linkn & 0x7)<<4); // 8 bits used<br>- sysconf.conf_io_addrx[index] = val | ((io_min<<8) & 0xfffff000); // base : with enable bit<br>+ sysconf.conf_io_addrx[index] = val | ((io_min << 8) & 0xfffff000); // base : with enable bit<br> <br> if (sysconf.io_addr_num<(index+1))<br> sysconf.io_addr_num = index+1;<br>@@ -166,11 +166,11 @@<br> u32 tempreg;<br> <br> /* io range allocation */<br>- tempreg = (nodeid&0xf) | ((nodeid & 0x30)<<(8-4)) | (linkn<<4) | ((io_max&0xf0)<<(12-4)); //limit<br>+ tempreg = (nodeid&0xf) | ((nodeid & 0x30)<<(8-4)) | (linkn << 4) | ((io_max&0xf0)<<(12-4)); //limit<br> for (i = 0; i < sysconf.nodes; i++)<br> pci_write_config32(__f1_dev[i], reg+4, tempreg);<br> <br>- tempreg = 3 /*| (3<<4)*/ | ((io_min&0xf0)<<(12-4)); //base :ISA and VGA ?<br>+ tempreg = 3 /*| (3 << 4)*/ | ((io_min&0xf0)<<(12-4)); //base :ISA and VGA ?<br> for (i = 0; i < sysconf.nodes; i++)<br> pci_write_config32(__f1_dev[i], reg, tempreg);<br> }<br>@@ -181,7 +181,7 @@<br> u32 tempreg;<br> <br> /* io range allocation */<br>- tempreg = (nodeid&0xf) | (linkn<<4) | (mmio_max&0xffffff00); //limit<br>+ tempreg = (nodeid&0xf) | (linkn << 4) | (mmio_max&0xffffff00); //limit<br> for (i = 0; i < nodes; i++)<br> pci_write_config32(__f1_dev[i], reg+4, tempreg);<br> tempreg = 3 | (nodeid & 0x30) | (mmio_min&0xffffff00);<br>@@ -267,7 +267,7 @@<br> {<br> u32 val;<br> <br>- val = 1 | (nodeid<<4) | (linkn<<12);<br>+ val = 1 | (nodeid << 4) | (linkn << 12);<br> /* it will routing (1)mmio 0xa0000:0xbffff (2) io 0x3b0:0x3bb,<br> 0x3c0:0x3df */<br> f1_write_config32(0xf4, val);<br>@@ -329,7 +329,7 @@<br> if (!reg) {<br> //because of Extend conf space, we will never run out of reg, but we need one index to differ them. so same node and same link can have multi range<br> u32 index = get_io_addr_index(nodeid, link);<br>- reg = 0x110+ (index<<24) + (4<<20); // index could be 0, 255<br>+ reg = 0x110+ (index << 24) + (4 << 20); // index could be 0, 255<br> }<br> <br> resource = new_resource(dev, IOINDEX(0x1000 + reg, link));<br>@@ -366,7 +366,7 @@<br> // but we need one index to differ them. so same node and<br> // same link can have multi range<br> u32 index = get_mmio_addr_index(nodeid, link);<br>- reg = 0x110+ (index<<24) + (6<<20); // index could be 0, 63<br>+ reg = 0x110+ (index << 24) + (6 << 20); // index could be 0, 63<br> <br> }<br> resource = new_resource(dev, IOINDEX(0x1000 + reg, link));<br>@@ -669,7 +669,7 @@<br> <br> hole = pci_read_config32(__f1_dev[i], 0xf0);<br> if (hole & 1) { // we find the hole<br>- mem_hole.hole_startk = (hole & (0xff<<24)) >> 10;<br>+ mem_hole.hole_startk = (hole & (0xff << 24)) >> 10;<br> mem_hole.node_id = i; // record the node No with hole<br> break; // only one hole<br> }<br>@@ -936,7 +936,7 @@<br> nb_cfg_54 = 0;<br> ApicIdCoreIdSize = (cpuid_ecx(0x80000008)>>12 & 0xf);<br> if (ApicIdCoreIdSize) {<br>- siblings = (1<<ApicIdCoreIdSize)-1;<br>+ siblings = (1 << ApicIdCoreIdSize)-1;<br> } else {<br> siblings = 3; //quad core<br> }<br>diff --git a/src/northbridge/amd/agesa/family10/reset_test.h b/src/northbridge/amd/agesa/family10/reset_test.h<br>index 48634ea..61de4d9 100644<br>--- a/src/northbridge/amd/agesa/family10/reset_test.h<br>+++ b/src/northbridge/amd/agesa/family10/reset_test.h<br>@@ -23,9 +23,9 @@<br> <br> #define NODE_ID 0x60<br> #define HT_INIT_CONTROL 0x6c<br>-#define HTIC_ColdR_Detect (1<<4)<br>-#define HTIC_BIOSR_Detect (1<<5)<br>-#define HTIC_INIT_Detect (1<<6)<br>+#define HTIC_ColdR_Detect (1 << 4)<br>+#define HTIC_BIOSR_Detect (1 << 5)<br>+#define HTIC_INIT_Detect (1 << 6)<br> <br> static inline u32 warm_reset_detect(u8 nodeid)<br> {<br>diff --git a/src/northbridge/amd/agesa/family12/amdfam12_conf.c b/src/northbridge/amd/agesa/family12/amdfam12_conf.c<br>index 46af104..4c5ef19 100644<br>--- a/src/northbridge/amd/agesa/family12/amdfam12_conf.c<br>+++ b/src/northbridge/amd/agesa/family12/amdfam12_conf.c<br>@@ -53,12 +53,12 @@<br> device_t dev;<br> <br> /* io range allocation */<br>- tempreg = (nodeid&0xf) | ((nodeid & 0x30)<<(8-4)) | (linkn<<4) | ((io_max&0xf0)<<(12-4)); //limit<br>+ tempreg = (nodeid&0xf) | ((nodeid & 0x30)<<(8-4)) | (linkn << 4) | ((io_max&0xf0)<<(12-4)); //limit<br> for (i = 0; i < nodes; i++) {<br> dev = NODE_PCI(i, 1);<br> pci_write_config32(dev, 0xC4 + ht_c_index * 8, tempreg);<br> }<br>- tempreg = 3 /*| (3<<4)*/ | ((io_min&0xf0)<<(12-4)); //base :ISA and VGA ?<br>+ tempreg = 3 /*| (3 << 4)*/ | ((io_min&0xf0)<<(12-4)); //base :ISA and VGA ?<br> for (i = 0; i < nodes; i++) {<br> dev = NODE_PCI(i, 1);<br> pci_write_config32(dev, 0xC0 + ht_c_index * 8, tempreg);<br>@@ -98,10 +98,10 @@<br> <br> u32 tempreg;<br> /* io range allocation */<br>- tempreg = (nodeid&0xf) | ((nodeid & 0x30)<<(8-4)) | (linkn<<4) | ((io_max&0xf0)<<(12-4)); //limit<br>+ tempreg = (nodeid&0xf) | ((nodeid & 0x30)<<(8-4)) | (linkn << 4) | ((io_max&0xf0)<<(12-4)); //limit<br> pci_write_config32(__f1_dev[0], reg+4, tempreg);<br> <br>- tempreg = 3 /*| (3<<4)*/ | ((io_min&0xf0)<<(12-4)); //base :ISA and VGA ?<br>+ tempreg = 3 /*| (3 << 4)*/ | ((io_min&0xf0)<<(12-4)); //base :ISA and VGA ?<br> pci_write_config32(__f1_dev[0], reg, tempreg);<br> }<br> <br>@@ -111,7 +111,7 @@<br> <br> u32 tempreg;<br> /* io range allocation */<br>- tempreg = (nodeid&0xf) | (linkn<<4) | (mmio_max&0xffffff00); //limit<br>+ tempreg = (nodeid&0xf) | (linkn << 4) | (mmio_max&0xffffff00); //limit<br> pci_write_config32(__f1_dev[0], reg+4, tempreg);<br> tempreg = 3 | (nodeid & 0x30) | (mmio_min&0xffffff00);<br> pci_write_config32(__f1_dev[0], reg, tempreg);<br>diff --git a/src/northbridge/amd/agesa/family12/northbridge.c b/src/northbridge/amd/agesa/family12/northbridge.c<br>index c931bf0..206ae47 100644<br>--- a/src/northbridge/amd/agesa/family12/northbridge.c<br>+++ b/src/northbridge/amd/agesa/family12/northbridge.c<br>@@ -108,7 +108,7 @@<br> u32 val;<br> <br> printk(BIOS_DEBUG, "\nFam12h - northbridge.c - %s - Start.\n",__func__);<br>- val = 1 | (nodeid<<4) | (linkn<<12);<br>+ val = 1 | (nodeid << 4) | (linkn << 12);<br> /* it will routing (1)mmio 0xa0000:0xbffff (2) io 0x3b0:0x3bb,<br> 0x3c0:0x3df */<br> f1_write_config32(0xf4, val);<br>@@ -162,7 +162,7 @@<br> if (!reg) {<br> //because of Extend conf space, we will never run out of reg, but we need one index to differ them. so same node and same link can have multi range<br> u32 index = get_io_addr_index(nodeid, link);<br>- reg = 0x110+ (index<<24) + (4<<20); // index could be 0, 255<br>+ reg = 0x110+ (index << 24) + (4 << 20); // index could be 0, 255<br> }<br> <br> resource = new_resource(dev, IOINDEX(0x1000 + reg, link));<br>@@ -198,7 +198,7 @@<br> // but we need one index to differ them. so same node and<br> // same link can have multi range<br> u32 index = get_mmio_addr_index(nodeid, link);<br>- reg = 0x110+ (index<<24) + (6<<20); // index could be 0, 63<br>+ reg = 0x110+ (index << 24) + (6 << 20); // index could be 0, 63<br> }<br> <br> resource = new_resource(dev, IOINDEX(0x1000 + reg, link));<br>@@ -280,7 +280,7 @@<br> if (d.mask & 1) {<br> hole = pci_read_config32(__f1_dev[0], 0xf0);<br> if (hole & 1) { // we find the hole<br>- mem_hole.hole_startk = (hole & (0xff<<24)) >> 10;<br>+ mem_hole.hole_startk = (hole & (0xff << 24)) >> 10;<br> mem_hole.node_id = 0; // record the node No with hole<br> }<br> }<br>diff --git a/src/northbridge/amd/agesa/family14/amdfam14_conf.c b/src/northbridge/amd/agesa/family14/amdfam14_conf.c<br>index 0e588ad..5de7a05 100644<br>--- a/src/northbridge/amd/agesa/family14/amdfam14_conf.c<br>+++ b/src/northbridge/amd/agesa/family14/amdfam14_conf.c<br>@@ -53,12 +53,12 @@<br> device_t dev;<br> <br> /* io range allocation */<br>- tempreg = (nodeid&0xf) | ((nodeid & 0x30)<<(8-4)) | (linkn<<4) | ((io_max&0xf0)<<(12-4)); //limit<br>+ tempreg = (nodeid&0xf) | ((nodeid & 0x30)<<(8-4)) | (linkn << 4) | ((io_max&0xf0)<<(12-4)); //limit<br> for (i = 0; i < nodes; i++) {<br> dev = NODE_PCI(i, 1);<br> pci_write_config32(dev, 0xC4 + ht_c_index * 8, tempreg);<br> }<br>- tempreg = 3 /*| (3<<4)*/ | ((io_min&0xf0)<<(12-4)); //base :ISA and VGA ?<br>+ tempreg = 3 /*| (3 << 4)*/ | ((io_min&0xf0)<<(12-4)); //base :ISA and VGA ?<br> for (i = 0; i < nodes; i++) {<br> dev = NODE_PCI(i, 1);<br> pci_write_config32(dev, 0xC0 + ht_c_index * 8, tempreg);<br>@@ -98,10 +98,10 @@<br> <br> u32 tempreg;<br> /* io range allocation */<br>- tempreg = (nodeid&0xf) | ((nodeid & 0x30)<<(8-4)) | (linkn<<4) | ((io_max&0xf0)<<(12-4)); //limit<br>+ tempreg = (nodeid&0xf) | ((nodeid & 0x30)<<(8-4)) | (linkn << 4) | ((io_max&0xf0)<<(12-4)); //limit<br> pci_write_config32(__f1_dev[0], reg+4, tempreg);<br> <br>- tempreg = 3 /*| (3<<4)*/ | ((io_min&0xf0)<<(12-4)); //base :ISA and VGA ?<br>+ tempreg = 3 /*| (3 << 4)*/ | ((io_min&0xf0)<<(12-4)); //base :ISA and VGA ?<br> pci_write_config32(__f1_dev[0], reg, tempreg);<br> }<br> <br>@@ -111,7 +111,7 @@<br> <br> u32 tempreg;<br> /* io range allocation */<br>- tempreg = (nodeid&0xf) | (linkn<<4) | (mmio_max&0xffffff00); //limit<br>+ tempreg = (nodeid&0xf) | (linkn << 4) | (mmio_max&0xffffff00); //limit<br> pci_write_config32(__f1_dev[0], reg+4, tempreg);<br> tempreg = 3 | (nodeid & 0x30) | (mmio_min&0xffffff00);<br> pci_write_config32(__f1_dev[0], reg, tempreg);<br>diff --git a/src/northbridge/amd/agesa/family15/northbridge.c b/src/northbridge/amd/agesa/family15/northbridge.c<br>index 5cb0f91..15af024 100644<br>--- a/src/northbridge/amd/agesa/family15/northbridge.c<br>+++ b/src/northbridge/amd/agesa/family15/northbridge.c<br>@@ -67,12 +67,12 @@<br> temp = pci_read_config32(dev, 0x44 + (nodeid << 3)); //[39:24] at [31:16]<br> d.mask = ((temp & 0xfff80000)>>(8+3)); // mask out DramMask [26:24] too<br> temp = pci_read_config32(dev, 0x144 + (nodeid <<3)) & 0xff; //[47:40] at [7:0]<br>- d.mask |= temp<<21;<br>+ d.mask |= temp << 21;<br> temp = pci_read_config32(dev, 0x40 + (nodeid << 3)); //[39:24] at [31:16]<br> d.mask |= (temp & 1); // enable bit<br> d.base = ((temp & 0xfff80000)>>(8+3)); // mask out DramBase [26:24) too<br> temp = pci_read_config32(dev, 0x140 + (nodeid <<3)) & 0xff; //[47:40] at [7:0]<br>- d.base |= temp<<21;<br>+ d.base |= temp << 21;<br> return d;<br> }<br> <br>@@ -82,10 +82,10 @@<br> u32 i;<br> u32 tempreg;<br> /* io range allocation */<br>- tempreg = (nodeid&0xf) | ((nodeid & 0x30)<<(8-4)) | (linkn<<4) | ((io_max&0xf0)<<(12-4)); //limit<br>+ tempreg = (nodeid&0xf) | ((nodeid & 0x30)<<(8-4)) | (linkn << 4) | ((io_max&0xf0)<<(12-4)); //limit<br> for (i = 0; i < node_nums; i++)<br> pci_write_config32(__f1_dev[i], reg+4, tempreg);<br>- tempreg = 3 /*| (3<<4)*/ | ((io_min&0xf0)<<(12-4)); //base :ISA and VGA ?<br>+ tempreg = 3 /*| (3 << 4)*/ | ((io_min&0xf0)<<(12-4)); //base :ISA and VGA ?<br> for (i = 0; i < node_nums; i++)<br> pci_write_config32(__f1_dev[i], reg, tempreg);<br> }<br>@@ -95,7 +95,7 @@<br> u32 i;<br> u32 tempreg;<br> /* io range allocation */<br>- tempreg = (nodeid&0xf) | (linkn<<4) | (mmio_max&0xffffff00); //limit<br>+ tempreg = (nodeid&0xf) | (linkn << 4) | (mmio_max&0xffffff00); //limit<br> for (i = 0; i < nodes; i++)<br> pci_write_config32(__f1_dev[i], reg+4, tempreg);<br> tempreg = 3 | (nodeid & 0x30) | (mmio_min&0xffffff00);<br>@@ -174,7 +174,7 @@<br> {<br> u32 val;<br> <br>- val = 1 | (nodeid<<4) | (linkn<<12);<br>+ val = 1 | (nodeid << 4) | (linkn << 12);<br> /* it will routing<br> * (1)mmio 0xa0000:0xbffff<br> * (2)io 0x3b0:0x3bb, 0x3c0:0x3df<br>@@ -668,7 +668,7 @@<br> if (!(d.mask & 1)) continue; // no memory on this node<br> hole = pci_read_config32(__f1_dev[i], 0xf0);<br> if (hole & 1) { // we find the hole<br>- mem_hole.hole_startk = (hole & (0xff<<24)) >> 10;<br>+ mem_hole.hole_startk = (hole & (0xff << 24)) >> 10;<br> mem_hole.node_id = i; // record the node No with hole<br> break; // only one hole<br> }<br>diff --git a/src/northbridge/amd/agesa/family15rl/northbridge.c b/src/northbridge/amd/agesa/family15rl/northbridge.c<br>index aa24a6a..8cb801b 100644<br>--- a/src/northbridge/amd/agesa/family15rl/northbridge.c<br>+++ b/src/northbridge/amd/agesa/family15rl/northbridge.c<br>@@ -66,12 +66,12 @@<br> temp = pci_read_config32(dev, 0x44 + (nodeid << 3)); //[39:24] at [31:16]<br> d.mask = ((temp & 0xfff80000)>>(8+3)); // mask out DramMask [26:24] too<br> temp = pci_read_config32(dev, 0x144 + (nodeid <<3)) & 0xff; //[47:40] at [7:0]<br>- d.mask |= temp<<21;<br>+ d.mask |= temp << 21;<br> temp = pci_read_config32(dev, 0x40 + (nodeid << 3)); //[39:24] at [31:16]<br> d.mask |= (temp & 1); // enable bit<br> d.base = ((temp & 0xfff80000)>>(8+3)); // mask out DramBase [26:24) too<br> temp = pci_read_config32(dev, 0x140 + (nodeid <<3)) & 0xff; //[47:40] at [7:0]<br>- d.base |= temp<<21;<br>+ d.base |= temp << 21;<br> return d;<br> }<br> <br>@@ -81,10 +81,10 @@<br> u32 i;<br> u32 tempreg;<br> /* io range allocation */<br>- tempreg = (nodeid&0xf) | ((nodeid & 0x30)<<(8-4)) | (linkn<<4) | ((io_max&0xf0)<<(12-4)); //limit<br>+ tempreg = (nodeid&0xf) | ((nodeid & 0x30)<<(8-4)) | (linkn << 4) | ((io_max&0xf0)<<(12-4)); //limit<br> for (i = 0; i < node_nums; i++)<br> pci_write_config32(__f1_dev[i], reg+4, tempreg);<br>- tempreg = 3 /*| (3<<4)*/ | ((io_min&0xf0)<<(12-4)); //base :ISA and VGA ?<br>+ tempreg = 3 /*| (3 << 4)*/ | ((io_min&0xf0)<<(12-4)); //base :ISA and VGA ?<br> for (i = 0; i < node_nums; i++)<br> pci_write_config32(__f1_dev[i], reg, tempreg);<br> }<br>@@ -94,7 +94,7 @@<br> u32 i;<br> u32 tempreg;<br> /* io range allocation */<br>- tempreg = (nodeid&0xf) | (linkn<<4) | (mmio_max&0xffffff00); //limit<br>+ tempreg = (nodeid&0xf) | (linkn << 4) | (mmio_max&0xffffff00); //limit<br> for (i = 0; i < nodes; i++)<br> pci_write_config32(__f1_dev[i], reg+4, tempreg);<br> tempreg = 3 | (nodeid & 0x30) | (mmio_min&0xffffff00);<br>@@ -173,7 +173,7 @@<br> {<br> u32 val;<br> <br>- val = 1 | (nodeid<<4) | (linkn<<12);<br>+ val = 1 | (nodeid << 4) | (linkn << 12);<br> /* it will routing<br> * (1)mmio 0xa0000:0xbffff<br> * (2)io 0x3b0:0x3bb, 0x3c0:0x3df<br>@@ -664,7 +664,7 @@<br> if (!(d.mask & 1)) continue; // no memory on this node<br> hole = pci_read_config32(__f1_dev[i], 0xf0);<br> if (hole & 1) { // we find the hole<br>- mem_hole.hole_startk = (hole & (0xff<<24)) >> 10;<br>+ mem_hole.hole_startk = (hole & (0xff << 24)) >> 10;<br> mem_hole.node_id = i; // record the node No with hole<br> break; // only one hole<br> }<br>diff --git a/src/northbridge/amd/agesa/family15tn/northbridge.c b/src/northbridge/amd/agesa/family15tn/northbridge.c<br>index 95787fc..66da338 100644<br>--- a/src/northbridge/amd/agesa/family15tn/northbridge.c<br>+++ b/src/northbridge/amd/agesa/family15tn/northbridge.c<br>@@ -65,12 +65,12 @@<br> temp = pci_read_config32(dev, 0x44 + (nodeid << 3)); //[39:24] at [31:16]<br> d.mask = ((temp & 0xfff80000)>>(8+3)); // mask out DramMask [26:24] too<br> temp = pci_read_config32(dev, 0x144 + (nodeid <<3)) & 0xff; //[47:40] at [7:0]<br>- d.mask |= temp<<21;<br>+ d.mask |= temp << 21;<br> temp = pci_read_config32(dev, 0x40 + (nodeid << 3)); //[39:24] at [31:16]<br> d.mask |= (temp & 1); // enable bit<br> d.base = ((temp & 0xfff80000)>>(8+3)); // mask out DramBase [26:24) too<br> temp = pci_read_config32(dev, 0x140 + (nodeid <<3)) & 0xff; //[47:40] at [7:0]<br>- d.base |= temp<<21;<br>+ d.base |= temp << 21;<br> return d;<br> }<br> <br>@@ -80,10 +80,10 @@<br> u32 i;<br> u32 tempreg;<br> /* io range allocation */<br>- tempreg = (nodeid&0xf) | ((nodeid & 0x30)<<(8-4)) | (linkn<<4) | ((io_max&0xf0)<<(12-4)); //limit<br>+ tempreg = (nodeid&0xf) | ((nodeid & 0x30)<<(8-4)) | (linkn << 4) | ((io_max&0xf0)<<(12-4)); //limit<br> for (i = 0; i < node_nums; i++)<br> pci_write_config32(__f1_dev[i], reg+4, tempreg);<br>- tempreg = 3 /*| (3<<4)*/ | ((io_min&0xf0)<<(12-4)); //base :ISA and VGA ?<br>+ tempreg = 3 /*| (3 << 4)*/ | ((io_min&0xf0)<<(12-4)); //base :ISA and VGA ?<br> for (i = 0; i < node_nums; i++)<br> pci_write_config32(__f1_dev[i], reg, tempreg);<br> }<br>@@ -93,7 +93,7 @@<br> u32 i;<br> u32 tempreg;<br> /* io range allocation */<br>- tempreg = (nodeid&0xf) | (linkn<<4) | (mmio_max&0xffffff00); //limit<br>+ tempreg = (nodeid&0xf) | (linkn << 4) | (mmio_max&0xffffff00); //limit<br> for (i = 0; i < nodes; i++)<br> pci_write_config32(__f1_dev[i], reg+4, tempreg);<br> tempreg = 3 | (nodeid & 0x30) | (mmio_min&0xffffff00);<br>@@ -172,7 +172,7 @@<br> {<br> u32 val;<br> <br>- val = 1 | (nodeid<<4) | (linkn<<12);<br>+ val = 1 | (nodeid << 4) | (linkn << 12);<br> /* it will routing<br> * (1)mmio 0xa0000:0xbffff<br> * (2)io 0x3b0:0x3bb, 0x3c0:0x3df<br>@@ -663,7 +663,7 @@<br> if (!(d.mask & 1)) continue; // no memory on this node<br> hole = pci_read_config32(__f1_dev[i], 0xf0);<br> if (hole & 1) { // we find the hole<br>- mem_hole.hole_startk = (hole & (0xff<<24)) >> 10;<br>+ mem_hole.hole_startk = (hole & (0xff << 24)) >> 10;<br> mem_hole.node_id = i; // record the node No with hole<br> break; // only one hole<br> }<br>diff --git a/src/northbridge/amd/agesa/family16kb/northbridge.c b/src/northbridge/amd/agesa/family16kb/northbridge.c<br>index f91448a..4545601 100644<br>--- a/src/northbridge/amd/agesa/family16kb/northbridge.c<br>+++ b/src/northbridge/amd/agesa/family16kb/northbridge.c<br>@@ -65,12 +65,12 @@<br> temp = pci_read_config32(dev, 0x44 + (nodeid << 3)); //[39:24] at [31:16]<br> d.mask = ((temp & 0xfff80000)>>(8+3)); // mask out DramMask [26:24] too<br> temp = pci_read_config32(dev, 0x144 + (nodeid <<3)) & 0xff; //[47:40] at [7:0]<br>- d.mask |= temp<<21;<br>+ d.mask |= temp << 21;<br> temp = pci_read_config32(dev, 0x40 + (nodeid << 3)); //[39:24] at [31:16]<br> d.mask |= (temp & 1); // enable bit<br> d.base = ((temp & 0xfff80000)>>(8+3)); // mask out DramBase [26:24) too<br> temp = pci_read_config32(dev, 0x140 + (nodeid <<3)) & 0xff; //[47:40] at [7:0]<br>- d.base |= temp<<21;<br>+ d.base |= temp << 21;<br> return d;<br> }<br> <br>@@ -80,10 +80,10 @@<br> u32 i;<br> u32 tempreg;<br> /* io range allocation */<br>- tempreg = (nodeid&0xf) | ((nodeid & 0x30)<<(8-4)) | (linkn<<4) | ((io_max&0xf0)<<(12-4)); //limit<br>+ tempreg = (nodeid&0xf) | ((nodeid & 0x30)<<(8-4)) | (linkn << 4) | ((io_max&0xf0)<<(12-4)); //limit<br> for (i = 0; i < node_nums; i++)<br> pci_write_config32(__f1_dev[i], reg+4, tempreg);<br>- tempreg = 3 /*| (3<<4)*/ | ((io_min&0xf0)<<(12-4)); //base :ISA and VGA ?<br>+ tempreg = 3 /*| (3 << 4)*/ | ((io_min&0xf0)<<(12-4)); //base :ISA and VGA ?<br> for (i = 0; i < node_nums; i++)<br> pci_write_config32(__f1_dev[i], reg, tempreg);<br> }<br>@@ -93,7 +93,7 @@<br> u32 i;<br> u32 tempreg;<br> /* io range allocation */<br>- tempreg = (nodeid&0xf) | (linkn<<4) | (mmio_max&0xffffff00); //limit<br>+ tempreg = (nodeid&0xf) | (linkn << 4) | (mmio_max&0xffffff00); //limit<br> for (i = 0; i < nodes; i++)<br> pci_write_config32(__f1_dev[i], reg+4, tempreg);<br> tempreg = 3 | (nodeid & 0x30) | (mmio_min&0xffffff00);<br>@@ -172,7 +172,7 @@<br> {<br> u32 val;<br> <br>- val = 1 | (nodeid<<4) | (linkn<<12);<br>+ val = 1 | (nodeid << 4) | (linkn << 12);<br> /* it will routing<br> * (1)mmio 0xa0000:0xbffff<br> * (2)io 0x3b0:0x3bb, 0x3c0:0x3df<br>@@ -678,7 +678,7 @@<br> if (!(d.mask & 1)) continue; // no memory on this node<br> hole = pci_read_config32(__f1_dev[i], 0xf0);<br> if (hole & 2) { // we find the hole<br>- mem_hole.hole_startk = (hole & (0xff<<24)) >> 10;<br>+ mem_hole.hole_startk = (hole & (0xff << 24)) >> 10;<br> mem_hole.node_id = i; // record the node No with hole<br> break; // only one hole<br> }<br></pre><p>To view, visit <a href="https://review.coreboot.org/20399">change 20399</a>. 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<div style="display:none"> Gerrit-Project: coreboot </div>
<div style="display:none"> Gerrit-Branch: master </div>
<div style="display:none"> Gerrit-MessageType: newchange </div>
<div style="display:none"> Gerrit-Change-Id: I56cb941d07ac48f8209a892ec18af8f5090765f7 </div>
<div style="display:none"> Gerrit-Change-Number: 20399 </div>
<div style="display:none"> Gerrit-PatchSet: 1 </div>
<div style="display:none"> Gerrit-Owner: HAOUAS Elyes <ehaouas@noos.fr> </div>