<p>HAOUAS Elyes has uploaded this change for <strong>review</strong>.</p><p><a href="https://review.coreboot.org/20397">View Change</a></p><pre style="font-family: monospace,monospace; white-space: pre-wrap;">cpu/*: Add whitespace around '<<'<br><br>Change-Id: Id46c0b57bd7c9b954b29537c70254df947690e0b<br>Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr><br>---<br>M src/cpu/amd/agesa/cache_as_ram.inc<br>M src/cpu/amd/agesa/cache_as_ram_legacy.inc<br>M src/cpu/amd/dualcore/amd_sibling.c<br>M src/cpu/amd/dualcore/dualcore.c<br>M src/cpu/amd/dualcore/dualcore_id.c<br>M src/cpu/amd/geode_gx2/cpubug.c<br>M src/cpu/amd/mtrr/amd_mtrr.c<br>M src/cpu/amd/pi/cache_as_ram.inc<br>M src/cpu/amd/quadcore/amd_sibling.c<br>M src/cpu/intel/car/cache_as_ram_ht.inc<br>M src/cpu/intel/haswell/smmrelocate.c<br>M src/cpu/intel/smm/gen1/smmrelocate.c<br>M src/cpu/via/c7/c7_init.c<br>M src/cpu/via/nano/nano_init.c<br>14 files changed, 28 insertions(+), 28 deletions(-)<br><br></pre><pre style="font-family: monospace,monospace; white-space: pre-wrap;">git pull ssh://review.coreboot.org:29418/coreboot refs/changes/97/20397/1</pre><pre style="font-family: monospace,monospace; white-space: pre-wrap;">diff --git a/src/cpu/amd/agesa/cache_as_ram.inc b/src/cpu/amd/agesa/cache_as_ram.inc<br>index 857873a..8038177 100644<br>--- a/src/cpu/amd/agesa/cache_as_ram.inc<br>+++ b/src/cpu/amd/agesa/cache_as_ram.inc<br>@@ -40,7 +40,7 @@<br> /* Turn on OSFXSR [BIT9] and OSXMMEXCPT [BIT10] onto CR4 register */<br> <br> movl %cr4, %eax<br>- orl $(3<<9), %eax<br>+ orl $(3 << 9), %eax<br> movl %eax, %cr4<br> <br> post_code(0xa1)<br>diff --git a/src/cpu/amd/agesa/cache_as_ram_legacy.inc b/src/cpu/amd/agesa/cache_as_ram_legacy.inc<br>index c0a69ec..5548007 100644<br>--- a/src/cpu/amd/agesa/cache_as_ram_legacy.inc<br>+++ b/src/cpu/amd/agesa/cache_as_ram_legacy.inc<br>@@ -43,7 +43,7 @@<br> /* Turn on OSFXSR [BIT9] and OSXMMEXCPT [BIT10] onto CR4 register */<br> <br> movl %cr4, %eax<br>- orl $(3<<9), %eax<br>+ orl $(3 << 9), %eax<br> movl %eax, %cr4<br> <br> /* Get the cpu_init_detected */<br>diff --git a/src/cpu/amd/dualcore/amd_sibling.c b/src/cpu/amd/dualcore/amd_sibling.c<br>index 1c003c8..693ceb8 100644<br>--- a/src/cpu/amd/dualcore/amd_sibling.c<br>+++ b/src/cpu/amd/dualcore/amd_sibling.c<br>@@ -59,7 +59,7 @@<br> uint32_t val;<br> dev = dev_find_slot(0, PCI_DEVFN(0x18+nodeid, 0));<br> val = pci_read_config32(dev, 0x68);<br>- val |= (1<<17)|(1<<18);<br>+ val |= (1 << 17)|(1 << 18);<br> pci_write_config32(dev, 0x68, val);<br> }<br> }<br>@@ -84,7 +84,7 @@<br> <br> if (bsp_apic_id > 0) { // IOAPIC could start from 0<br> return 0;<br>- } else if (pci_read_config32(dev, 0x68) & ( (1<<17) | (1<<18)) ) { // enabled ext id but bsp = 0<br>+ } else if (pci_read_config32(dev, 0x68) & ( (1 << 17) | (1 << 18)) ) { // enabled ext id but bsp = 0<br> return 1;<br> }<br> <br>diff --git a/src/cpu/amd/dualcore/dualcore.c b/src/cpu/amd/dualcore/dualcore.c<br>index 83302ca..1f25668 100644<br>--- a/src/cpu/amd/dualcore/dualcore.c<br>+++ b/src/cpu/amd/dualcore/dualcore.c<br>@@ -48,11 +48,11 @@<br> uint32_t dword;<br> // set PCI_DEV(0, 0x18+nodeid, 3), 0x44 bit 27 to redirect all MC4 accesses and error logging to core0<br> dword = pci_read_config32(PCI_DEV(0, 0x18+nodeid, 3), 0x44);<br>- dword |= 1<<27; // NbMcaToMstCpuEn bit<br>+ dword |= 1 << 27; // NbMcaToMstCpuEn bit<br> pci_write_config32(PCI_DEV(0, 0x18+nodeid, 3), 0x44, dword);<br> // set PCI_DEV(0, 0x18+nodeid, 0), 0x68 bit 5 to start core1<br> dword = pci_read_config32(PCI_DEV(0, 0x18+nodeid, 0), 0x68);<br>- dword |= 1<<5;<br>+ dword |= 1 << 5;<br> pci_write_config32(PCI_DEV(0, 0x18+nodeid, 0), 0x68, dword);<br> }<br> <br>diff --git a/src/cpu/amd/dualcore/dualcore_id.c b/src/cpu/amd/dualcore/dualcore_id.c<br>index 80ce1c7..e7af552 100644<br>--- a/src/cpu/amd/dualcore/dualcore_id.c<br>+++ b/src/cpu/amd/dualcore/dualcore_id.c<br>@@ -43,14 +43,14 @@<br> // when NB_CFG[54] is set, nodeid = ebx[27:25], coreid = ebx[24]<br> id.coreid = (cpuid_ebx(1) >> 24) & 0xf;<br> id.nodeid = (id.coreid>>CORE_ID_BIT);<br>- id.coreid &= ((1<<CORE_ID_BIT)-1);<br>+ id.coreid &= ((1 << CORE_ID_BIT)-1);<br> }<br> else<br> {<br> // when NB_CFG[54] is clear, nodeid = ebx[26:24], coreid = ebx[27]<br> id.nodeid = (cpuid_ebx(1) >> 24) & 0xf;<br> id.coreid = (id.nodeid>>NODE_ID_BIT);<br>- id.nodeid &= ((1<<NODE_ID_BIT)-1);<br>+ id.nodeid &= ((1 << NODE_ID_BIT)-1);<br> }<br> return id;<br> }<br>diff --git a/src/cpu/amd/geode_gx2/cpubug.c b/src/cpu/amd/geode_gx2/cpubug.c<br>index af7ddf3..cf2b79d 100644<br>--- a/src/cpu/amd/geode_gx2/cpubug.c<br>+++ b/src/cpu/amd/geode_gx2/cpubug.c<br>@@ -54,8 +54,8 @@<br> * for PCI writes to complete.<br> */<br> msr = rdmsr(CPU_DM_CONFIG0);<br>- msr.hi &= ~(7<<DM_CONFIG0_UPPER_WSREQ_SHIFT);<br>- msr.hi |= (2<<DM_CONFIG0_UPPER_WSREQ_SHIFT);<br>+ msr.hi &= ~(7 << DM_CONFIG0_UPPER_WSREQ_SHIFT);<br>+ msr.hi |= (2 << DM_CONFIG0_UPPER_WSREQ_SHIFT);<br> msr.lo |= DM_CONFIG0_LOWER_MISSER_SET;<br> wrmsr(CPU_DM_CONFIG0, msr);<br> <br>@@ -126,7 +126,7 @@<br> msr = rdmsr(MSR_GLCP+0x17);<br> if ((msr.lo & 0xff) <= CPU_REV_2_0) {<br> msr = rdmsr(GLCP_SYS_RSTPLL);<br>- if (msr.lo & (1<<RSTPPL_LOWER_SDRMODE_SHIFT))<br>+ if (msr.lo & (1 << RSTPPL_LOWER_SDRMODE_SHIFT))<br> return;<br> }<br> <br>diff --git a/src/cpu/amd/mtrr/amd_mtrr.c b/src/cpu/amd/mtrr/amd_mtrr.c<br>index 106cb79..8cb6658 100644<br>--- a/src/cpu/amd/mtrr/amd_mtrr.c<br>+++ b/src/cpu/amd/mtrr/amd_mtrr.c<br>@@ -54,8 +54,8 @@<br> "%s, TOP MEM2: msr.lo = 0x%08x, msr.hi = 0x%08x\n",<br> __func__, msr2.lo, msr2.hi);<br> <br>- amd_topmem = (uint64_t) msr.hi<<32 | msr.lo;<br>- amd_topmem2 = (uint64_t) msr2.hi<<32 | msr2.lo;<br>+ amd_topmem = (uint64_t) msr.hi << 32 | msr.lo;<br>+ amd_topmem2 = (uint64_t) msr2.hi << 32 | msr2.lo;<br> }<br> <br> static void setup_ap_ramtop(void)<br>@@ -128,7 +128,7 @@<br> <br> /* if DRAM above 4GB: set SYSCFG_MSR_TOM2En and SYSCFG_MSR_TOM2WB */<br> sys_cfg.lo &= ~(SYSCFG_MSR_TOM2En | SYSCFG_MSR_TOM2WB);<br>- if (bsp_topmem2() > (uint64_t)1<<32) {<br>+ if (bsp_topmem2() > (uint64_t)1 << 32) {<br> sys_cfg.lo |= SYSCFG_MSR_TOM2En;<br> if (has_tom2wb)<br> sys_cfg.lo |= SYSCFG_MSR_TOM2WB;<br>diff --git a/src/cpu/amd/pi/cache_as_ram.inc b/src/cpu/amd/pi/cache_as_ram.inc<br>index c0a69ec..5548007 100644<br>--- a/src/cpu/amd/pi/cache_as_ram.inc<br>+++ b/src/cpu/amd/pi/cache_as_ram.inc<br>@@ -43,7 +43,7 @@<br> /* Turn on OSFXSR [BIT9] and OSXMMEXCPT [BIT10] onto CR4 register */<br> <br> movl %cr4, %eax<br>- orl $(3<<9), %eax<br>+ orl $(3 << 9), %eax<br> movl %eax, %cr4<br> <br> /* Get the cpu_init_detected */<br>diff --git a/src/cpu/amd/quadcore/amd_sibling.c b/src/cpu/amd/quadcore/amd_sibling.c<br>index c4eb50c..a04ec55 100644<br>--- a/src/cpu/amd/quadcore/amd_sibling.c<br>+++ b/src/cpu/amd/quadcore/amd_sibling.c<br>@@ -64,7 +64,7 @@<br> u32 val;<br> dev = get_node_pci(nodeid, 0);<br> val = pci_read_config32(dev, 0x68);<br>- val |= (1<<17)|(1<<18);<br>+ val |= (1 << 17)|(1 << 18);<br> pci_write_config32(dev, 0x68, val);<br> }<br> }<br>diff --git a/src/cpu/intel/car/cache_as_ram_ht.inc b/src/cpu/intel/car/cache_as_ram_ht.inc<br>index db779fa..e716caf 100644<br>--- a/src/cpu/intel/car/cache_as_ram_ht.inc<br>+++ b/src/cpu/intel/car/cache_as_ram_ht.inc<br>@@ -82,7 +82,7 @@<br> addrsize_no_MSR:<br> movl $1, %eax<br> cpuid<br>- andl $(1<<6 | 1<<17), %edx /* PAE or PSE36 */<br>+ andl $(1 << 6 | 1 << 17), %edx /* PAE or PSE36 */<br> jz addrsize_set_high<br> movl $0x0f, %edx<br> <br>@@ -208,7 +208,7 @@<br> <br> /* MTRR registers are shared between HT siblings. */<br> movl $(MTRR_PHYS_BASE(0)), %ecx<br>- movl $(1<<12), %eax<br>+ movl $(1 << 12), %eax<br> xorl %edx, %edx<br> wrmsr<br> <br>diff --git a/src/cpu/intel/haswell/smmrelocate.c b/src/cpu/intel/haswell/smmrelocate.c<br>index 5c88dfa..8d9a4dc 100644<br>--- a/src/cpu/intel/haswell/smmrelocate.c<br>+++ b/src/cpu/intel/haswell/smmrelocate.c<br>@@ -42,8 +42,8 @@<br> #define SMBASE_MSR 0xc20<br> #define IEDBASE_MSR 0xc22<br> <br>-#define SMRR_SUPPORTED (1<<11)<br>-#define EMRR_SUPPORTED (1<<12)<br>+#define SMRR_SUPPORTED (1 << 11)<br>+#define EMRR_SUPPORTED (1 << 12)<br> <br> struct smm_relocation_params {<br> u32 smram_base;<br>diff --git a/src/cpu/intel/smm/gen1/smmrelocate.c b/src/cpu/intel/smm/gen1/smmrelocate.c<br>index 1da7a4b..387fb8b 100644<br>--- a/src/cpu/intel/smm/gen1/smmrelocate.c<br>+++ b/src/cpu/intel/smm/gen1/smmrelocate.c<br>@@ -28,7 +28,7 @@<br> #include <console/console.h><br> #include "smi.h"<br> <br>-#define SMRR_SUPPORTED (1<<11)<br>+#define SMRR_SUPPORTED (1 << 11)<br> <br> #define D_OPEN (1 << 6)<br> #define D_CLS (1 << 5)<br>diff --git a/src/cpu/via/c7/c7_init.c b/src/cpu/via/c7/c7_init.c<br>index 8ddc931..480f61a 100644<br>--- a/src/cpu/via/c7/c7_init.c<br>+++ b/src/cpu/via/c7/c7_init.c<br>@@ -190,7 +190,7 @@<br> <br> /* Enable APIC */<br> msr = rdmsr(0x1107);<br>- msr.lo |= 1<<24;<br>+ msr.lo |= 1 << 24;<br> wrmsr(0x1107, msr);<br> <br> /* Turn on cache */<br>diff --git a/src/cpu/via/nano/nano_init.c b/src/cpu/via/nano/nano_init.c<br>index 3a6c1a0..7d6338e 100644<br>--- a/src/cpu/via/nano/nano_init.c<br>+++ b/src/cpu/via/nano/nano_init.c<br>@@ -104,12 +104,12 @@<br> * This MSR is not documented by VIA docs, other than setting these<br> * bits */<br> msr = rdmsr(NANO_MYSTERIOUS_MSR);<br>- msr.lo |= ( (1<<7) | (1<<4) );<br>+ msr.lo |= ( (1 << 7) | (1 << 4) );<br> /* FIXME: Do we have a 6-bit or 7-bit VRM?<br> * set bit [5] for 7-bit, or don't set it for 6 bit VRM<br> * This will probably require a Kconfig option<br> * My board has a 7-bit VRM, so I can't test the 6-bit VRM stuff */<br>- msr.lo |= (1<<5);<br>+ msr.lo |= (1 << 5);<br> wrmsr(NANO_MYSTERIOUS_MSR, msr);<br> <br> /* Set the maximum frequency and voltage */<br>@@ -117,7 +117,7 @@<br> <br> /* Enable TM3 */<br> msr = rdmsr(MSR_IA32_MISC_ENABLE);<br>- msr.lo |= ( (1<<3) | (1<<13) );<br>+ msr.lo |= ( (1 << 3) | (1 << 13) );<br> wrmsr(MSR_IA32_MISC_ENABLE, msr);<br> <br> u8 stepping = ( cpuid_eax(0x1) ) &0xf;<br>@@ -125,14 +125,14 @@<br> /* Hello Nano 3000. The Terminator needs a CPU upgrade */<br> /* Enable C1e, C2e, C3e, and C4e states */<br> msr = rdmsr(MSR_IA32_MISC_ENABLE);<br>- msr.lo |= ( (1<<25) | (1<<26) | (1<<31)); /* C1e, C2e, C3e */<br>- msr.hi |= (1<<0); /* C4e */<br>+ msr.lo |= ( (1 << 25) | (1 << 26) | (1 << 31)); /* C1e, C2e, C3e */<br>+ msr.hi |= (1 << 0); /* C4e */<br> wrmsr(MSR_IA32_MISC_ENABLE, msr);<br> }<br> <br> /* Lock on Powersaver */<br> msr = rdmsr(MSR_IA32_MISC_ENABLE);<br>- msr.lo |= (1<<20);<br>+ msr.lo |= (1 << 20);<br> wrmsr(MSR_IA32_MISC_ENABLE, msr);<br> }<br> <br></pre><p>To view, visit <a href="https://review.coreboot.org/20397">change 20397</a>. To unsubscribe, visit <a href="https://review.coreboot.org/settings">settings</a>.</p><div itemscope itemtype="http://schema.org/EmailMessage"><div itemscope itemprop="action" itemtype="http://schema.org/ViewAction"><link itemprop="url" href="https://review.coreboot.org/20397"/><meta itemprop="name" content="View Change"/></div></div>
<div style="display:none"> Gerrit-Project: coreboot </div>
<div style="display:none"> Gerrit-Branch: master </div>
<div style="display:none"> Gerrit-MessageType: newchange </div>
<div style="display:none"> Gerrit-Change-Id: Id46c0b57bd7c9b954b29537c70254df947690e0b </div>
<div style="display:none"> Gerrit-Change-Number: 20397 </div>
<div style="display:none"> Gerrit-PatchSet: 1 </div>
<div style="display:none"> Gerrit-Owner: HAOUAS Elyes <ehaouas@noos.fr> </div>