<p>Marshall Dawson has uploaded this change for <strong>review</strong>.</p><p><a href="https://review.coreboot.org/20370">View Change</a></p><pre style="font-family: monospace,monospace; white-space: pre-wrap;">soc/amd/stoneyridge: Revise pci_devs.h file<br><br>Now that pci_devs.h is part of soc/ and not used for multiple<br>southbridges:<br> * Remove devices not present in the Stoney Ridge APU<br> * Complete the list to include additional devices besides<br> those in the FCH.<br><br>BUG=chrome-os-partner:62578372<br><br>Change-Id: I1cd2d5e41473f362bbfd28ee93788a292bc33991<br>Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com><br>---<br>M src/soc/amd/stoneyridge/include/soc/pci_devs.h<br>1 file changed, 231 insertions(+), 59 deletions(-)<br><br></pre><pre style="font-family: monospace,monospace; white-space: pre-wrap;">git pull ssh://review.coreboot.org:29418/coreboot refs/changes/70/20370/1</pre><pre style="font-family: monospace,monospace; white-space: pre-wrap;">diff --git a/src/soc/amd/stoneyridge/include/soc/pci_devs.h b/src/soc/amd/stoneyridge/include/soc/pci_devs.h<br>index e234678..8bea376 100644<br>--- a/src/soc/amd/stoneyridge/include/soc/pci_devs.h<br>+++ b/src/soc/amd/stoneyridge/include/soc/pci_devs.h<br>@@ -16,18 +16,242 @@<br> #ifndef _PI_STONEYRIDGE_PCI_DEVS_H_<br> #define _PI_STONEYRIDGE_PCI_DEVS_H_<br> <br>-#define BUS0 0<br>+#include <device/pci_def.h><br>+#include <rules.h><br>+<br>+/* HT Configuration */<br>+#define HT_DEV 0x18<br>+#define HT_FUNC 0<br>+#define HT_DEVID 0x15b0<br>+#define HT_DEVFN PCI_DEVFN(HT_DEV, HT_FUNC)<br>+<br>+/* Address Maps */<br>+#define ADDR_DEV 0x18<br>+#define ADDR_FUNC 1<br>+#define ADDR_DEVID 0x15b1<br>+#define ADDR_DEVFN PCI_DEVFN(ADDR_DEV, ADDR_FUNC)<br>+<br>+/* DRAM Configuration */<br>+#define DCT_DEV 0x18<br>+#define DCT_FUNC 2<br>+#define DCT_DEVID 0x15b2<br>+#define DCT_DEVFN PCI_DEVFN(DCT_DEV, DCT_FUNC)<br>+<br>+/* Misc. Configuration */<br>+#define MISC_DEV 0x18<br>+#define MISC_FUNC 3<br>+#define MISC_DEVID 0x15b3<br>+#define MISC_DEVFN PCI_DEVFN(MISC_DEV, MISC_FUNC)<br>+<br>+/* PM Configuration */<br>+#define PM_DEV 0x18<br>+#define PM_FUNC 4<br>+#define PM_DEVID 0x15b4<br>+#define PM_DEVFN PCI_DEVFN(PM_DEV, PM_FUNC)<br>+#if !defined(__SIMPLE_DEVICE__)<br>+ #include <device/device.h><br>+ #define DEV_D18F4 dev_find_slot(0, PM_DEVFN)<br>+#else<br>+ #define DEV_D18F4 PCI_DEV(0, PM_DEV, PM_FUNC)<br>+#endif<br>+<br>+/* Northbridge Configuration */<br>+#define NB_DEV 0x18<br>+#define NB_FUNC 5<br>+#define NB_DEVID 0x15b5<br>+#define NB_DEVFN PCI_DEVFN(NB_DEV, NB_FUNC)<br>+<br>+/* GNB Root Complex */<br>+#define GNB_DEV 0x0<br>+#define GNB_FUNC 0<br>+#define GNB_DEVID 0x1576<br>+#define GNB_DEVFN PCI_DEVFN(GNB_DEV, GNB_FUNC)<br>+<br>+/* IOMMU */<br>+#define IOMMU_DEV 0x0<br>+#define IOMMU_FUNC 2<br>+#define IOMMU_DEVID 0x1577<br>+#define IOMMU_DEVFN PCI_DEVFN(IOMMU_DEV, IOMMU_FUNC)<br>+<br>+/* Internal Graphics */<br>+#define GFX_DEV 0x1<br>+#define GFX_FUNC 0<br>+#define GFX_DEVID 098e4 /* subject to SKU/OPN variation */<br>+#define GFX_DEVFN PCI_DEVFN(GFX_DEV, GFX_FUNC)<br>+<br>+/* HD Audio 0 */<br>+#define HDA0_DEV 0x1<br>+#define HDA0_FUNC 1<br>+#define HDA0_DEVID 015b3<br>+#define HDA0_DEVFN PCI_DEVFN(HDA_DEV, HDA_FUNC)<br>+<br>+/* Host Bridge */<br>+#define HOST_DEV 0x2<br>+#define HOST_FUNC 0<br>+#define HOST_DEVID 0x157b<br>+#define HOST_DEVFN PCI_DEVFN(HOST_DEV, HOST_FUNC)<br>+<br>+/* PCIe GPP Bridge 0 */<br>+#define PCIE0_DEV 0x2<br>+#define PCIE0_FUNC 1<br>+#define PCIE0_DEVID 0x157c<br>+#define PCIE0_DEVFN PCI_DEVFN(PCIE0_DEV, PCIE0_FUNC)<br>+<br>+/* PCIe GPP Bridge 1 */<br>+#define PCIE1_DEV 0x2<br>+#define PCIE1_FUNC 2<br>+#define PCIE1_DEVID 0x157c<br>+#define PCIE1_DEVFN PCI_DEVFN(PCIE1_DEV, PCIE1_FUNC)<br>+<br>+/* PCIe GPP Bridge 2 */<br>+#define PCIE2_DEV 0x2<br>+#define PCIE2_FUNC 3<br>+#define PCIE2_DEVID 0x157c<br>+#define PCIE2_DEVFN PCI_DEVFN(PCIE2_DEV, PCIE2_FUNC)<br>+<br>+/* PCIe GPP Bridge 3 */<br>+#define PCIE3_DEV 0x2<br>+#define PCIE3_FUNC 4<br>+#define PCIE3_DEVID 0x157c<br>+#define PCIE3_DEVFN PCI_DEVFN(PCIE3_DEV, PCIE3_FUNC)<br>+<br>+/* PCIe GPP Bridge 4 */<br>+#define PCIE4_DEV 0x2<br>+#define PCIE4_FUNC 5<br>+#define PCIE4_DEVID 0x157c<br>+#define PCIE4_DEVFN PCI_DEVFN(PCIE4_DEV, PCIE4_FUNC)<br>+<br>+/* Platform Security Processor */<br>+#define PSP_DEV 0x8<br>+#define PSP_FUNC 0<br>+#define PSP_DEVID 0x1578<br>+#define PSP_DEVFN PCI_DEVFN(PSP_DEV, PSP_FUNC)<br>+<br>+/* HD Audio 1 */<br>+#define HDA1_DEV 0x9<br>+#define HDA1_FUNC 2<br>+#define HDA1_DEVID 0x157a<br>+#define HDA1_DEVFN PCI_DEVFN(HDA1_DEV, HDA1_FUNC)<br>+<br>+/* HT Configuration */<br>+#define HT_DEV 0x18<br>+#define HT_FUNC 0<br>+#define HT_DEVID 0x15b0<br>+#define HT_DEVFN PCI_DEVFN(HT_DEV, HT_FUNC)<br>+<br>+/* Address Maps */<br>+#define ADDR_DEV 0x18<br>+#define ADDR_FUNC 1<br>+#define ADDR_DEVID 0x15b1<br>+#define ADDR_DEVFN PCI_DEVFN(ADDR_DEV, ADDR_FUNC)<br>+<br>+/* DRAM Configuration */<br>+#define DCT_DEV 0x18<br>+#define DCT_FUNC 2<br>+#define DCT_DEVID 0x15b2<br>+#define DCT_DEVFN PCI_DEVFN(DCT_DEV, DCT_FUNC)<br>+<br>+/* Misc. Configuration */<br>+#define MISC_DEV 0x18<br>+#define MISC_FUNC 3<br>+#define MISC_DEVID 0x15b3<br>+#define MISC_DEVFN PCI_DEVFN(MISC_DEV, MISC_FUNC)<br>+<br>+/* PM Configuration */<br>+#define PM_DEV 0x18<br>+#define PM_FUNC 4<br>+#define PM_DEVID 0x15b4<br>+#define PM_DEVFN PCI_DEVFN(PM_DEV, PM_FUNC)<br>+#if !defined(__SIMPLE_DEVICE__)<br>+ #include <device/device.h><br>+ #define DEV_D18F4 dev_find_slot(0, PM_DEVFN)<br>+#else<br>+ #define DEV_D18F4 PCI_DEV(0, PM_DEV, PM_FUNC)<br>+#endif<br>+<br>+/* Northbridge Configuration */<br>+#define NB_DEV 0x18<br>+#define NB_FUNC 5<br>+#define NB_DEVID 0x15b5<br>+#define NB_DEVFN PCI_DEVFN(NB_DEV, NB_FUNC)<br>+<br>+/* GNB Root Complex */<br>+#define GNB_DEV 0x0<br>+#define GNB_FUNC 0<br>+#define GNB_DEVID 0x1576<br>+#define GNB_DEVFN PCI_DEVFN(GNB_DEV, GNB_FUNC)<br>+<br>+/* IOMMU */<br>+#define IOMMU_DEV 0x0<br>+#define IOMMU_FUNC 2<br>+#define IOMMU_DEVID 0x1577<br>+#define IOMMU_DEVFN PCI_DEVFN(IOMMU_DEV, IOMMU_FUNC)<br>+<br>+/* Internal Graphics */<br>+#define GFX_DEV 0x1<br>+#define GFX_FUNC 0<br>+#define GFX_DEVID 098e4 /* subject to SKU/OPN variation */<br>+#define GFX_DEVFN PCI_DEVFN(GFX_DEV, GFX_FUNC)<br>+<br>+/* HD Audio 0 */<br>+#define HDA0_DEV 0x1<br>+#define HDA0_FUNC 1<br>+#define HDA0_DEVID 015b3<br>+#define HDA0_DEVFN PCI_DEVFN(HDA_DEV, HDA_FUNC)<br>+<br>+/* Host Bridge */<br>+#define HOST_DEV 0x2<br>+#define HOST_FUNC 0<br>+#define HOST_DEVID 0x157b<br>+#define HOST_DEVFN PCI_DEVFN(HOST_DEV, HOST_FUNC)<br>+<br>+/* PCIe GPP Bridge 0 */<br>+#define PCIE0_DEV 0x2<br>+#define PCIE0_FUNC 1<br>+#define PCIE0_DEVID 0x157c<br>+#define PCIE0_DEVFN PCI_DEVFN(PCIE0_DEV, PCIE0_FUNC)<br>+<br>+/* PCIe GPP Bridge 1 */<br>+#define PCIE1_DEV 0x2<br>+#define PCIE1_FUNC 2<br>+#define PCIE1_DEVID 0x157c<br>+#define PCIE1_DEVFN PCI_DEVFN(PCIE1_DEV, PCIE1_FUNC)<br>+<br>+/* PCIe GPP Bridge 2 */<br>+#define PCIE2_DEV 0x2<br>+#define PCIE2_FUNC 3<br>+#define PCIE2_DEVID 0x157c<br>+#define PCIE2_DEVFN PCI_DEVFN(PCIE2_DEV, PCIE2_FUNC)<br>+<br>+/* PCIe GPP Bridge 3 */<br>+#define PCIE3_DEV 0x2<br>+#define PCIE3_FUNC 4<br>+#define PCIE3_DEVID 0x157c<br>+#define PCIE3_DEVFN PCI_DEVFN(PCIE3_DEV, PCIE3_FUNC)<br>+<br>+/* PCIe GPP Bridge 4 */<br>+#define PCIE4_DEV 0x2<br>+#define PCIE4_FUNC 5<br>+#define PCIE4_DEVID 0x157c<br>+#define PCIE4_DEVFN PCI_DEVFN(PCIE4_DEV, PCIE4_FUNC)<br>+<br>+/* Platform Security Processor */<br>+#define PSP_DEV 0x8<br>+#define PSP_FUNC 0<br>+#define PSP_DEVID 0x1578<br>+#define PSP_DEVFN PCI_DEVFN(PSP_DEV, PSP_FUNC)<br>+<br>+/* HD Audio 1 */<br>+#define HDA1_DEV 0x9<br>+#define HDA1_FUNC 2<br>+#define HDA1_DEVID 0x157a<br>+#define HDA1_DEVFN PCI_DEVFN(HDA1_DEV, HDA1_FUNC)<br> <br> /* XHCI */<br> #define XHCI_DEV 0x10<br> #define XHCI_FUNC 0<br> #define XHCI_DEVID 0x7914<br> #define XHCI_DEVFN PCI_DEVFN(XHCI_DEV, XHCI_FUNC)<br>-<br>-#define XHCI2_DEV 0x10<br>-#define XHCI2_FUNC 1<br>-#define XHCI2_DEVID 0x7814<br>-#define XHCI2_DEVFN PCI_DEVFN(XHCI2_DEV, XHCI2_FUNC)<br> <br> /* SATA */<br> #define SATA_DEV 0x11<br>@@ -37,52 +261,17 @@<br> #define AHCI_DEVID_AMD 0x7904<br> #define SATA_DEVFN PCI_DEVFN(SATA_DEV, SATA_FUNC)<br> <br>-/* OHCI */<br>-#define OHCI1_DEV 0x12<br>-#define OHCI1_FUNC 0<br>-#define OHCI2_DEV 0x13<br>-#define OHCI2_FUNC 0<br>-#define OHCI3_DEV 0x16<br>-#define OHCI3_FUNC 0<br>-#define OHCI4_DEV 0x14<br>-#define OHCI4_FUNC 5<br>-#define OHCI_DEVID 0x7807<br>-#define OHCI1_DEVFN PCI_DEVFN(OHCI1_DEV, OHCI1_FUNC)<br>-#define OHCI2_DEVFN PCI_DEVFN(OHCI2_DEV, OHCI2_FUNC)<br>-#define OHCI3_DEVFN PCI_DEVFN(OHCI3_DEV, OHCI3_FUNC)<br>-#define OHCI4_DEVFN PCI_DEVFN(OHCI4_DEV, OHCI4_FUNC)<br>-<br> /* EHCI */<br> #define EHCI_DEV 0x12<br> #define EHCI_FUNC 0<br>-#define EHCI2_DEV 0x13<br>-#define EHCI2_FUNC 2<br>-#define EHCI3_DEV 0x16<br>-#define EHCI3_FUNC 2<br> #define EHCI_DEVID 0x7908<br>-#define EHCI1_DEVFN PCI_DEVFN(EHCI1_DEV, EHCI1_FUNC)<br>-#define EHCI2_DEVFN PCI_DEVFN(EHCI2_DEV, EHCI2_FUNC)<br>-#define EHCI3_DEVFN PCI_DEVFN(EHCI3_DEV, EHCI3_FUNC)<br>+#define EHCI1_DEVFN PCI_DEVFN(EHCI_DEV, EHCI_FUNC)<br> <br> /* SMBUS */<br> #define SMBUS_DEV 0x14<br> #define SMBUS_FUNC 0<br> #define SMBUS_DEVID 0x790b<br> #define SMBUS_DEVFN PCI_DEVFN(SMBUS_DEV, SMBUS_FUNC)<br>-<br>-/* IDE */<br>-#if IS_ENABLED(CONFIG_SOUTHBRIDGE_AMD_PI_BOLTON)<br>-#define IDE_DEV 0x14<br>-#define IDE_FUNC 1<br>-#define IDE_DEVID 0x780c<br>-#define IDE_DEVFN PCI_DEVFN(IDE_DEV, IDE_FUNC)<br>-#endif<br>-<br>-/* HD Audio */<br>-#define HDA_DEV 0x14<br>-#define HDA_FUNC 2<br>-#define HDA_DEVID 0x780d<br>-#define HDA_DEVFN PCI_DEVFN(HDA_DEV, HDA_FUNC)<br> <br> /* LPC BUS */<br> #define PCU_DEV 0x14<br>@@ -95,22 +284,5 @@<br> #define SD_FUNC 7<br> #define SD_DEVID 0x7906<br> #define SD_DEVFN PCI_DEVFN(SD_DEV, SD_FUNC)<br>-<br>-/* PCIe Ports */<br>-#if IS_ENABLED(CONFIG_SOUTHBRIDGE_AMD_PI_BOLTON)<br>-#define SB_PCIE_DEV 0x15<br>-#define SB_PCIE_PORT1_FUNC 0<br>-#define SB_PCIE_PORT2_FUNC 1<br>-#define SB_PCIE_PORT3_FUNC 2<br>-#define SB_PCIE_PORT4_FUNC 3<br>-#define SB_PCIE_PORT1_DEVID 0x7820<br>-#define SB_PCIE_PORT2_DEVID 0x7821<br>-#define SB_PCIE_PORT3_DEVID 0x7822<br>-#define SB_PCIE_PORT4_DEVID 0x7823<br>-#define SB_PCIE_PORT1_DEVFN PCI_DEVFN(SB_PCIE_DEV, SB_PCIE_PORT1_FUNC)<br>-#define SB_PCIE_PORT2_DEVFN PCI_DEVFN(SB_PCIE_DEV, SB_PCIE_PORT2_FUNC)<br>-#define SB_PCIE_PORT3_DEVFN PCI_DEVFN(SB_PCIE_DEV, SB_PCIE_PORT3_FUNC)<br>-#define SB_PCIE_PORT4_DEVFN PCI_DEVFN(SB_PCIE_DEV, SB_PCIE_PORT4_FUNC)<br>-#endif<br> <br> #endif /* _PI_STONEYRIDGE_PCI_DEVS_H_ */<br></pre><p>To view, visit <a href="https://review.coreboot.org/20370">change 20370</a>. To unsubscribe, visit <a href="https://review.coreboot.org/settings">settings</a>.</p><div itemscope itemtype="http://schema.org/EmailMessage"><div itemscope itemprop="action" itemtype="http://schema.org/ViewAction"><link itemprop="url" href="https://review.coreboot.org/20370"/><meta itemprop="name" content="View Change"/></div></div>
<div style="display:none"> Gerrit-Project: coreboot </div>
<div style="display:none"> Gerrit-Branch: master </div>
<div style="display:none"> Gerrit-MessageType: newchange </div>
<div style="display:none"> Gerrit-Change-Id: I1cd2d5e41473f362bbfd28ee93788a292bc33991 </div>
<div style="display:none"> Gerrit-Change-Number: 20370 </div>
<div style="display:none"> Gerrit-PatchSet: 1 </div>
<div style="display:none"> Gerrit-Owner: Marshall Dawson <marshalldawson3rd@gmail.com> </div>