<p>Martin Roth has uploaded this change for <strong>review</strong>.</p><p><a href="https://review.coreboot.org/20335">View Change</a></p><pre style="font-family: monospace,monospace; white-space: pre-wrap;">cpu/amd: add IS_ENABLED() around Kconfig symbol references<br><br>Some of these can be changed from #if to if(), but that will happen<br>in a follow-on commmit.<br><br>Change-Id: I9f4155285529ec28e826637a61436478f648704c<br>Signed-off-by: Martin Roth <martinroth@google.com><br>---<br>M src/cpu/amd/agesa/amd_late_init.c<br>M src/cpu/amd/car/cache_as_ram.inc<br>M src/cpu/amd/dualcore/dualcore.c<br>M src/cpu/amd/family_10h-family_15h/fidvid.c<br>M src/cpu/amd/family_10h-family_15h/init_cpus.c<br>M src/cpu/amd/family_10h-family_15h/model_10xxx_init.c<br>M src/cpu/amd/geode_gx2/syspreinit.c<br>M src/cpu/amd/geode_lx/syspreinit.c<br>M src/cpu/amd/model_fxx/fidvid.c<br>M src/cpu/amd/model_fxx/init_cpus.c<br>M src/cpu/amd/model_fxx/microcode_blob.c<br>M src/cpu/amd/model_fxx/model_fxx_init.c<br>M src/cpu/amd/model_fxx/model_fxx_update_microcode.c<br>M src/cpu/amd/model_fxx/powernow_acpi.c<br>M src/cpu/amd/model_fxx/processor_name.c<br>M src/cpu/amd/pi/00630F01/model_15_init.c<br>M src/cpu/amd/pi/00660F01/model_15_init.c<br>M src/cpu/amd/pi/00670F00/model_15_init.c<br>M src/cpu/amd/pi/00730F01/model_16_init.c<br>M src/cpu/amd/quadcore/quadcore.c<br>20 files changed, 85 insertions(+), 84 deletions(-)<br><br></pre><pre style="font-family: monospace,monospace; white-space: pre-wrap;">git pull ssh://review.coreboot.org:29418/coreboot refs/changes/35/20335/1</pre><pre style="font-family: monospace,monospace; white-space: pre-wrap;">diff --git a/src/cpu/amd/agesa/amd_late_init.c b/src/cpu/amd/agesa/amd_late_init.c<br>index a55ebd8..9bb6b27 100644<br>--- a/src/cpu/amd/agesa/amd_late_init.c<br>+++ b/src/cpu/amd/agesa/amd_late_init.c<br>@@ -18,7 +18,7 @@<br> <br> #include <northbridge/amd/agesa/agesawrapper.h><br> <br>-#if CONFIG_AMD_SB_CIMX<br>+#if IS_ENABLED(CONFIG_AMD_SB_CIMX)<br> #include <sb_cimx.h><br> #endif<br> <br>@@ -29,7 +29,7 @@<br> <br> agesawrapper_amdinitlate();<br> <br>-#if CONFIG_AMD_SB_CIMX<br>+#if IS_ENABLED(CONFIG_AMD_SB_CIMX)<br> sb_Late_Post();<br> #endif<br> if (!acpi_s3_resume_allowed())<br>diff --git a/src/cpu/amd/car/cache_as_ram.inc b/src/cpu/amd/car/cache_as_ram.inc<br>index 156333f..e48d25c 100644<br>--- a/src/cpu/amd/car/cache_as_ram.inc<br>+++ b/src/cpu/amd/car/cache_as_ram.inc<br>@@ -143,7 +143,7 @@<br> <br> CAR_FAM10_errata_applied:<br> <br>-#if CONFIG_MMCONF_SUPPORT<br>+#if IS_ENABLED(CONFIG_MMCONF_SUPPORT)<br> #if (CONFIG_MMCONF_BASE_ADDRESS > 0xFFFFFFFF)<br> #error "MMCONF_BASE_ADDRESS too big"<br> #elif (CONFIG_MMCONF_BASE_ADDRESS & 0xFFFFF)<br>diff --git a/src/cpu/amd/dualcore/dualcore.c b/src/cpu/amd/dualcore/dualcore.c<br>index 83302ca..f3cb0972 100644<br>--- a/src/cpu/amd/dualcore/dualcore.c<br>+++ b/src/cpu/amd/dualcore/dualcore.c<br>@@ -15,7 +15,7 @@<br> <br> #include "cpu/amd/dualcore/dualcore_id.c"<br> #include <pc80/mc146818rtc.h><br>-#if CONFIG_HAVE_OPTION_TABLE<br>+#if IS_ENABLED(CONFIG_HAVE_OPTION_TABLE)<br> #include "option_table.h"<br> #endif<br> <br>@@ -30,7 +30,7 @@<br> <br> static inline uint8_t set_apicid_cpuid_lo(void)<br> {<br>-#if !CONFIG_K8_REV_F_SUPPORT<br>+#if !IS_ENABLED(CONFIG_K8_REV_F_SUPPORT)<br> if (is_cpu_pre_e0()) return 0; // pre_e0 can not be set<br> #endif<br> <br>diff --git a/src/cpu/amd/family_10h-family_15h/fidvid.c b/src/cpu/amd/family_10h-family_15h/fidvid.c<br>index 1262718..12fc2c7 100644<br>--- a/src/cpu/amd/family_10h-family_15h/fidvid.c<br>+++ b/src/cpu/amd/family_10h-family_15h/fidvid.c<br>@@ -94,21 +94,21 @@<br> <br> static inline void print_debug_fv(const char *str, u32 val)<br> {<br>-#if CONFIG_SET_FIDVID_DEBUG<br>+#if IS_ENABLED(CONFIG_SET_FIDVID_DEBUG)<br> printk(BIOS_DEBUG, "%s%x\n", str, val);<br> #endif<br> }<br> <br> static inline void print_debug_fv_8(const char *str, u8 val)<br> {<br>-#if CONFIG_SET_FIDVID_DEBUG<br>+#if IS_ENABLED(CONFIG_SET_FIDVID_DEBUG)<br> printk(BIOS_DEBUG, "%s%02x\n", str, val);<br> #endif<br> }<br> <br> static inline void print_debug_fv_64(const char *str, u32 val, u32 val2)<br> {<br>-#if CONFIG_SET_FIDVID_DEBUG<br>+#if IS_ENABLED(CONFIG_SET_FIDVID_DEBUG)<br> printk(BIOS_DEBUG, "%s%x%x\n", str, val, val2);<br> #endif<br> }<br>@@ -503,7 +503,7 @@<br> }<br> <br> /* TODO: look into C1E state and F3xA0[IdleExitEn]*/<br>- #if CONFIG_SVI_HIGH_FREQ<br>+ #if IS_ENABLED(CONFIG_SVI_HIGH_FREQ)<br> if (cpuRev & AMD_FAM10_C3) {<br> dword |= SVI_HIGH_FREQ_ON;<br> }<br>@@ -583,7 +583,7 @@<br> if (cpuRev & AMD_DR_Bx ) {<br> smaf001 = 0xA6;<br> } else {<br>- #if CONFIG_SVI_HIGH_FREQ<br>+ #if IS_ENABLED(CONFIG_SVI_HIGH_FREQ)<br> if (cpuRev & (AMD_RB_C3 | AMD_DA_C3)) {<br> smaf001 = 0xF6;<br> }<br>@@ -1034,7 +1034,7 @@<br> }<br> <br> <br>-#if CONFIG_SET_FIDVID_STORE_AP_APICID_AT_FIRST<br>+#if IS_ENABLED(CONFIG_SET_FIDVID_STORE_AP_APICID_AT_FIRST)<br> struct ap_apicid_st {<br> u32 num;<br> // it could use 256 bytes for 64 node quad core system<br>@@ -1053,7 +1053,7 @@<br> <br> int init_fidvid_bsp(u32 bsp_apicid, u32 nodes)<br> {<br>-#if CONFIG_SET_FIDVID_STORE_AP_APICID_AT_FIRST<br>+#if IS_ENABLED(CONFIG_SET_FIDVID_STORE_AP_APICID_AT_FIRST)<br> struct ap_apicid_st ap_apicidx;<br> u32 i;<br> #endif<br>@@ -1068,7 +1068,8 @@<br> <br> print_debug_fv("BSP fid = ", fv.common_fid);<br> <br>-#if CONFIG_SET_FIDVID_STORE_AP_APICID_AT_FIRST && !CONFIG_SET_FIDVID_CORE0_ONLY<br>+#if IS_ENABLED(CONFIG_SET_FIDVID_STORE_AP_APICID_AT_FIRST) && \<br>+ !IS_ENABLED(CONFIG_SET_FIDVID_CORE0_ONLY)<br> /* For all APs (We know the APIC ID of all APs even when the APIC ID<br> is lifted) remote read from AP LAPIC_MSG_REG about max fid.<br> Then calculate the common max fid that can be used for all<br>diff --git a/src/cpu/amd/family_10h-family_15h/init_cpus.c b/src/cpu/amd/family_10h-family_15h/init_cpus.c<br>index 2f90f43..c151aac 100644<br>--- a/src/cpu/amd/family_10h-family_15h/init_cpus.c<br>+++ b/src/cpu/amd/family_10h-family_15h/init_cpus.c<br>@@ -16,7 +16,7 @@<br> <br> #include "init_cpus.h"<br> <br>-#if CONFIG_HAVE_OPTION_TABLE<br>+#if IS_ENABLED(CONFIG_HAVE_OPTION_TABLE)<br> #include "option_table.h"<br> #endif<br> #include <pc80/mc146818rtc.h><br>@@ -36,7 +36,7 @@<br> <br> #include "cpu/amd/car/post_cache_as_ram.c"<br> <br>-#if CONFIG_PCI_IO_CFG_EXT<br>+#if IS_ENABLED(CONFIG_PCI_IO_CFG_EXT)<br> static void set_EnableCf8ExtCfg(void)<br> {<br> // set the NB_CFG[46]=1;<br>@@ -152,7 +152,7 @@<br> /* get_nodes define in ht_wrapper.c */<br> nodes = get_nodes();<br> <br>- if (!CONFIG_LOGICAL_CPUS ||<br>+ if (!IS_ENABLED(CONFIG_LOGICAL_CPUS) ||<br> read_option(multi_core, 0) != 0) { // 0 means multi core<br> disable_siblings = 1;<br> } else {<br>@@ -182,8 +182,8 @@<br> for (j = jstart; j <= jend; j++) {<br> ap_apicid = get_boot_apic_id(i, j);<br> <br>-#if CONFIG_ENABLE_APIC_EXT_ID && (CONFIG_APIC_ID_OFFSET > 0)<br>-#if !CONFIG_LIFT_BSP_APIC_ID<br>+#if IS_ENABLED(CONFIG_ENABLE_APIC_EXT_ID) && (CONFIG_APIC_ID_OFFSET > 0)<br>+#if !IS_ENABLED(CONFIG_LIFT_BSP_APIC_ID)<br> if ((i != 0) || (j != 0)) /* except bsp */<br> #endif<br> ap_apicid += CONFIG_APIC_ID_OFFSET;<br>@@ -227,7 +227,7 @@<br> return result;<br> }<br> <br>-#if CONFIG_SET_FIDVID<br>+#if IS_ENABLED(CONFIG_SET_FIDVID)<br> static void init_fidvid_ap(u32 apicid, u32 nodeid, u32 coreid);<br> #endif<br> <br>@@ -398,17 +398,17 @@<br> if (!is_fam15h())<br> set_apicid_cpuid_lo();<br> set_EnableCf8ExtCfg();<br>-#if CONFIG_ENABLE_APIC_EXT_ID<br>+#if IS_ENABLED(CONFIG_ENABLE_APIC_EXT_ID)<br> enable_apic_ext_id(id.nodeid);<br> #endif<br> }<br> <br> enable_lapic();<br> <br>-#if CONFIG_ENABLE_APIC_EXT_ID && (CONFIG_APIC_ID_OFFSET > 0)<br>+#if IS_ENABLED(CONFIG_ENABLE_APIC_EXT_ID) && (CONFIG_APIC_ID_OFFSET > 0)<br> u32 initial_apicid = get_initial_apicid();<br> <br>-#if !CONFIG_LIFT_BSP_APIC_ID<br>+#if !IS_ENABLED(CONFIG_LIFT_BSP_APIC_ID)<br> if (initial_apicid != 0) // other than bsp<br> #endif<br> {<br>@@ -420,7 +420,7 @@<br> <br> lapic_write(LAPIC_ID, dword);<br> }<br>-#if CONFIG_LIFT_BSP_APIC_ID<br>+#if IS_ENABLED(CONFIG_LIFT_BSP_APIC_ID)<br> bsp_apicid += CONFIG_APIC_ID_OFFSET;<br> #endif<br> <br>@@ -473,8 +473,8 @@<br> }<br> }<br> <br>-#if CONFIG_SET_FIDVID<br>-#if CONFIG_LOGICAL_CPUS && CONFIG_SET_FIDVID_CORE0_ONLY<br>+#if IS_ENABLED(CONFIG_SET_FIDVID)<br>+#if IS_ENABLED(CONFIG_LOGICAL_CPUS) && IS_ENABLED(CONFIG_SET_FIDVID_CORE0_ONLY)<br> // Run on all AP for proper FID/VID setup.<br> if (id.coreid == 0) // only need set fid for core0<br> #endif<br>@@ -574,7 +574,7 @@<br> /* Enable routing table */<br> printk(BIOS_DEBUG, "Start node %02x", node);<br> <br>-#if CONFIG_NORTHBRIDGE_AMD_AMDFAM10<br>+#if IS_ENABLED(CONFIG_NORTHBRIDGE_AMD_AMDFAM10)<br> /* For FAM10 support, we need to set Dram base/limit for the new node */<br> pci_write_config32(NODE_MP(node), 0x44, 0);<br> pci_write_config32(NODE_MP(node), 0x40, 3);<br>@@ -1865,7 +1865,7 @@<br> cpuSetAMDPCI(i);<br> }<br> <br>-#if CONFIG_SET_FIDVID<br>+#if IS_ENABLED(CONFIG_SET_FIDVID)<br> // Prep each node for FID/VID setup.<br> prep_fid_change();<br> #endif<br>diff --git a/src/cpu/amd/family_10h-family_15h/model_10xxx_init.c b/src/cpu/amd/family_10h-family_15h/model_10xxx_init.c<br>index b002b62..361a866 100644<br>--- a/src/cpu/amd/family_10h-family_15h/model_10xxx_init.c<br>+++ b/src/cpu/amd/family_10h-family_15h/model_10xxx_init.c<br>@@ -64,7 +64,7 @@<br> u8 i;<br> msr_t msr;<br> struct node_core_id id;<br>-#if CONFIG_LOGICAL_CPUS<br>+#if IS_ENABLED(CONFIG_LOGICAL_CPUS)<br> u32 siblings;<br> #endif<br> uint8_t delay_start;<br>@@ -124,7 +124,7 @@<br> /* Set the processor name string */<br> init_processor_name();<br> <br>-#if CONFIG_LOGICAL_CPUS<br>+#if IS_ENABLED(CONFIG_LOGICAL_CPUS)<br> siblings = cpuid_ecx(0x80000008) & 0xff;<br> <br> if (siblings > 0) {<br>diff --git a/src/cpu/amd/geode_gx2/syspreinit.c b/src/cpu/amd/geode_gx2/syspreinit.c<br>index 350e6df..aa1a39d 100644<br>--- a/src/cpu/amd/geode_gx2/syspreinit.c<br>+++ b/src/cpu/amd/geode_gx2/syspreinit.c<br>@@ -26,7 +26,7 @@<br> void SystemPreInit(void)<br> {<br> /* they want a jump ... */<br>-#if !CONFIG_CACHE_AS_RAM<br>+#if !IS_ENABLED(CONFIG_CACHE_AS_RAM)<br> __asm__ __volatile__("jmp .+2\ninvd\njmp .+2\n");<br> #endif<br> StartTimer1();<br>diff --git a/src/cpu/amd/geode_lx/syspreinit.c b/src/cpu/amd/geode_lx/syspreinit.c<br>index 4a59d02..de6e141 100644<br>--- a/src/cpu/amd/geode_lx/syspreinit.c<br>+++ b/src/cpu/amd/geode_lx/syspreinit.c<br>@@ -32,7 +32,7 @@<br> void SystemPreInit(void)<br> {<br> /* they want a jump ... */<br>-#if !CONFIG_CACHE_AS_RAM<br>+#if !IS_ENABLED(CONFIG_CACHE_AS_RAM)<br> __asm__ __volatile__("jmp .+2\ninvd\njmp .+2\n");<br> #endif<br> StartTimer1();<br>diff --git a/src/cpu/amd/model_fxx/fidvid.c b/src/cpu/amd/model_fxx/fidvid.c<br>index 20d0906..371d4b9 100644<br>--- a/src/cpu/amd/model_fxx/fidvid.c<br>+++ b/src/cpu/amd/model_fxx/fidvid.c<br>@@ -11,7 +11,7 @@<br> * GNU General Public License for more details.<br> */<br> <br>-#if CONFIG_SET_FIDVID<br>+#if IS_ENABLED(CONFIG_SET_FIDVID)<br> <br> #ifndef SB_VFSMAF<br> #define SB_VFSMAF 1<br>@@ -21,21 +21,21 @@<br> <br> static inline void print_debug_fv(const char *str, u32 val)<br> {<br>-#if CONFIG_SET_FIDVID_DEBUG<br>+#if IS_ENABLED(CONFIG_SET_FIDVID_DEBUG)<br> printk(BIOS_DEBUG, "%s%x\n", str, val);<br> #endif<br> }<br> <br> static inline void print_debug_fv_8(const char *str, u8 val)<br> {<br>-#if CONFIG_SET_FIDVID_DEBUG<br>+#if IS_ENABLED(CONFIG_SET_FIDVID_DEBUG)<br> printk(BIOS_DEBUG, "%s%02x\n", str, val);<br> #endif<br> }<br> <br> static inline void print_debug_fv_64(const char *str, u32 val, u32 val2)<br> {<br>-#if CONFIG_SET_FIDVID_DEBUG<br>+#if IS_ENABLED(CONFIG_SET_FIDVID_DEBUG)<br> printk(BIOS_DEBUG, "%s%x%x\n", str, val, val2);<br> #endif<br> }<br>@@ -59,7 +59,7 @@<br> <br> /* disable the DRAM interface at first, it will be enabled<br> * by raminit again (see also erratum #181) */<br>-#if CONFIG_K8_REV_F_SUPPORT<br>+#if IS_ENABLED(CONFIG_K8_REV_F_SUPPORT)<br> dword = pci_read_config32(PCI_DEV(0, 0x18 + i, 2), 0x94);<br> dword |= (1 << 14);<br> pci_write_config32(PCI_DEV(0, 0x18 + i, 2), 0x94, dword);<br>@@ -76,7 +76,7 @@<br> // dword = 0x00070000; /* enable FID/VID change */<br> pci_write_config32(PCI_DEV(0, 0x18 + i, 3), 0x80, dword);<br> <br>-#if CONFIG_HAVE_ACPI_RESUME<br>+#if IS_ENABLED(CONFIG_HAVE_ACPI_RESUME)<br> dword = 0x21132113;<br> #else<br> dword = 0x00132113;<br>@@ -86,7 +86,7 @@<br> }<br> }<br> <br>-#if !CONFIG_SET_FIDVID_ONE_BY_ONE<br>+#if !IS_ENABLED(CONFIG_SET_FIDVID_ONE_BY_ONE)<br> static unsigned set_fidvid_without_init(unsigned fidvid)<br> {<br> msr_t msr;<br>@@ -292,7 +292,7 @@<br> ldtstop_sb();<br> #endif<br> <br>-#if CONFIG_SET_FIDVID_DEBUG<br>+#if IS_ENABLED(CONFIG_SET_FIDVID_DEBUG)<br> if (showmessage) {<br> print_debug_fv_8("set_fidvid APICID = ", apicid);<br> print_debug_fv_64("fidvid ctrl msr ", msr.hi, msr.lo);<br>@@ -306,7 +306,7 @@<br> }<br> fid_cur = msr.lo & 0x3f;<br> <br>-#if CONFIG_SET_FIDVID_DEBUG<br>+#if IS_ENABLED(CONFIG_SET_FIDVID_DEBUG)<br> if (showmessage) {<br> print_debug_fv_64("fidvid status msr ", msr.hi, msr.lo);<br> }<br>@@ -387,7 +387,7 @@<br> send |= ((msr.hi >> (48 - 32)) & 0x3f) << 16; /* max vid */<br> send |= (apicid << 24); /* ap apicid */<br> <br>-#if CONFIG_SET_FIDVID_ONE_BY_ONE<br>+#if IS_ENABLED(CONFIG_SET_FIDVID_ONE_BY_ONE)<br> vid_cur = msr.hi & 0x3f;<br> fid_cur = msr.lo & 0x3f;<br> <br>@@ -418,7 +418,7 @@<br> }<br> <br> if (loop > 0) {<br>-#if CONFIG_SET_FIDVID_ONE_BY_ONE<br>+#if IS_ENABLED(CONFIG_SET_FIDVID_ONE_BY_ONE)<br> readback = set_fidvid(apicid, readback & 0xffff00, 1); // this AP<br> #else<br> readback = set_fidvid_without_init(readback & 0xffff00); // this AP<br>@@ -521,7 +521,7 @@<br> print_debug_fv("\treadback=", readback);<br> }<br> <br>-#if CONFIG_SET_FIDVID_STORE_AP_APICID_AT_FIRST<br>+#if IS_ENABLED(CONFIG_SET_FIDVID_STORE_AP_APICID_AT_FIRST)<br> struct ap_apicid_st {<br> u32 num;<br> unsigned apicid[16]; /* 8 way dual core need 16 */<br>@@ -543,7 +543,7 @@<br> <br> struct fidvid_st fv;<br> <br>-#if CONFIG_SET_FIDVID_STORE_AP_APICID_AT_FIRST<br>+#if IS_ENABLED(CONFIG_SET_FIDVID_STORE_AP_APICID_AT_FIRST)<br> struct ap_apicid_st ap_apicidx;<br> unsigned i;<br> #endif<br>@@ -573,7 +573,7 @@<br> <br> /* calculate the common max fid/vid that could be used for<br> * all APs and BSP */<br>-#if CONFIG_SET_FIDVID_STORE_AP_APICID_AT_FIRST<br>+#if IS_ENABLED(CONFIG_SET_FIDVID_STORE_AP_APICID_AT_FIRST)<br> ap_apicidx.num = 0;<br> <br> for_each_ap(bsp_apicid, CONFIG_SET_FIDVID_CORE0_ONLY, store_ap_apicid, &ap_apicidx);<br>@@ -609,7 +609,7 @@<br> <br> #endif<br> <br>-#if CONFIG_SET_FIDVID_ONE_BY_ONE<br>+#if IS_ENABLED(CONFIG_SET_FIDVID_ONE_BY_ONE)<br> /* set BSP fid and vid */<br> print_debug_fv("bsp apicid=", bsp_apicid);<br> fv.common_fidvid = set_fidvid(bsp_apicid, fv.common_fidvid, 1);<br>@@ -623,7 +623,7 @@<br> fv.common_fidvid &= 0xffff00;<br> <br> /* set state 2 allow is in init_fidvid_bsp_stage2 */<br>-#if CONFIG_SET_FIDVID_STORE_AP_APICID_AT_FIRST<br>+#if IS_ENABLED(CONFIG_SET_FIDVID_STORE_AP_APICID_AT_FIRST)<br> for (i = 0; i < ap_apicidx.num; i++) {<br> init_fidvid_bsp_stage2(ap_apicidx.apicid[i], &fv);<br> }<br>@@ -631,7 +631,7 @@<br> for_each_ap(bsp_apicid, CONFIG_SET_FIDVID_CORE0_ONLY, init_fidvid_bsp_stage2, &fv);<br> #endif<br> <br>-#if !CONFIG_SET_FIDVID_ONE_BY_ONE<br>+#if !IS_ENABLED(CONFIG_SET_FIDVID_ONE_BY_ONE)<br> /* set BSP fid and vid */<br> print_debug_fv("bsp apicid=", bsp_apicid);<br> fv.common_fidvid = set_fidvid(bsp_apicid, fv.common_fidvid, 1);<br>diff --git a/src/cpu/amd/model_fxx/init_cpus.c b/src/cpu/amd/model_fxx/init_cpus.c<br>index 035453e..48920bb 100644<br>--- a/src/cpu/amd/model_fxx/init_cpus.c<br>+++ b/src/cpu/amd/model_fxx/init_cpus.c<br>@@ -15,7 +15,7 @@<br> #include <northbridge/amd/amdk8/amdk8.h><br> #include "cpu/amd/car/post_cache_as_ram.c"<br> <br>-#if CONFIG_HAVE_OPTION_TABLE<br>+#if IS_ENABLED(CONFIG_HAVE_OPTION_TABLE)<br> #include "option_table.h"<br> #endif<br> <br>@@ -61,7 +61,7 @@<br> 3);<br> if (nb_cfg_54) {<br> if (j == 0) { // if it is single core, we need to increase siblings for APIC calculation<br>-#if !CONFIG_K8_REV_F_SUPPORT<br>+#if !IS_ENABLED(CONFIG_K8_REV_F_SUPPORT)<br> e0_later_single_core = is_e0_later_in_bsp(i); // single core<br> #else<br> e0_later_single_core = is_cpu_f0_in_bsp(i); // We can read cpuid(1) from Func3<br>@@ -93,8 +93,8 @@<br> i * (nb_cfg_54 ? (siblings + 1) : 1) +<br> j * (nb_cfg_54 ? 1 : 8);<br> <br>-#if CONFIG_ENABLE_APIC_EXT_ID<br>-#if !CONFIG_LIFT_BSP_APIC_ID<br>+#if IS_ENABLED(CONFIG_ENABLE_APIC_EXT_ID)<br>+#if !IS_ENABLED(CONFIG_LIFT_BSP_APIC_ID)<br> if ((i != 0) || (j != 0)) /* except bsp */<br> #endif<br> ap_apicid += CONFIG_APIC_ID_OFFSET;<br>@@ -140,7 +140,7 @@<br> <br> #define LAPIC_MSG_REG 0x380<br> <br>-#if CONFIG_SET_FIDVID<br>+#if IS_ENABLED(CONFIG_SET_FIDVID)<br> static void init_fidvid_ap(u32 bsp_apicid, u32 apicid);<br> #endif<br> <br>@@ -223,7 +223,7 @@<br> stop_this_cpu();<br> }<br> <br>-#if CONFIG_RAMINIT_SYSINFO<br>+#if IS_ENABLED(CONFIG_RAMINIT_SYSINFO)<br> static u32 init_cpus(u32 cpu_init_detectedx, struct sys_info *sysinfo)<br> #else<br> static u32 init_cpus(u32 cpu_init_detectedx)<br>@@ -265,10 +265,10 @@<br> enable_lapic();<br> // init_timer(); // We need TMICT to pass msg for FID/VID change<br> <br>-#if CONFIG_ENABLE_APIC_EXT_ID<br>+#if IS_ENABLED(CONFIG_ENABLE_APIC_EXT_ID)<br> u32 initial_apicid = get_initial_apicid();<br> <br>-#if !CONFIG_LIFT_BSP_APIC_ID<br>+#if !IS_ENABLED(CONFIG_LIFT_BSP_APIC_ID)<br> if (initial_apicid != 0) // other than bsp<br> #endif<br> {<br>@@ -280,7 +280,7 @@<br> <br> lapic_write(LAPIC_ID, dword);<br> }<br>-#if CONFIG_LIFT_BSP_APIC_ID<br>+#if IS_ENABLED(CONFIG_LIFT_BSP_APIC_ID)<br> bsp_apicid += CONFIG_APIC_ID_OFFSET;<br> #endif<br> <br>@@ -315,8 +315,8 @@<br> u32 timeout = 1;<br> u32 loop = 100;<br> <br>-#if CONFIG_SET_FIDVID<br>-#if CONFIG_LOGICAL_CPUS && CONFIG_SET_FIDVID_CORE0_ONLY<br>+#if IS_ENABLED(CONFIG_SET_FIDVID)<br>+#if IS_ENABLED(CONFIG_LOGICAL_CPUS) && IS_ENABLED(CONFIG_SET_FIDVID_CORE0_ONLY)<br> if (id.coreid == 0) // only need set fid for core0<br> #endif<br> init_fidvid_ap(bsp_apicid, apicid);<br>@@ -333,7 +333,7 @@<br> }<br> lapic_write(LAPIC_MSG_REG, (apicid << 24) | 0x44); // bsp can not check it before stop_this_cpu<br> set_var_mtrr(0, 0x00000000, CACHE_TMP_RAMTOP, MTRR_TYPE_WRBACK);<br>-#if CONFIG_K8_REV_F_SUPPORT<br>+#if IS_ENABLED(CONFIG_K8_REV_F_SUPPORT)<br> #if CONFIG_MEM_TRAIN_SEQ == 1<br> train_ram_on_node(id.nodeid, id.coreid, sysinfo,<br> (unsigned)STOP_CAR_AND_CPU);<br>diff --git a/src/cpu/amd/model_fxx/microcode_blob.c b/src/cpu/amd/model_fxx/microcode_blob.c<br>index 691ae83..98b418b 100644<br>--- a/src/cpu/amd/model_fxx/microcode_blob.c<br>+++ b/src/cpu/amd/model_fxx/microcode_blob.c<br>@@ -12,7 +12,7 @@<br> */<br> <br> unsigned char microcode[] __attribute__ ((aligned(16))) = {<br>-#if !CONFIG_K8_REV_F_SUPPORT<br>+#if !IS_ENABLED(CONFIG_K8_REV_F_SUPPORT)<br> #include "../../../../3rdparty/blobs/cpu/amd/model_fxx/microcode.h"<br> #endif<br> };<br>diff --git a/src/cpu/amd/model_fxx/model_fxx_init.c b/src/cpu/amd/model_fxx/model_fxx_init.c<br>index 8f4bae2..c21bce6 100644<br>--- a/src/cpu/amd/model_fxx/model_fxx_init.c<br>+++ b/src/cpu/amd/model_fxx/model_fxx_init.c<br>@@ -39,10 +39,10 @@<br> #include <cpu/amd/multicore.h><br> #include <cpu/amd/msr.h><br> <br>-#if CONFIG_WAIT_BEFORE_CPUS_INIT<br>+#if IS_ENABLED(CONFIG_WAIT_BEFORE_CPUS_INIT)<br> void cpus_ready_for_init(void)<br> {<br>-#if CONFIG_K8_REV_F_SUPPORT<br>+#if IS_ENABLED(CONFIG_K8_REV_F_SUPPORT)<br> #if CONFIG_MEM_TRAIN_SEQ == 1<br> struct sys_info *sysinfox = (struct sys_info *)((CONFIG_RAMTOP) - sizeof(*sysinfox));<br> // wait for ap memory to trained<br>@@ -511,7 +511,7 @@<br> /* Enable the local CPU APICs */<br> setup_lapic();<br> <br>-#if CONFIG_LOGICAL_CPUS<br>+#if IS_ENABLED(CONFIG_LOGICAL_CPUS)<br> u32 siblings = cpuid_ecx(0x80000008) & 0xff;<br> <br> if (siblings > 0) {<br>@@ -559,7 +559,7 @@<br> };<br> <br> static struct cpu_device_id cpu_table[] = {<br>-#if !CONFIG_K8_REV_F_SUPPORT<br>+#if !IS_ENABLED(CONFIG_K8_REV_F_SUPPORT)<br> { X86_VENDOR_AMD, 0xf40 }, /* SH-B0 (socket 754) */<br> { X86_VENDOR_AMD, 0xf50 }, /* SH-B0 (socket 940) */<br> { X86_VENDOR_AMD, 0xf51 }, /* SH-B3 (socket 940) */<br>@@ -601,7 +601,7 @@<br> { X86_VENDOR_AMD, 0x30ff2 }, /* E4 ? */<br> #endif<br> <br>-#if CONFIG_K8_REV_F_SUPPORT<br>+#if IS_ENABLED(CONFIG_K8_REV_F_SUPPORT)<br> /*<br> * AMD F0 support.<br> *<br>diff --git a/src/cpu/amd/model_fxx/model_fxx_update_microcode.c b/src/cpu/amd/model_fxx/model_fxx_update_microcode.c<br>index 4b70e58..6ae055b 100644<br>--- a/src/cpu/amd/model_fxx/model_fxx_update_microcode.c<br>+++ b/src/cpu/amd/model_fxx/model_fxx_update_microcode.c<br>@@ -26,7 +26,7 @@<br> <br> static u16 get_equivalent_processor_rev_id(u32 orig_id) {<br> static const struct id_mapping id_mapping_table[] = {<br>- #if !CONFIG_K8_REV_F_SUPPORT<br>+ #if !IS_ENABLED(CONFIG_K8_REV_F_SUPPORT)<br> { 0x0f48, 0x0048 },<br> { 0x0f58, 0x0048 },<br> <br>@@ -49,7 +49,7 @@<br> { 0x20fb1, 0x0210 },<br> #endif<br> <br>- #if CONFIG_K8_REV_F_SUPPORT<br>+ #if IS_ENABLED(CONFIG_K8_REV_F_SUPPORT)<br> /* FIXME<br> * Microcode files for CPU revision 0xf do<br> * not seem to be available...<br>diff --git a/src/cpu/amd/model_fxx/powernow_acpi.c b/src/cpu/amd/model_fxx/powernow_acpi.c<br>index 9979055..c718351 100644<br>--- a/src/cpu/amd/model_fxx/powernow_acpi.c<br>+++ b/src/cpu/amd/model_fxx/powernow_acpi.c<br>@@ -69,7 +69,7 @@<br> acpigen_pop_len();<br> }<br> <br>-#if CONFIG_K8_REV_F_SUPPORT<br>+#if IS_ENABLED(CONFIG_K8_REV_F_SUPPORT)<br> /*<br> * Details about this algorithm , refer to BDKG 10.5.1<br> * Two parts are included, the another is the DSDT reconstruction process<br>diff --git a/src/cpu/amd/model_fxx/processor_name.c b/src/cpu/amd/model_fxx/processor_name.c<br>index 60dbf6e..de6a514 100644<br>--- a/src/cpu/amd/model_fxx/processor_name.c<br>+++ b/src/cpu/amd/model_fxx/processor_name.c<br>@@ -39,7 +39,7 @@<br> * your mainboard will not be posted on the AMD Recommended Motherboard Website<br> */<br> <br>-#if !CONFIG_K8_REV_F_SUPPORT<br>+#if !IS_ENABLED(CONFIG_K8_REV_F_SUPPORT)<br> static const char *processor_names[]={<br> /* 0x00 */ "AMD Engineering Sample",<br> /* 0x01-0x03 */ NULL, NULL, NULL,<br>@@ -99,7 +99,7 @@<br> <br> int init_processor_name(void)<br> {<br>-#if !CONFIG_K8_REV_F_SUPPORT<br>+#if !IS_ENABLED(CONFIG_K8_REV_F_SUPPORT)<br> u32 EightBitBrandId;<br> #endif<br> u32 BrandId;<br>@@ -113,7 +113,7 @@<br> char program_string[48];<br> unsigned int *program_values = (unsigned int *)program_string;<br> <br>-#if !CONFIG_K8_REV_F_SUPPORT<br>+#if !IS_ENABLED(CONFIG_K8_REV_F_SUPPORT)<br> /* Find out which CPU brand it is */<br> EightBitBrandId = cpuid_ebx(0x00000001) & 0xff;<br> BrandId = cpuid_ebx(0x80000001) & 0xffff;<br>@@ -137,7 +137,7 @@<br> processor_name_string = "AMD Processor model unknown";<br> #endif<br> <br>-#if CONFIG_K8_REV_F_SUPPORT<br>+#if IS_ENABLED(CONFIG_K8_REV_F_SUPPORT)<br> u32 Socket;<br> u32 CmpCap;<br> u32 PwrLmt;<br>@@ -394,7 +394,7 @@<br> for (i=0; i<47; i++) { // 48 -1<br> if (program_string[i] == program_string[i+1]) {<br> switch (program_string[i]) {<br>-#if !CONFIG_K8_REV_F_SUPPORT<br>+#if !IS_ENABLED(CONFIG_K8_REV_F_SUPPORT)<br> case 'X': ModelNumber = 22+ NN; break;<br> case 'Y': ModelNumber = 38 + (2*NN); break;<br> case 'Z':<br>@@ -403,7 +403,7 @@<br> case 'V': ModelNumber = 9 + NN; break;<br> #endif<br> <br>-#if CONFIG_K8_REV_F_SUPPORT<br>+#if IS_ENABLED(CONFIG_K8_REV_F_SUPPORT)<br> case 'R': ModelNumber = NN - 1; break;<br> case 'P': ModelNumber = 26 + NN; break;<br> case 'T': ModelNumber = 15 + (CmpCap * 10) + NN; break;<br>diff --git a/src/cpu/amd/pi/00630F01/model_15_init.c b/src/cpu/amd/pi/00630F01/model_15_init.c<br>index c2f2e9d..317aca8 100644<br>--- a/src/cpu/amd/pi/00630F01/model_15_init.c<br>+++ b/src/cpu/amd/pi/00630F01/model_15_init.c<br>@@ -39,7 +39,7 @@<br> msr_t msr;<br> int msrno;<br> unsigned int cpu_idx;<br>-#if CONFIG_LOGICAL_CPUS<br>+#if IS_ENABLED(CONFIG_LOGICAL_CPUS)<br> u32 siblings;<br> #endif<br> <br>@@ -79,7 +79,7 @@<br> /* Enable the local CPU APICs */<br> setup_lapic();<br> <br>-#if CONFIG_LOGICAL_CPUS<br>+#if IS_ENABLED(CONFIG_LOGICAL_CPUS)<br> siblings = cpuid_ecx(0x80000008) & 0xff;<br> <br> if (siblings > 0) {<br>diff --git a/src/cpu/amd/pi/00660F01/model_15_init.c b/src/cpu/amd/pi/00660F01/model_15_init.c<br>index c31dec8..8f739cf 100644<br>--- a/src/cpu/amd/pi/00660F01/model_15_init.c<br>+++ b/src/cpu/amd/pi/00660F01/model_15_init.c<br>@@ -54,7 +54,7 @@<br> u8 i;<br> msr_t msr;<br> int msrno;<br>-#if CONFIG_LOGICAL_CPUS<br>+#if IS_ENABLED(CONFIG_LOGICAL_CPUS)<br> u32 siblings;<br> #endif<br> <br>@@ -93,7 +93,7 @@<br> /* Enable the local CPU APICs */<br> setup_lapic();<br> <br>-#if CONFIG_LOGICAL_CPUS<br>+#if IS_ENABLED(CONFIG_LOGICAL_CPUS)<br> siblings = cpuid_ecx(0x80000008) & 0xff;<br> <br> if (siblings > 0) {<br>diff --git a/src/cpu/amd/pi/00670F00/model_15_init.c b/src/cpu/amd/pi/00670F00/model_15_init.c<br>index 02e5b79..5550b99 100644<br>--- a/src/cpu/amd/pi/00670F00/model_15_init.c<br>+++ b/src/cpu/amd/pi/00670F00/model_15_init.c<br>@@ -54,7 +54,7 @@<br> u8 i;<br> msr_t msr;<br> int msrno;<br>-#if CONFIG_LOGICAL_CPUS<br>+#if IS_ENABLED(CONFIG_LOGICAL_CPUS)<br> u32 siblings;<br> #endif<br> <br>@@ -92,7 +92,7 @@<br> /* Enable the local CPU APICs */<br> setup_lapic();<br> <br>-#if CONFIG_LOGICAL_CPUS<br>+#if IS_ENABLED(CONFIG_LOGICAL_CPUS)<br> siblings = cpuid_ecx(0x80000008) & 0xff;<br> <br> if (siblings > 0) {<br>diff --git a/src/cpu/amd/pi/00730F01/model_16_init.c b/src/cpu/amd/pi/00730F01/model_16_init.c<br>index 294814f..ddea603 100644<br>--- a/src/cpu/amd/pi/00730F01/model_16_init.c<br>+++ b/src/cpu/amd/pi/00730F01/model_16_init.c<br>@@ -37,7 +37,7 @@<br> u8 i;<br> msr_t msr;<br> int msrno;<br>-#if CONFIG_LOGICAL_CPUS<br>+#if IS_ENABLED(CONFIG_LOGICAL_CPUS)<br> u32 siblings;<br> #endif<br> <br>@@ -76,7 +76,7 @@<br> /* Enable the local CPU APICs */<br> setup_lapic();<br> <br>-#if CONFIG_LOGICAL_CPUS<br>+#if IS_ENABLED(CONFIG_LOGICAL_CPUS)<br> siblings = cpuid_ecx(0x80000008) & 0xff;<br> <br> if (siblings > 0) {<br>diff --git a/src/cpu/amd/quadcore/quadcore.c b/src/cpu/amd/quadcore/quadcore.c<br>index 2f0822e..097a88f 100644<br>--- a/src/cpu/amd/quadcore/quadcore.c<br>+++ b/src/cpu/amd/quadcore/quadcore.c<br>@@ -16,7 +16,7 @@<br> <br> #include <console/console.h><br> #include <pc80/mc146818rtc.h><br>-#if CONFIG_HAVE_OPTION_TABLE<br>+#if IS_ENABLED(CONFIG_HAVE_OPTION_TABLE)<br> #include "option_table.h"<br> #endif<br> <br></pre><p>To view, visit <a href="https://review.coreboot.org/20335">change 20335</a>. To unsubscribe, visit <a href="https://review.coreboot.org/settings">settings</a>.</p><div itemscope itemtype="http://schema.org/EmailMessage"><div itemscope itemprop="action" itemtype="http://schema.org/ViewAction"><link itemprop="url" href="https://review.coreboot.org/20335"/><meta itemprop="name" content="View Change"/></div></div>
<div style="display:none"> Gerrit-Project: coreboot </div>
<div style="display:none"> Gerrit-Branch: master </div>
<div style="display:none"> Gerrit-MessageType: newchange </div>
<div style="display:none"> Gerrit-Change-Id: I9f4155285529ec28e826637a61436478f648704c </div>
<div style="display:none"> Gerrit-Change-Number: 20335 </div>
<div style="display:none"> Gerrit-PatchSet: 1 </div>
<div style="display:none"> Gerrit-Owner: Martin Roth <martinroth@google.com> </div>