<p>Martin Roth has uploaded this change for <strong>review</strong>.</p><p><a href="https://review.coreboot.org/20343">View Change</a></p><pre style="font-family: monospace,monospace; white-space: pre-wrap;">mainboard/[g-l]: add IS_ENABLED() around Kconfig symbol references<br><br>Change-Id: I1f906c8c465108017bc4d08534653233078ef32d<br>Signed-off-by: Martin Roth <martinroth@google.com><br>---<br>M src/mainboard/gigabyte/ga_2761gxdk/romstage.c<br>M src/mainboard/gigabyte/m57sli/romstage.c<br>M src/mainboard/gigabyte/ma785gm/romstage.c<br>M src/mainboard/gigabyte/ma785gmt/romstage.c<br>M src/mainboard/gigabyte/ma78gm/romstage.c<br>M src/mainboard/google/auron/smihandler.c<br>M src/mainboard/google/beltino/acpi_tables.c<br>M src/mainboard/google/butterfly/romstage.c<br>M src/mainboard/google/foster/chromeos.c<br>M src/mainboard/google/link/acpi_tables.c<br>M src/mainboard/google/link/mainboard.c<br>M src/mainboard/google/link/mainboard_smi.c<br>M src/mainboard/google/nyan_blaze/romstage.c<br>M src/mainboard/google/parrot/acpi_tables.c<br>M src/mainboard/google/parrot/smihandler.c<br>M src/mainboard/google/rambi/mainboard.c<br>M src/mainboard/google/rambi/mainboard_smi.c<br>M src/mainboard/google/slippy/acpi_tables.c<br>M src/mainboard/google/slippy/smihandler.c<br>M src/mainboard/google/storm/mainboard.c<br>M src/mainboard/google/stout/acpi_tables.c<br>M src/mainboard/google/stout/ec.c<br>M src/mainboard/hp/dl145_g1/romstage.c<br>M src/mainboard/hp/dl145_g3/mptable.c<br>M src/mainboard/hp/dl145_g3/romstage.c<br>M src/mainboard/hp/dl165_g6_fam10/mptable.c<br>M src/mainboard/hp/dl165_g6_fam10/romstage.c<br>M src/mainboard/hp/pavilion_m6_1035dx/buildOpts.c<br>M src/mainboard/iei/kino-780am2-fam10/romstage.c<br>M src/mainboard/intel/baskingridge/acpi_tables.c<br>M src/mainboard/intel/bayleybay_fsp/mainboard.c<br>M src/mainboard/intel/camelbackmountain_fsp/mainboard.c<br>M src/mainboard/intel/cougar_canyon2/romstage.c<br>M src/mainboard/intel/eagleheights/fadt.c<br>M src/mainboard/iwill/dk8_htx/mptable.c<br>M src/mainboard/iwill/dk8_htx/romstage.c<br>M src/mainboard/jetway/pa78vm5/romstage.c<br>M src/mainboard/kontron/kt690/romstage.c<br>M src/mainboard/kontron/ktqm77/mainboard.c<br>M src/mainboard/lenovo/g505s/buildOpts.c<br>M src/mainboard/lenovo/t400/romstage.c<br>M src/mainboard/lenovo/x200/romstage.c<br>M src/mainboard/lenovo/x201/romstage.c<br>M src/mainboard/lippert/frontrunner/romstage.c<br>M src/mainboard/lippert/hurricane-lx/mainboard.c<br>M src/mainboard/lippert/hurricane-lx/romstage.c<br>M src/mainboard/lippert/literunner-lx/mainboard.c<br>M src/mainboard/lippert/literunner-lx/romstage.c<br>M src/mainboard/lippert/roadrunner-lx/mainboard.c<br>M src/mainboard/lippert/roadrunner-lx/romstage.c<br>M src/mainboard/lippert/spacerunner-lx/mainboard.c<br>M src/mainboard/lippert/spacerunner-lx/romstage.c<br>52 files changed, 88 insertions(+), 87 deletions(-)<br><br></pre><pre style="font-family: monospace,monospace; white-space: pre-wrap;">git pull ssh://review.coreboot.org:29418/coreboot refs/changes/43/20343/1</pre><pre style="font-family: monospace,monospace; white-space: pre-wrap;">diff --git a/src/mainboard/gigabyte/ga_2761gxdk/romstage.c b/src/mainboard/gigabyte/ga_2761gxdk/romstage.c<br>index 6a18e98..79debd7 100644<br>--- a/src/mainboard/gigabyte/ga_2761gxdk/romstage.c<br>+++ b/src/mainboard/gigabyte/ga_2761gxdk/romstage.c<br>@@ -137,7 +137,7 @@<br> setup_coherent_ht_domain(); // routing table and start other core0<br> <br> wait_all_core0_started();<br>-#if CONFIG_LOGICAL_CPUS<br>+#if IS_ENABLED(CONFIG_LOGICAL_CPUS)<br> // It is said that we should start core1 after all core0 launched<br> /* becase optimize_link_coherent_ht is moved out from setup_coherent_ht_domain,<br> * So here need to make sure last core0 is started, esp for two way system,<br>@@ -150,7 +150,7 @@<br> /* it will set up chains and store link pair for optimization later */<br> ht_setup_chains_x(sysinfo); // it will init sblnk and sbbusn, nodes, sbdn<br> <br>-#if CONFIG_SET_FIDVID<br>+#if IS_ENABLED(CONFIG_SET_FIDVID)<br> {<br> msr_t msr;<br> msr = rdmsr(0xc0010042);<br>diff --git a/src/mainboard/gigabyte/m57sli/romstage.c b/src/mainboard/gigabyte/m57sli/romstage.c<br>index d4b6367..7346657 100644<br>--- a/src/mainboard/gigabyte/m57sli/romstage.c<br>+++ b/src/mainboard/gigabyte/m57sli/romstage.c<br>@@ -155,7 +155,7 @@<br> setup_coherent_ht_domain(); // routing table and start other core0<br> <br> wait_all_core0_started();<br>-#if CONFIG_LOGICAL_CPUS<br>+#if IS_ENABLED(CONFIG_LOGICAL_CPUS)<br> // It is said that we should start core1 after all core0 launched<br> /* becase optimize_link_coherent_ht is moved out from setup_coherent_ht_domain,<br> * So here need to make sure last core0 is started, esp for two way system,<br>@@ -168,7 +168,7 @@<br> /* it will set up chains and store link pair for optimization later */<br> ht_setup_chains_x(sysinfo); // it will init sblnk and sbbusn, nodes, sbdn<br> <br>-#if CONFIG_SET_FIDVID<br>+#if IS_ENABLED(CONFIG_SET_FIDVID)<br> {<br> msr_t msr;<br> msr = rdmsr(0xc0010042);<br>diff --git a/src/mainboard/gigabyte/ma785gm/romstage.c b/src/mainboard/gigabyte/ma785gm/romstage.c<br>index 2e22556..12fe12c 100644<br>--- a/src/mainboard/gigabyte/ma785gm/romstage.c<br>+++ b/src/mainboard/gigabyte/ma785gm/romstage.c<br>@@ -137,7 +137,7 @@<br> */<br> wait_all_core0_started();<br> <br>-#if CONFIG_LOGICAL_CPUS<br>+#if IS_ENABLED(CONFIG_LOGICAL_CPUS)<br> /* Core0 on each node is configured. Now setup any additional cores. */<br> printk(BIOS_DEBUG, "start_other_cores()\n");<br> start_other_cores(bsp_apicid);<br>@@ -151,7 +151,7 @@<br> rs780_early_setup();<br> sb7xx_51xx_early_setup();<br> <br>-#if CONFIG_SET_FIDVID<br>+#if IS_ENABLED(CONFIG_SET_FIDVID)<br> msr = rdmsr(0xc0010071);<br> printk(BIOS_DEBUG, "\nBegin FIDVID MSR 0xc0010071 0x%08x 0x%08x\n", msr.hi, msr.lo);<br> <br>diff --git a/src/mainboard/gigabyte/ma785gmt/romstage.c b/src/mainboard/gigabyte/ma785gmt/romstage.c<br>index bf51e38..6747a62 100644<br>--- a/src/mainboard/gigabyte/ma785gmt/romstage.c<br>+++ b/src/mainboard/gigabyte/ma785gmt/romstage.c<br>@@ -137,7 +137,7 @@<br> */<br> wait_all_core0_started();<br> <br>-#if CONFIG_LOGICAL_CPUS<br>+#if IS_ENABLED(CONFIG_LOGICAL_CPUS)<br> /* Core0 on each node is configured. Now setup any additional cores. */<br> printk(BIOS_DEBUG, "start_other_cores()\n");<br> start_other_cores(bsp_apicid);<br>@@ -151,7 +151,7 @@<br> rs780_early_setup();<br> sb7xx_51xx_early_setup();<br> <br>-#if CONFIG_SET_FIDVID<br>+#if IS_ENABLED(CONFIG_SET_FIDVID)<br> msr = rdmsr(0xc0010071);<br> printk(BIOS_DEBUG, "\nBegin FIDVID MSR 0xc0010071 0x%08x 0x%08x\n", msr.hi, msr.lo);<br> <br>diff --git a/src/mainboard/gigabyte/ma78gm/romstage.c b/src/mainboard/gigabyte/ma78gm/romstage.c<br>index 1405507..ff9ced2 100644<br>--- a/src/mainboard/gigabyte/ma78gm/romstage.c<br>+++ b/src/mainboard/gigabyte/ma78gm/romstage.c<br>@@ -139,7 +139,7 @@<br> */<br> wait_all_core0_started();<br> <br>-#if CONFIG_LOGICAL_CPUS<br>+#if IS_ENABLED(CONFIG_LOGICAL_CPUS)<br> /* Core0 on each node is configured. Now setup any additional cores. */<br> printk(BIOS_DEBUG, "start_other_cores()\n");<br> start_other_cores(bsp_apicid);<br>@@ -153,7 +153,7 @@<br> rs780_early_setup();<br> sb7xx_51xx_early_setup();<br> <br>-#if CONFIG_SET_FIDVID<br>+#if IS_ENABLED(CONFIG_SET_FIDVID)<br> msr = rdmsr(0xc0010071);<br> printk(BIOS_DEBUG, "\nBegin FIDVID MSR 0xc0010071 0x%08x 0x%08x\n", msr.hi, msr.lo);<br> <br>diff --git a/src/mainboard/google/auron/smihandler.c b/src/mainboard/google/auron/smihandler.c<br>index 03d07b9..247fc2f 100644<br>--- a/src/mainboard/google/auron/smihandler.c<br>+++ b/src/mainboard/google/auron/smihandler.c<br>@@ -33,7 +33,7 @@<br> u8 cmd = google_chromeec_get_event();<br> u32 pm1_cnt;<br> <br>-#if CONFIG_ELOG_GSMI<br>+#if IS_ENABLED(CONFIG_ELOG_GSMI)<br> /* Log this event */<br> if (cmd)<br> elog_add_event_byte(ELOG_TYPE_EC_EVENT, cmd);<br>diff --git a/src/mainboard/google/beltino/acpi_tables.c b/src/mainboard/google/beltino/acpi_tables.c<br>index 6eaa5e2..86a25fc 100644<br>--- a/src/mainboard/google/beltino/acpi_tables.c<br>+++ b/src/mainboard/google/beltino/acpi_tables.c<br>@@ -72,7 +72,7 @@<br> gnvs->tpmp = 1;<br> <br> <br>-#if CONFIG_CHROMEOS<br>+#if IS_ENABLED(CONFIG_CHROMEOS)<br> // SuperIO is always RO<br> gnvs->chromeos.vbt2 = ACTIVE_ECFW_RO;<br> #endif<br>diff --git a/src/mainboard/google/butterfly/romstage.c b/src/mainboard/google/butterfly/romstage.c<br>index 70916d5..1ce25b4 100644<br>--- a/src/mainboard/google/butterfly/romstage.c<br>+++ b/src/mainboard/google/butterfly/romstage.c<br>@@ -34,7 +34,7 @@<br> #include <arch/cpu.h><br> #include <cpu/x86/msr.h><br> #include <halt.h><br>-#if CONFIG_CHROMEOS<br>+#if IS_ENABLED(CONFIG_CHROMEOS)<br> #include <vendorcode/google/chromeos/chromeos.h><br> #endif<br> #include <cbfs.h><br>diff --git a/src/mainboard/google/foster/chromeos.c b/src/mainboard/google/foster/chromeos.c<br>index 3f86c29..bd17c4d 100644<br>--- a/src/mainboard/google/foster/chromeos.c<br>+++ b/src/mainboard/google/foster/chromeos.c<br>@@ -68,7 +68,7 @@<br> <br> int get_recovery_mode_switch(void)<br> {<br>-#if CONFIG_EC_GOOGLE_CHROMEEC<br>+#if IS_ENABLED(CONFIG_EC_GOOGLE_CHROMEEC)<br> uint32_t ec_events;<br> <br> ec_events = google_chromeec_get_events_b();<br>diff --git a/src/mainboard/google/link/acpi_tables.c b/src/mainboard/google/link/acpi_tables.c<br>index 13c358b..28d9922 100644<br>--- a/src/mainboard/google/link/acpi_tables.c<br>+++ b/src/mainboard/google/link/acpi_tables.c<br>@@ -58,7 +58,7 @@<br> gnvs->s5u0 = 0;<br> gnvs->s5u1 = 0;<br> <br>-#if CONFIG_CHROMEOS<br>+#if IS_ENABLED(CONFIG_CHROMEOS)<br> gnvs->chromeos.vbt2 = google_ec_running_ro() ?<br> ACTIVE_ECFW_RO : ACTIVE_ECFW_RW;<br> #endif<br>diff --git a/src/mainboard/google/link/mainboard.c b/src/mainboard/google/link/mainboard.c<br>index 53915d2..24062e9 100644<br>--- a/src/mainboard/google/link/mainboard.c<br>+++ b/src/mainboard/google/link/mainboard.c<br>@@ -21,7 +21,7 @@<br> #include <device/pci_def.h><br> #include <device/pci_ops.h><br> #include <console/console.h><br>-#if CONFIG_VGA_ROM_RUN<br>+#if IS_ENABLED(CONFIG_VGA_ROM_RUN)<br> #include <x86emu/x86emu.h><br> #endif<br> #include <pc80/mc146818rtc.h><br>@@ -52,7 +52,7 @@<br> */<br> }<br> <br>-#if CONFIG_VGA_ROM_RUN<br>+#if IS_ENABLED(CONFIG_VGA_ROM_RUN)<br> static int int15_handler(void)<br> {<br> int res = 0;<br>@@ -201,7 +201,7 @@<br> dev->ops->init = mainboard_init;<br> dev->ops->get_smbios_data = link_onboard_smbios_data;<br> dev->ops->acpi_inject_dsdt_generator = chromeos_dsdt_generator;<br>-#if CONFIG_VGA_ROM_RUN<br>+#if IS_ENABLED(CONFIG_VGA_ROM_RUN)<br> /* Install custom int15 handler for VGA OPROM */<br> mainboard_interrupt_handlers(0x15, &int15_handler);<br> #endif<br>diff --git a/src/mainboard/google/link/mainboard_smi.c b/src/mainboard/google/link/mainboard_smi.c<br>index a0d3803..0babb54 100644<br>--- a/src/mainboard/google/link/mainboard_smi.c<br>+++ b/src/mainboard/google/link/mainboard_smi.c<br>@@ -33,7 +33,7 @@<br> u8 cmd = google_chromeec_get_event();<br> u32 pm1_cnt;<br> <br>-#if CONFIG_ELOG_GSMI<br>+#if IS_ENABLED(CONFIG_ELOG_GSMI)<br> /* Log this event */<br> if (cmd)<br> elog_add_event_byte(ELOG_TYPE_EC_EVENT, cmd);<br>diff --git a/src/mainboard/google/nyan_blaze/romstage.c b/src/mainboard/google/nyan_blaze/romstage.c<br>index e3d7116..f094e34 100644<br>--- a/src/mainboard/google/nyan_blaze/romstage.c<br>+++ b/src/mainboard/google/nyan_blaze/romstage.c<br>@@ -53,7 +53,7 @@<br> u32 dram_end_mb = sdram_max_addressable_mb();<br> u32 dram_size_mb = dram_end_mb - dram_start_mb;<br> <br>-#if !CONFIG_VBOOT<br>+#if !IS_ENABLED(CONFIG_VBOOT)<br> configure_l2_cache();<br> mmu_init();<br> /* Device memory below DRAM is uncached. */<br>@@ -96,7 +96,7 @@<br> /* Stub to force arm_init_caches to the top, before any stack/memory accesses */<br> void main(void)<br> {<br>-#if !CONFIG_VBOOT<br>+#if !IS_ENABLED(CONFIG_VBOOT)<br> asm volatile ("bl arm_init_caches"<br> ::: "r0","r1","r2","r3","r4","r5","ip");<br> #endif<br>diff --git a/src/mainboard/google/parrot/acpi_tables.c b/src/mainboard/google/parrot/acpi_tables.c<br>index 2cda4a2..ae36ba0 100644<br>--- a/src/mainboard/google/parrot/acpi_tables.c<br>+++ b/src/mainboard/google/parrot/acpi_tables.c<br>@@ -51,7 +51,7 @@<br> gnvs->s5u1 = 0;<br> <br> <br>-#if CONFIG_CHROMEOS<br>+#if IS_ENABLED(CONFIG_CHROMEOS)<br> gnvs->chromeos.vbt2 = parrot_ec_running_ro() ?<br> ACTIVE_ECFW_RO : ACTIVE_ECFW_RW;<br> #endif<br>diff --git a/src/mainboard/google/parrot/smihandler.c b/src/mainboard/google/parrot/smihandler.c<br>index 351f082..176e33c 100644<br>--- a/src/mainboard/google/parrot/smihandler.c<br>+++ b/src/mainboard/google/parrot/smihandler.c<br>@@ -29,7 +29,7 @@<br> {<br> u8 src;<br> u32 pm1_cnt;<br>-#if CONFIG_ELOG_GSMI<br>+#if IS_ENABLED(CONFIG_ELOG_GSMI)<br> static int battery_critical_logged;<br> #endif<br> <br>@@ -39,7 +39,7 @@<br> <br> switch (src) {<br> case EC_BATTERY_CRITICAL:<br>-#if CONFIG_ELOG_GSMI<br>+#if IS_ENABLED(CONFIG_ELOG_GSMI)<br> if (!battery_critical_logged)<br> elog_add_event_byte(ELOG_TYPE_EC_EVENT,<br> EC_EVENT_BATTERY_CRITICAL);<br>@@ -49,7 +49,7 @@<br> case EC_LID_CLOSE:<br> printk(BIOS_DEBUG, "LID CLOSED, SHUTDOWN\n");<br> <br>-#if CONFIG_ELOG_GSMI<br>+#if IS_ENABLED(CONFIG_ELOG_GSMI)<br> elog_add_event_byte(ELOG_TYPE_EC_EVENT, EC_EVENT_LID_CLOSED);<br> #endif<br> /* Go to S5 */<br>@@ -74,7 +74,7 @@<br> else if (gpi_sts & (1 << EC_LID_GPI)) {<br> printk(BIOS_DEBUG, "LID CLOSED, SHUTDOWN\n");<br> <br>-#if CONFIG_ELOG_GSMI<br>+#if IS_ENABLED(CONFIG_ELOG_GSMI)<br> elog_add_event_byte(ELOG_TYPE_EC_EVENT, EC_EVENT_LID_CLOSED);<br> #endif<br> /* Go to S5 */<br>diff --git a/src/mainboard/google/rambi/mainboard.c b/src/mainboard/google/rambi/mainboard.c<br>index acd4ffe..b8dd805 100644<br>--- a/src/mainboard/google/rambi/mainboard.c<br>+++ b/src/mainboard/google/rambi/mainboard.c<br>@@ -21,7 +21,7 @@<br> #include <device/pci_def.h><br> #include <device/pci_ops.h><br> #include <console/console.h><br>-#if CONFIG_VGA_ROM_RUN<br>+#if IS_ENABLED(CONFIG_VGA_ROM_RUN)<br> #include <x86emu/x86emu.h><br> #endif<br> #include <pc80/mc146818rtc.h><br>@@ -40,7 +40,7 @@<br> {<br> }<br> <br>-#if CONFIG_VGA_ROM_RUN<br>+#if IS_ENABLED(CONFIG_VGA_ROM_RUN)<br> static int int15_handler(void)<br> {<br> int res = 1;<br>@@ -169,7 +169,7 @@<br> dev->ops->init = mainboard_init;<br> dev->ops->get_smbios_data = mainboard_smbios_data;<br> dev->ops->acpi_inject_dsdt_generator = chromeos_dsdt_generator;<br>-#if CONFIG_VGA_ROM_RUN<br>+#if IS_ENABLED(CONFIG_VGA_ROM_RUN)<br> /* Install custom int15 handler for VGA OPROM */<br> mainboard_interrupt_handlers(0x15, &int15_handler);<br> #endif<br>diff --git a/src/mainboard/google/rambi/mainboard_smi.c b/src/mainboard/google/rambi/mainboard_smi.c<br>index bd6f91e..113e7ce 100644<br>--- a/src/mainboard/google/rambi/mainboard_smi.c<br>+++ b/src/mainboard/google/rambi/mainboard_smi.c<br>@@ -34,7 +34,7 @@<br> uint16_t pmbase = get_pmbase();<br> uint32_t pm1_cnt;<br> <br>-#if CONFIG_ELOG_GSMI<br>+#if IS_ENABLED(CONFIG_ELOG_GSMI)<br> /* Log this event */<br> if (cmd)<br> elog_add_event_byte(ELOG_TYPE_EC_EVENT, cmd);<br>diff --git a/src/mainboard/google/slippy/acpi_tables.c b/src/mainboard/google/slippy/acpi_tables.c<br>index bf16858..4036f1b 100644<br>--- a/src/mainboard/google/slippy/acpi_tables.c<br>+++ b/src/mainboard/google/slippy/acpi_tables.c<br>@@ -55,7 +55,7 @@<br> gnvs->tpmp = 1;<br> <br> <br>-#if CONFIG_CHROMEOS<br>+#if IS_ENABLED(CONFIG_CHROMEOS)<br> gnvs->chromeos.vbt2 = google_ec_running_ro() ?<br> ACTIVE_ECFW_RO : ACTIVE_ECFW_RW;<br> #endif<br>diff --git a/src/mainboard/google/slippy/smihandler.c b/src/mainboard/google/slippy/smihandler.c<br>index 24f76f5..3480147 100644<br>--- a/src/mainboard/google/slippy/smihandler.c<br>+++ b/src/mainboard/google/slippy/smihandler.c<br>@@ -41,7 +41,7 @@<br> u8 cmd = google_chromeec_get_event();<br> u32 pm1_cnt;<br> <br>-#if CONFIG_ELOG_GSMI<br>+#if IS_ENABLED(CONFIG_ELOG_GSMI)<br> /* Log this event */<br> if (cmd)<br> elog_add_event_byte(ELOG_TYPE_EC_EVENT, cmd);<br>diff --git a/src/mainboard/google/storm/mainboard.c b/src/mainboard/google/storm/mainboard.c<br>index e3e7b68..3c1477d 100644<br>--- a/src/mainboard/google/storm/mainboard.c<br>+++ b/src/mainboard/google/storm/mainboard.c<br>@@ -31,7 +31,7 @@<br> <br> static void setup_usb(void)<br> {<br>-#if !CONFIG_BOARD_VARIANT_AP148<br>+#if !IS_ENABLED(CONFIG_BOARD_VARIANT_AP148)<br> gpio_tlmm_config_set(USB_ENABLE_GPIO, FUNC_SEL_GPIO,<br> GPIO_PULL_UP, GPIO_10MA, GPIO_ENABLE);<br> gpio_set(USB_ENABLE_GPIO, 1);<br>diff --git a/src/mainboard/google/stout/acpi_tables.c b/src/mainboard/google/stout/acpi_tables.c<br>index 7019c81..078cba2 100644<br>--- a/src/mainboard/google/stout/acpi_tables.c<br>+++ b/src/mainboard/google/stout/acpi_tables.c<br>@@ -53,7 +53,7 @@<br> gnvs->s5u1 = 0;<br> <br> <br>-#if CONFIG_CHROMEOS<br>+#if IS_ENABLED(CONFIG_CHROMEOS)<br> gnvs->chromeos.vbt2 = get_recovery_mode_switch() ?<br> ACTIVE_ECFW_RO : ACTIVE_ECFW_RW;<br> #endif<br>diff --git a/src/mainboard/google/stout/ec.c b/src/mainboard/google/stout/ec.c<br>index a7006d9..a459d0c 100644<br>--- a/src/mainboard/google/stout/ec.c<br>+++ b/src/mainboard/google/stout/ec.c<br>@@ -76,7 +76,7 @@<br> if (ec_reg & 0x8) {<br> printk(BIOS_ERR, " EC Fan Error\n");<br> critical_shutdown = 1;<br>-#if CONFIG_ELOG_GSMI<br>+#if IS_ENABLED(CONFIG_ELOG_GSMI)<br> elog_add_event_word(EC_EVENT_BATTERY_CRITICAL, EC_EVENT_FAN_ERROR);<br> #endif<br> }<br>@@ -86,7 +86,7 @@<br> if (ec_reg & 0x80) {<br> printk(BIOS_ERR, " EC Thermal Device Error\n");<br> critical_shutdown = 1;<br>-#if CONFIG_ELOG_GSMI<br>+#if IS_ENABLED(CONFIG_ELOG_GSMI)<br> elog_add_event_word(EC_EVENT_BATTERY_CRITICAL, EC_EVENT_THERMAL);<br> #endif<br> }<br>@@ -98,14 +98,14 @@<br> if ((ec_reg & 0xCF) == 0xC0) {<br> printk(BIOS_ERR, " EC Critical Battery Error\n");<br> critical_shutdown = 1;<br>-#if CONFIG_ELOG_GSMI<br>+#if IS_ENABLED(CONFIG_ELOG_GSMI)<br> elog_add_event_word(ELOG_TYPE_EC_EVENT, EC_EVENT_BATTERY_CRITICAL);<br> #endif<br> }<br> <br> if ((ec_reg & 0x8F) == 0x8F) {<br> printk(BIOS_ERR, " EC Read Battery Error\n");<br>-#if CONFIG_ELOG_GSMI<br>+#if IS_ENABLED(CONFIG_ELOG_GSMI)<br> elog_add_event_word(ELOG_TYPE_EC_EVENT, EC_EVENT_BATTERY);<br> #endif<br> }<br>diff --git a/src/mainboard/hp/dl145_g1/romstage.c b/src/mainboard/hp/dl145_g1/romstage.c<br>index 7c54a79..5c94548 100644<br>--- a/src/mainboard/hp/dl145_g1/romstage.c<br>+++ b/src/mainboard/hp/dl145_g1/romstage.c<br>@@ -88,7 +88,7 @@<br> #include "cpu/amd/dualcore/dualcore.c"<br> #include <spd.h><br> #include "cpu/amd/model_fxx/init_cpus.c"<br>-#if CONFIG_SET_FIDVID<br>+#if IS_ENABLED(CONFIG_SET_FIDVID)<br> #include "cpu/amd/model_fxx/fidvid.c"<br> #endif<br> <br>@@ -128,14 +128,14 @@<br> <br> setup_coherent_ht_domain();<br> wait_all_core0_started();<br>-#if CONFIG_LOGICAL_CPUS<br>+#if IS_ENABLED(CONFIG_LOGICAL_CPUS)<br> // It is said that we should start core1 after all core0 launched<br> start_other_cores();<br> wait_all_other_cores_started(bsp_apicid);<br> #endif<br> <br> ht_setup_chains_x(sysinfo);<br>-#if CONFIG_SET_FIDVID<br>+#if IS_ENABLED(CONFIG_SET_FIDVID)<br> /* Check to see if processor is capable of changing FIDVID */<br> /* otherwise it will throw a GP# when reading FIDVID_STATUS */<br> struct cpuid_result cpuid1 = cpuid(0x80000007);<br>@@ -191,7 +191,7 @@<br> fill_mem_ctrl(sysinfo->nodes, sysinfo->ctrl, spd_addr);<br> <br> memreset_setup();<br>-#if CONFIG_SET_FIDVID<br>+#if IS_ENABLED(CONFIG_SET_FIDVID)<br> init_timer(); // Need to use TMICT to synchronize FID/VID<br> #endif<br> sdram_initialize(sysinfo->nodes, sysinfo->ctrl, sysinfo);<br>diff --git a/src/mainboard/hp/dl145_g3/mptable.c b/src/mainboard/hp/dl145_g3/mptable.c<br>index 3a784e7..86affe8 100644<br>--- a/src/mainboard/hp/dl145_g3/mptable.c<br>+++ b/src/mainboard/hp/dl145_g3/mptable.c<br>@@ -29,7 +29,7 @@<br> #include <device/pci.h><br> #include <string.h><br> #include <stdint.h><br>-#if CONFIG_LOGICAL_CPUS<br>+#if IS_ENABLED(CONFIG_LOGICAL_CPUS)<br> #include <cpu/amd/multicore.h><br> #endif<br> #include <cpu/amd/amdk8_sysconf.h><br>diff --git a/src/mainboard/hp/dl145_g3/romstage.c b/src/mainboard/hp/dl145_g3/romstage.c<br>index 0dcc6e5..ef6890d 100644<br>--- a/src/mainboard/hp/dl145_g3/romstage.c<br>+++ b/src/mainboard/hp/dl145_g3/romstage.c<br>@@ -152,7 +152,7 @@<br> setup_coherent_ht_domain();<br> <br> wait_all_core0_started();<br>-#if CONFIG_LOGICAL_CPUS<br>+#if IS_ENABLED(CONFIG_LOGICAL_CPUS)<br> // It is said that we should start core1 after all core0 launched<br> /* becase optimize_link_coherent_ht is moved out from setup_coherent_ht_domain,<br> * So here need to make sure last core0 is started, esp for two way system,<br>@@ -166,7 +166,7 @@<br> ht_setup_chains_x(sysinfo); // it will init sblnk and sbbusn, nodes, sbdn<br> bcm5785_early_setup();<br> <br>-#if CONFIG_SET_FIDVID<br>+#if IS_ENABLED(CONFIG_SET_FIDVID)<br> {<br> msr_t msr;<br> msr = rdmsr(0xc0010042);<br>diff --git a/src/mainboard/hp/dl165_g6_fam10/mptable.c b/src/mainboard/hp/dl165_g6_fam10/mptable.c<br>index 17e42e4..b1c91c8 100644<br>--- a/src/mainboard/hp/dl165_g6_fam10/mptable.c<br>+++ b/src/mainboard/hp/dl165_g6_fam10/mptable.c<br>@@ -29,7 +29,7 @@<br> #include <device/pci.h><br> #include <string.h><br> #include <stdint.h><br>-#if CONFIG_LOGICAL_CPUS<br>+#if IS_ENABLED(CONFIG_LOGICAL_CPUS)<br> #include <cpu/amd/multicore.h><br> #endif<br> #include <cpu/amd/amdfam10_sysconf.h><br>diff --git a/src/mainboard/hp/dl165_g6_fam10/romstage.c b/src/mainboard/hp/dl165_g6_fam10/romstage.c<br>index d282e34..96619ed 100644<br>--- a/src/mainboard/hp/dl165_g6_fam10/romstage.c<br>+++ b/src/mainboard/hp/dl165_g6_fam10/romstage.c<br>@@ -152,7 +152,7 @@<br> <br> wait_all_core0_started();<br> <br>-#if CONFIG_LOGICAL_CPUS<br>+#if IS_ENABLED(CONFIG_LOGICAL_CPUS)<br> /* Core0 on each node is configured. Now setup any additional cores. */<br> printk(BIOS_DEBUG, "start_other_cores()\n");<br> start_other_cores(bsp_apicid);<br>@@ -160,7 +160,7 @@<br> wait_all_other_cores_started(bsp_apicid);<br> #endif<br> <br>-#if CONFIG_SET_FIDVID<br>+#if IS_ENABLED(CONFIG_SET_FIDVID)<br> msr = rdmsr(0xc0010071);<br> printk(BIOS_DEBUG, "\nBegin FIDVID MSR 0xc0010071 0x%08x 0x%08x\n", msr.hi, msr.lo);<br> <br>diff --git a/src/mainboard/hp/pavilion_m6_1035dx/buildOpts.c b/src/mainboard/hp/pavilion_m6_1035dx/buildOpts.c<br>index 48258ca..709c81f 100644<br>--- a/src/mainboard/hp/pavilion_m6_1035dx/buildOpts.c<br>+++ b/src/mainboard/hp/pavilion_m6_1035dx/buildOpts.c<br>@@ -169,7 +169,7 @@<br> #define BLDCFG_LVDS_POWER_ON_SEQ_VARY_BL_TO_BLON 3<br> #define BLDCFG_LVDS_POWER_ON_SEQ_BLON_TO_VARY_BL 3<br> <br>-#if CONFIG_GFXUMA<br>+#if IS_ENABLED(CONFIG_GFXUMA)<br> #define BLDCFG_UMA_ALIGNMENT UMA_4MB_ALIGNED<br> #define BLDCFG_UMA_ALLOCATION_MODE UMA_SPECIFIED<br> //#define BLDCFG_UMA_ALLOCATION_SIZE 0x1000//0x1800//0x1000 /* (1000 << 16) = 256M*/<br>diff --git a/src/mainboard/iei/kino-780am2-fam10/romstage.c b/src/mainboard/iei/kino-780am2-fam10/romstage.c<br>index 1731ef4..7417c1a 100644<br>--- a/src/mainboard/iei/kino-780am2-fam10/romstage.c<br>+++ b/src/mainboard/iei/kino-780am2-fam10/romstage.c<br>@@ -139,7 +139,7 @@<br> */<br> wait_all_core0_started();<br> <br>- #if CONFIG_LOGICAL_CPUS<br>+ #if IS_ENABLED(CONFIG_LOGICAL_CPUS)<br> /* Core0 on each node is configured. Now setup any additional cores. */<br> printk(BIOS_DEBUG, "start_other_cores()\n");<br> start_other_cores(bsp_apicid);<br>@@ -153,7 +153,7 @@<br> rs780_early_setup();<br> sb7xx_51xx_early_setup();<br> <br>- #if CONFIG_SET_FIDVID<br>+ #if IS_ENABLED(CONFIG_SET_FIDVID)<br> msr = rdmsr(0xc0010071);<br> printk(BIOS_DEBUG, "\nBegin FIDVID MSR 0xc0010071 0x%08x 0x%08x\n", msr.hi, msr.lo);<br> <br>diff --git a/src/mainboard/intel/baskingridge/acpi_tables.c b/src/mainboard/intel/baskingridge/acpi_tables.c<br>index a532ab0..e3a52fa 100644<br>--- a/src/mainboard/intel/baskingridge/acpi_tables.c<br>+++ b/src/mainboard/intel/baskingridge/acpi_tables.c<br>@@ -74,7 +74,7 @@<br> gnvs->tpmp = 1;<br> <br> <br>-#if CONFIG_CHROMEOS<br>+#if IS_ENABLED(CONFIG_CHROMEOS)<br> /* Emerald Lake has no EC (?) */<br> gnvs->chromeos.vbt2 = ACTIVE_ECFW_RO;<br> #endif<br>diff --git a/src/mainboard/intel/bayleybay_fsp/mainboard.c b/src/mainboard/intel/bayleybay_fsp/mainboard.c<br>index 67bee39..ea57c93 100644<br>--- a/src/mainboard/intel/bayleybay_fsp/mainboard.c<br>+++ b/src/mainboard/intel/bayleybay_fsp/mainboard.c<br>@@ -21,7 +21,7 @@<br> #include <device/pci_def.h><br> #include <device/pci_ops.h><br> #include <console/console.h><br>-#if CONFIG_VGA_ROM_RUN<br>+#if IS_ENABLED(CONFIG_VGA_ROM_RUN)<br> #include <x86emu/x86emu.h><br> #endif<br> #include <pc80/mc146818rtc.h><br>diff --git a/src/mainboard/intel/camelbackmountain_fsp/mainboard.c b/src/mainboard/intel/camelbackmountain_fsp/mainboard.c<br>index 58da036..393fad8 100644<br>--- a/src/mainboard/intel/camelbackmountain_fsp/mainboard.c<br>+++ b/src/mainboard/intel/camelbackmountain_fsp/mainboard.c<br>@@ -21,7 +21,7 @@<br> #include <device/pci_def.h><br> #include <device/pci_ops.h><br> #include <console/console.h><br>-#if CONFIG_VGA_ROM_RUN<br>+#if IS_ENABLED(CONFIG_VGA_ROM_RUN)<br> #include <x86emu/x86emu.h><br> #endif<br> #include <pc80/mc146818rtc.h><br>diff --git a/src/mainboard/intel/cougar_canyon2/romstage.c b/src/mainboard/intel/cougar_canyon2/romstage.c<br>index bf5b738..96c22ea 100644<br>--- a/src/mainboard/intel/cougar_canyon2/romstage.c<br>+++ b/src/mainboard/intel/cougar_canyon2/romstage.c<br>@@ -213,7 +213,7 @@<br> pm1_cnt = inl(DEFAULT_PMBASE + PM1_CNT);<br> post_code(0x46);<br> if ((pm1_sts & WAK_STS) && ((pm1_cnt >> 10) & 7) == 5) {<br>-#if CONFIG_HAVE_ACPI_RESUME<br>+#if IS_ENABLED(CONFIG_HAVE_ACPI_RESUME)<br> printk(BIOS_DEBUG, "Resume from S3 detected.\n");<br> boot_mode = 2;<br> /* Clear SLP_TYPE. This will break stage2 but<br>@@ -261,7 +261,7 @@<br> <br> post_code(0x49);<br> <br>-#if CONFIG_USBDEBUG<br>+#if IS_ENABLED(CONFIG_USBDEBUG)<br> /* FSP reconfigures USB, so reinit it to have debug */<br> early_usbdebug_init();<br> #endif<br>diff --git a/src/mainboard/intel/eagleheights/fadt.c b/src/mainboard/intel/eagleheights/fadt.c<br>index 7d0e8a3..eaea7f7 100644<br>--- a/src/mainboard/intel/eagleheights/fadt.c<br>+++ b/src/mainboard/intel/eagleheights/fadt.c<br>@@ -62,7 +62,7 @@<br> fadt->dsdt = (unsigned long) dsdt;<br> fadt->preferred_pm_profile = 7; /* Performance Server */<br> fadt->sci_int = 0x9;<br>-#if CONFIG_HAVE_SMI_HANDLER<br>+#if IS_ENABLED(CONFIG_HAVE_SMI_HANDLER)<br> fadt->smi_cmd = APM_CNT;<br> #else<br> fadt->smi_cmd = 0x00;<br>diff --git a/src/mainboard/iwill/dk8_htx/mptable.c b/src/mainboard/iwill/dk8_htx/mptable.c<br>index b1fcdd1..74770d4 100644<br>--- a/src/mainboard/iwill/dk8_htx/mptable.c<br>+++ b/src/mainboard/iwill/dk8_htx/mptable.c<br>@@ -4,7 +4,7 @@<br> #include <device/pci.h><br> #include <string.h><br> #include <stdint.h><br>-#if CONFIG_LOGICAL_CPUS<br>+#if IS_ENABLED(CONFIG_LOGICAL_CPUS)<br> #include <cpu/amd/multicore.h><br> #endif<br> #include <cpu/amd/amdk8_sysconf.h><br>diff --git a/src/mainboard/iwill/dk8_htx/romstage.c b/src/mainboard/iwill/dk8_htx/romstage.c<br>index 9d29ae2..47d2619 100644<br>--- a/src/mainboard/iwill/dk8_htx/romstage.c<br>+++ b/src/mainboard/iwill/dk8_htx/romstage.c<br>@@ -99,7 +99,7 @@<br> setup_coherent_ht_domain(); // routing table and start other core0<br> <br> wait_all_core0_started();<br>-#if CONFIG_LOGICAL_CPUS<br>+#if IS_ENABLED(CONFIG_LOGICAL_CPUS)<br> // It is said that we should start core1 after all core0 launched<br> /* becase optimize_link_coherent_ht is moved out from setup_coherent_ht_domain,<br> * So here need to make sure last core0 is started, esp for two way system,<br>@@ -112,7 +112,7 @@<br> /* it will set up chains and store link pair for optimization later */<br> ht_setup_chains_x(sysinfo); // it will init sblnk and sbbusn, nodes, sbdn<br> <br>-#if CONFIG_SET_FIDVID<br>+#if IS_ENABLED(CONFIG_SET_FIDVID)<br> {<br> msr_t msr;<br> msr = rdmsr(0xc0010042);<br>diff --git a/src/mainboard/jetway/pa78vm5/romstage.c b/src/mainboard/jetway/pa78vm5/romstage.c<br>index f540a73..23f2892 100644<br>--- a/src/mainboard/jetway/pa78vm5/romstage.c<br>+++ b/src/mainboard/jetway/pa78vm5/romstage.c<br>@@ -144,7 +144,7 @@<br> */<br> wait_all_core0_started();<br> <br>- #if CONFIG_LOGICAL_CPUS<br>+ #if IS_ENABLED(CONFIG_LOGICAL_CPUS)<br> /* Core0 on each node is configured. Now setup any additional cores. */<br> printk(BIOS_DEBUG, "start_other_cores()\n");<br> start_other_cores(bsp_apicid);<br>@@ -158,7 +158,7 @@<br> rs780_early_setup();<br> sb7xx_51xx_early_setup();<br> <br>-#if CONFIG_SET_FIDVID<br>+#if IS_ENABLED(CONFIG_SET_FIDVID)<br> msr = rdmsr(0xc0010071);<br> printk(BIOS_DEBUG, "\nBegin FIDVID MSR 0xc0010071 0x%08x 0x%08x\n", msr.hi, msr.lo);<br> <br>diff --git a/src/mainboard/kontron/kt690/romstage.c b/src/mainboard/kontron/kt690/romstage.c<br>index 7769647..8470ae1 100644<br>--- a/src/mainboard/kontron/kt690/romstage.c<br>+++ b/src/mainboard/kontron/kt690/romstage.c<br>@@ -91,7 +91,7 @@<br> <br> setup_coherent_ht_domain();<br> <br>-#if CONFIG_LOGICAL_CPUS<br>+#if IS_ENABLED(CONFIG_LOGICAL_CPUS)<br> /* It is said that we should start core1 after all core0 launched */<br> wait_all_core0_started();<br> start_other_cores();<br>diff --git a/src/mainboard/kontron/ktqm77/mainboard.c b/src/mainboard/kontron/ktqm77/mainboard.c<br>index b82102a..5a697f0 100644<br>--- a/src/mainboard/kontron/ktqm77/mainboard.c<br>+++ b/src/mainboard/kontron/ktqm77/mainboard.c<br>@@ -21,7 +21,7 @@<br> #include <device/pci_def.h><br> #include <device/pci_ops.h><br> #include <console/console.h><br>-#if CONFIG_VGA_ROM_RUN<br>+#if IS_ENABLED(CONFIG_VGA_ROM_RUN)<br> #include <x86emu/x86emu.h><br> #endif<br> #include <pc80/mc146818rtc.h><br>@@ -31,7 +31,7 @@<br> #include <boot/coreboot_tables.h><br> #include <southbridge/intel/bd82x6x/pch.h><br> <br>-#if CONFIG_VGA_ROM_RUN<br>+#if IS_ENABLED(CONFIG_VGA_ROM_RUN)<br> static int int15_handler(void)<br> {<br> int res = 0;<br>@@ -164,7 +164,8 @@<br> <br> static void mainboard_enable(device_t dev)<br> {<br>-#if CONFIG_PCI_OPTION_ROM_RUN_YABEL || CONFIG_PCI_OPTION_ROM_RUN_REALMODE<br>+#if IS_ENABLED(CONFIG_PCI_OPTION_ROM_RUN_YABEL) || \<br>+ IS_ENABLED(CONFIG_PCI_OPTION_ROM_RUN_REALMODE)<br> /* Install custom int15 handler for VGA OPROM */<br> mainboard_interrupt_handlers(0x15, &int15_handler);<br> #endif<br>diff --git a/src/mainboard/lenovo/g505s/buildOpts.c b/src/mainboard/lenovo/g505s/buildOpts.c<br>index eda1a4d..80b91ba 100644<br>--- a/src/mainboard/lenovo/g505s/buildOpts.c<br>+++ b/src/mainboard/lenovo/g505s/buildOpts.c<br>@@ -169,7 +169,7 @@<br> #define BLDCFG_LVDS_POWER_ON_SEQ_VARY_BL_TO_BLON 3<br> #define BLDCFG_LVDS_POWER_ON_SEQ_BLON_TO_VARY_BL 3<br> <br>-#if CONFIG_GFXUMA<br>+#if IS_ENABLED(CONFIG_GFXUMA)<br> #define BLDCFG_UMA_ALIGNMENT UMA_4MB_ALIGNED<br> #define BLDCFG_UMA_ALLOCATION_MODE UMA_SPECIFIED<br> //#define BLDCFG_UMA_ALLOCATION_SIZE 0x1000//0x1800//0x1000 /* (1000 << 16) = 256M*/<br>diff --git a/src/mainboard/lenovo/t400/romstage.c b/src/mainboard/lenovo/t400/romstage.c<br>index 1a5c17c..2d35650 100644<br>--- a/src/mainboard/lenovo/t400/romstage.c<br>+++ b/src/mainboard/lenovo/t400/romstage.c<br>@@ -94,7 +94,7 @@<br> /* Check for S3 resume. */<br> const u32 pm1_cnt = inl(DEFAULT_PMBASE + 0x04);<br> if (((pm1_cnt >> 10) & 7) == 5) {<br>-#if CONFIG_HAVE_ACPI_RESUME<br>+#if IS_ENABLED(CONFIG_HAVE_ACPI_RESUME)<br> printk(BIOS_DEBUG, "Resume from S3 detected.\n");<br> s3resume = 1;<br> /* Clear SLP_TYPE. This will break stage2 but<br>diff --git a/src/mainboard/lenovo/x200/romstage.c b/src/mainboard/lenovo/x200/romstage.c<br>index 02f7116..e3f4686 100644<br>--- a/src/mainboard/lenovo/x200/romstage.c<br>+++ b/src/mainboard/lenovo/x200/romstage.c<br>@@ -89,7 +89,7 @@<br> /* Check for S3 resume. */<br> const u32 pm1_cnt = inl(DEFAULT_PMBASE + 0x04);<br> if (((pm1_cnt >> 10) & 7) == 5) {<br>-#if CONFIG_HAVE_ACPI_RESUME<br>+#if IS_ENABLED(CONFIG_HAVE_ACPI_RESUME)<br> printk(BIOS_DEBUG, "Resume from S3 detected.\n");<br> s3resume = 1;<br> /* Clear SLP_TYPE. This will break stage2 but<br>diff --git a/src/mainboard/lenovo/x201/romstage.c b/src/mainboard/lenovo/x201/romstage.c<br>index 7634de8..e8312d7 100644<br>--- a/src/mainboard/lenovo/x201/romstage.c<br>+++ b/src/mainboard/lenovo/x201/romstage.c<br>@@ -286,7 +286,7 @@<br> else<br> quick_ram_check();<br> <br>-#if CONFIG_LPC_TPM<br>+#if IS_ENABLED(CONFIG_LPC_TPM)<br> init_tpm(s3resume);<br> #endif<br> }<br>diff --git a/src/mainboard/lippert/frontrunner/romstage.c b/src/mainboard/lippert/frontrunner/romstage.c<br>index d44cbf3..e7fcbda 100644<br>--- a/src/mainboard/lippert/frontrunner/romstage.c<br>+++ b/src/mainboard/lippert/frontrunner/romstage.c<br>@@ -50,7 +50,7 @@<br> if (device != DIMM0)<br> return 0xFF; /* No DIMM1, don't even try. */<br> <br>-#if CONFIG_DEBUG_SMBUS<br>+#if IS_ENABLED(CONFIG_DEBUG_SMBUS)<br> if (address >= sizeof(spdbytes) || spdbytes[address] == 0xFF) {<br> printk(BIOS_ERR, "ERROR: spd_read_byte(DIMM0, 0x%02x) "<br> "returns 0xff\n", address);<br>diff --git a/src/mainboard/lippert/hurricane-lx/mainboard.c b/src/mainboard/lippert/hurricane-lx/mainboard.c<br>index 3d32113..0f210cb 100644<br>--- a/src/mainboard/lippert/hurricane-lx/mainboard.c<br>+++ b/src/mainboard/lippert/hurricane-lx/mainboard.c<br>@@ -25,7 +25,7 @@<br> #include <device/pci_ids.h><br> <br> /* Bit1 switches Com1 to RS485, bit2 same for Com2. */<br>-#if CONFIG_ONBOARD_UARTS_RS485<br>+#if IS_ENABLED(CONFIG_ONBOARD_UARTS_RS485)<br> #define SIO_GP1X_CONFIG 0x06<br> #else<br> #define SIO_GP1X_CONFIG 0x00<br>@@ -54,7 +54,7 @@<br> outl(0x00000040, gpio_base + 0x04); // GPIO6 output 1 - LAN_PD#<br> outl(0x00000400, gpio_base + 0x34); // GPIO10 in aux1 1 - THRM_ALRM#<br> outl(0x00000400, gpio_base + 0x20); // GPIO10 input 1 - THRM_ALRM#<br>-#if !CONFIG_BOARD_OLD_REVISION<br>+#if !IS_ENABLED(CONFIG_BOARD_OLD_REVISION)<br> outl(0x00000800, gpio_base + 0x94); // GPIO27 out aux2 1 - 32kHz<br> outl(0x00000800, gpio_base + 0x84); // GPIO27 output 1 - 32kHz<br> #endif<br>diff --git a/src/mainboard/lippert/hurricane-lx/romstage.c b/src/mainboard/lippert/hurricane-lx/romstage.c<br>index b76960f..9d7b565 100644<br>--- a/src/mainboard/lippert/hurricane-lx/romstage.c<br>+++ b/src/mainboard/lippert/hurricane-lx/romstage.c<br>@@ -48,7 +48,7 @@<br> return smbus_read_byte(device, address);<br> }<br> <br>-#if !CONFIG_BOARD_OLD_REVISION<br>+#if !IS_ENABLED(CONFIG_BOARD_OLD_REVISION)<br> /* Send config data to System Management Controller via SMB. */<br> static int smc_send_config(unsigned char config_data)<br> {<br>@@ -79,7 +79,7 @@<br> 0x042C, // disable ATXPG; VIN6 enabled, FAN4/5 disabled, VIN7,VIN3 enabled<br> 0x1423, // don't delay PoWeROK1/2<br> 0x9072, // watchdog triggers PWROK, counts seconds<br>-#if !CONFIG_USE_WATCHDOG_ON_BOOT<br>+#if !IS_ENABLED(CONFIG_USE_WATCHDOG_ON_BOOT)<br> 0x0073, 0x0074, // disarm watchdog by changing 56 s timeout to 0<br> #endif<br> 0xBF25, 0x172A, 0xF326, // select GPIO function for most pins<br>@@ -88,7 +88,7 @@<br> 0x07C0, // enable Simple-I/O for GP12-10= RS485_EN2,1, WD_ACTIVE<br> 0x06C8, // config GP12,11 as output, GP10 as input<br> 0x2DF5, // map Hw Monitor Thermal Output to GP55<br>-#if CONFIG_BOARD_OLD_REVISION<br>+#if IS_ENABLED(CONFIG_BOARD_OLD_REVISION)<br> 0x1F2A, 0xC072, // switch GP13 to GPIO, WDT output from PWROK to KRST<br> #endif<br> };<br>@@ -132,7 +132,7 @@<br> <br> cpuRegInit(0, DIMM0, DIMM1, DRAM_TERMINATED);<br> <br>-#if !CONFIG_BOARD_OLD_REVISION<br>+#if !IS_ENABLED(CONFIG_BOARD_OLD_REVISION)<br> int err;<br> /* bit0 = Spread Spectrum */<br> if ((err = smc_send_config(SMC_CONFIG))) {<br>diff --git a/src/mainboard/lippert/literunner-lx/mainboard.c b/src/mainboard/lippert/literunner-lx/mainboard.c<br>index e4084b5..11f9e14 100644<br>--- a/src/mainboard/lippert/literunner-lx/mainboard.c<br>+++ b/src/mainboard/lippert/literunner-lx/mainboard.c<br>@@ -25,7 +25,7 @@<br> #include <device/pci_ids.h><br> <br> /* Bit0 turns off the Live LED, bit1 switches Com1 to RS485, bit2 same for Com2. */<br>-#if CONFIG_ONBOARD_UARTS_RS485<br>+#if IS_ENABLED(CONFIG_ONBOARD_UARTS_RS485)<br> #define SIO_GP1X_CONFIG 0x07<br> #else<br> #define SIO_GP1X_CONFIG 0x01<br>diff --git a/src/mainboard/lippert/literunner-lx/romstage.c b/src/mainboard/lippert/literunner-lx/romstage.c<br>index e83924c..1474ecd 100644<br>--- a/src/mainboard/lippert/literunner-lx/romstage.c<br>+++ b/src/mainboard/lippert/literunner-lx/romstage.c<br>@@ -38,7 +38,7 @@<br> #define GPIO_DEV PNP_DEV(0x2e, IT8712F_GPIO)<br> <br> /* Bit0 enables Spread Spectrum, bit1 makes on-board CF slot act as IDE slave. */<br>-#if CONFIG_ONBOARD_IDE_SLAVE<br>+#if IS_ENABLED(CONFIG_ONBOARD_IDE_SLAVE)<br> #define SMC_CONFIG 0x03<br> #else<br> #define SMC_CONFIG 0x01<br>@@ -79,7 +79,7 @@<br> if (device != DIMM0)<br> return 0xFF; /* No DIMM1, don't even try. */<br> <br>-#if CONFIG_DEBUG_SMBUS<br>+#if IS_ENABLED(CONFIG_DEBUG_SMBUS)<br> if (address >= sizeof(spdbytes) || spdbytes[address] == 0xFF)<br> printk(BIOS_ERR, "ERROR: spd_read_byte(DIMM0, 0x%02x) "<br> "returns 0xff\n", address);<br>@@ -118,7 +118,7 @@<br> 0x072C, // VIN6 enabled, FAN4/5 disabled, VIN7,VIN3 internal<br> 0x1423, // don't delay PoWeROK1/2<br> 0x9072, // watchdog triggers PWROK, counts seconds<br>-#if !CONFIG_USE_WATCHDOG_ON_BOOT<br>+#if !IS_ENABLED(CONFIG_USE_WATCHDOG_ON_BOOT)<br> 0x0073, 0x0074, // disarm watchdog by changing 56 s timeout to 0<br> #endif<br> 0xBF25, 0x172A, 0xF326, // select GPIO function for most pins<br>diff --git a/src/mainboard/lippert/roadrunner-lx/mainboard.c b/src/mainboard/lippert/roadrunner-lx/mainboard.c<br>index 1d35ebe..b922e78 100644<br>--- a/src/mainboard/lippert/roadrunner-lx/mainboard.c<br>+++ b/src/mainboard/lippert/roadrunner-lx/mainboard.c<br>@@ -25,7 +25,7 @@<br> #include <device/pci_ids.h><br> <br> /* Bit1 switches Com1 to RS485, bit2 same for Com2, bit5 turns off the Live LED. */<br>-#if CONFIG_ONBOARD_UARTS_RS485<br>+#if IS_ENABLED(CONFIG_ONBOARD_UARTS_RS485)<br> #define SIO_GP1X_CONFIG 0x26<br> #else<br> #define SIO_GP1X_CONFIG 0x20<br>diff --git a/src/mainboard/lippert/roadrunner-lx/romstage.c b/src/mainboard/lippert/roadrunner-lx/romstage.c<br>index 6ba90d7..8341178 100644<br>--- a/src/mainboard/lippert/roadrunner-lx/romstage.c<br>+++ b/src/mainboard/lippert/roadrunner-lx/romstage.c<br>@@ -55,7 +55,7 @@<br> 0x1E2C, // disable ATXPG; VIN6,FAN4/5,VIN3 enabled, VIN7 internal<br> 0x1423, // don't delay PoWeROK1/2 - triggers 2nd reset<br> 0x9072, // watchdog triggers PWROK, counts seconds<br>-#if !CONFIG_USE_WATCHDOG_ON_BOOT<br>+#if !IS_ENABLED(CONFIG_USE_WATCHDOG_ON_BOOT)<br> 0x0073, 0x0074, // disarm watchdog by changing 56 s timeout to 0<br> #endif<br> 0xBF25, 0x372A, 0xF326, // select GPIO function for most pins<br>diff --git a/src/mainboard/lippert/spacerunner-lx/mainboard.c b/src/mainboard/lippert/spacerunner-lx/mainboard.c<br>index b0bc74e..594545d 100644<br>--- a/src/mainboard/lippert/spacerunner-lx/mainboard.c<br>+++ b/src/mainboard/lippert/spacerunner-lx/mainboard.c<br>@@ -25,7 +25,7 @@<br> #include <device/pci_ids.h><br> <br> /* Bit0 turns off the Live LED, bit1 switches Com1 to RS485, bit2 same for Com2. */<br>-#if CONFIG_ONBOARD_UARTS_RS485<br>+#if IS_ENABLED(CONFIG_ONBOARD_UARTS_RS485)<br> #define SIO_GP1X_CONFIG 0x07<br> #else<br> #define SIO_GP1X_CONFIG 0x01<br>diff --git a/src/mainboard/lippert/spacerunner-lx/romstage.c b/src/mainboard/lippert/spacerunner-lx/romstage.c<br>index c77d82f..a73276e 100644<br>--- a/src/mainboard/lippert/spacerunner-lx/romstage.c<br>+++ b/src/mainboard/lippert/spacerunner-lx/romstage.c<br>@@ -38,7 +38,7 @@<br> #define GPIO_DEV PNP_DEV(0x2e, IT8712F_GPIO)<br> <br> /* Bit0 enables Spread Spectrum, bit1 makes on-board SSD act as IDE slave. */<br>-#if CONFIG_ONBOARD_IDE_SLAVE<br>+#if IS_ENABLED(CONFIG_ONBOARD_IDE_SLAVE)<br> #define SMC_CONFIG 0x03<br> #else<br> #define SMC_CONFIG 0x01<br>@@ -79,7 +79,7 @@<br> if (device != DIMM0)<br> return 0xFF; /* No DIMM1, don't even try. */<br> <br>-#if CONFIG_DEBUG_SMBUS<br>+#if IS_ENABLED(CONFIG_DEBUG_SMBUS)<br> if (address >= sizeof(spdbytes) || spdbytes[address] == 0xFF) {<br> printk(BIOS_ERR, "ERROR: spd_read_byte(DIMM0, 0x%02x) "<br> "returns 0xff\n", address);<br>@@ -119,7 +119,7 @@<br> 0x072C, // VIN6 enabled, FAN4/5 disabled, VIN7,VIN3 internal<br> 0x1423, // don't delay PoWeROK1/2<br> 0x9072, // watchdog triggers PWROK, counts seconds<br>-#if !CONFIG_USE_WATCHDOG_ON_BOOT<br>+#if !IS_ENABLED(CONFIG_USE_WATCHDOG_ON_BOOT)<br> 0x0073, 0x0074, // disarm watchdog by changing 56 s timeout to 0<br> #endif<br> 0xBF25, 0x172A, 0xF326, // select GPIO function for most pins<br></pre><p>To view, visit <a href="https://review.coreboot.org/20343">change 20343</a>. To unsubscribe, visit <a href="https://review.coreboot.org/settings">settings</a>.</p><div itemscope itemtype="http://schema.org/EmailMessage"><div itemscope itemprop="action" itemtype="http://schema.org/ViewAction"><link itemprop="url" href="https://review.coreboot.org/20343"/><meta itemprop="name" content="View Change"/></div></div>
<div style="display:none"> Gerrit-Project: coreboot </div>
<div style="display:none"> Gerrit-Branch: master </div>
<div style="display:none"> Gerrit-MessageType: newchange </div>
<div style="display:none"> Gerrit-Change-Id: I1f906c8c465108017bc4d08534653233078ef32d </div>
<div style="display:none"> Gerrit-Change-Number: 20343 </div>
<div style="display:none"> Gerrit-PatchSet: 1 </div>
<div style="display:none"> Gerrit-Owner: Martin Roth <martinroth@google.com> </div>