<p>Martin Roth has uploaded this change for <strong>review</strong>.</p><p><a href="https://review.coreboot.org/20344">View Change</a></p><pre style="font-family: monospace,monospace; white-space: pre-wrap;">mainboard/[m-w]: add IS_ENABLED() around Kconfig symbol references<br><br>Change-Id: Ifba3257b0328d0b6ad1bee9bf885683998df5851<br>Signed-off-by: Martin Roth <martinroth@google.com><br>---<br>M src/mainboard/msi/ms7135/romstage.c<br>M src/mainboard/msi/ms7260/romstage.c<br>M src/mainboard/msi/ms7721/buildOpts.c<br>M src/mainboard/msi/ms9185/mptable.c<br>M src/mainboard/msi/ms9185/romstage.c<br>M src/mainboard/msi/ms9282/romstage.c<br>M src/mainboard/msi/ms9652_fam10/romstage.c<br>M src/mainboard/nvidia/l1_2pvv/romstage.c<br>M src/mainboard/samsung/lumpy/acpi_tables.c<br>M src/mainboard/samsung/lumpy/romstage.c<br>M src/mainboard/samsung/stumpy/romstage.c<br>M src/mainboard/siemens/mc_bdx1/mainboard.c<br>M src/mainboard/siemens/mc_tcu3/mainboard.c<br>M src/mainboard/siemens/sitemp_g1p1/acpi_tables.c<br>M src/mainboard/siemens/sitemp_g1p1/mainboard.c<br>M src/mainboard/siemens/sitemp_g1p1/romstage.c<br>M src/mainboard/sunw/ultra40/romstage.c<br>M src/mainboard/sunw/ultra40m2/romstage.c<br>M src/mainboard/supermicro/h8dme/romstage.c<br>M src/mainboard/supermicro/h8dmr/romstage.c<br>M src/mainboard/supermicro/h8dmr_fam10/romstage.c<br>M src/mainboard/supermicro/h8qgi/buildOpts.c<br>M src/mainboard/supermicro/h8qgi/rd890_cfg.h<br>M src/mainboard/supermicro/h8qgi/sb700_cfg.h<br>M src/mainboard/supermicro/h8qme_fam10/romstage.c<br>M src/mainboard/supermicro/h8scm/rd890_cfg.h<br>M src/mainboard/supermicro/h8scm/sb700_cfg.h<br>M src/mainboard/supermicro/h8scm_fam10/romstage.c<br>M src/mainboard/technexion/tim5690/mainboard.c<br>M src/mainboard/technexion/tim5690/romstage.c<br>M src/mainboard/technexion/tim8690/romstage.c<br>M src/mainboard/thomson/ip1000/spd_table.h<br>M src/mainboard/tyan/s2912/romstage.c<br>M src/mainboard/tyan/s2912_fam10/romstage.c<br>M src/mainboard/tyan/s8226/buildOpts.c<br>M src/mainboard/tyan/s8226/rd890_cfg.h<br>M src/mainboard/tyan/s8226/sb700_cfg.h<br>M src/mainboard/via/epia-m850/mainboard.c<br>M src/mainboard/via/epia-m850/romstage.c<br>M src/mainboard/winent/mb6047/romstage.c<br>40 files changed, 81 insertions(+), 81 deletions(-)<br><br></pre><pre style="font-family: monospace,monospace; white-space: pre-wrap;">git pull ssh://review.coreboot.org:29418/coreboot refs/changes/44/20344/1</pre><pre style="font-family: monospace,monospace; white-space: pre-wrap;">diff --git a/src/mainboard/msi/ms7135/romstage.c b/src/mainboard/msi/ms7135/romstage.c<br>index 08fbdc7..c595006 100644<br>--- a/src/mainboard/msi/ms7135/romstage.c<br>+++ b/src/mainboard/msi/ms7135/romstage.c<br>@@ -41,7 +41,7 @@<br> #include <spd.h><br> #include <northbridge/amd/amdk8/pre_f.h><br> <br>-#if CONFIG_HAVE_OPTION_TABLE<br>+#if IS_ENABLED(CONFIG_HAVE_OPTION_TABLE)<br> #include "option_table.h"<br> #endif<br> <br>@@ -132,7 +132,7 @@<br> needs_reset = setup_coherent_ht_domain();<br> <br> wait_all_core0_started();<br>-#if CONFIG_LOGICAL_CPUS<br>+#if IS_ENABLED(CONFIG_LOGICAL_CPUS)<br> // It is said that we should start core1 after all core0 launched<br> start_other_cores();<br> wait_all_other_cores_started(bsp_apicid);<br>@@ -156,7 +156,7 @@<br> ms7135_set_nf4_voltage();<br> ms7135_set_ram_voltage();<br> <br>-#if CONFIG_DEBUG_SMBUS<br>+#if IS_ENABLED(CONFIG_DEBUG_SMBUS)<br> dump_spd_registers(&ctrl[0]);<br> dump_smbus_registers();<br> #endif<br>diff --git a/src/mainboard/msi/ms7260/romstage.c b/src/mainboard/msi/ms7260/romstage.c<br>index 6feddcf..5287258a 100644<br>--- a/src/mainboard/msi/ms7260/romstage.c<br>+++ b/src/mainboard/msi/ms7260/romstage.c<br>@@ -144,7 +144,7 @@<br> setup_coherent_ht_domain(); /* Routing table and start other core0. */<br> wait_all_core0_started();<br> <br>-#if CONFIG_LOGICAL_CPUS<br>+#if IS_ENABLED(CONFIG_LOGICAL_CPUS)<br> /* It is said that we should start core1 after all core0 launched<br> * becase optimize_link_coherent_ht is moved out from<br> * setup_coherent_ht_domain, so here need to make sure last core0 is<br>@@ -158,7 +158,7 @@<br> /* Set up chains and store link pair for optimization later. */<br> ht_setup_chains_x(sysinfo); /* Init sblnk and sbbusn, nodes, sbdn. */<br> <br>-#if CONFIG_SET_FIDVID<br>+#if IS_ENABLED(CONFIG_SET_FIDVID)<br> {<br> msr_t msr = rdmsr(0xc0010042);<br> printk(BIOS_DEBUG, "begin msr fid, vid %08x%08x\n", msr.hi, msr.lo);<br>diff --git a/src/mainboard/msi/ms7721/buildOpts.c b/src/mainboard/msi/ms7721/buildOpts.c<br>index ecb168c..5191574 100644<br>--- a/src/mainboard/msi/ms7721/buildOpts.c<br>+++ b/src/mainboard/msi/ms7721/buildOpts.c<br>@@ -168,7 +168,7 @@<br> #define BLDCFG_LVDS_POWER_ON_SEQ_VARY_BL_TO_BLON 3<br> #define BLDCFG_LVDS_POWER_ON_SEQ_BLON_TO_VARY_BL 3<br> <br>-#if CONFIG_GFXUMA<br>+#if IS_ENABLED(CONFIG_GFXUMA)<br> #define BLDCFG_UMA_ALIGNMENT UMA_4MB_ALIGNED<br> #define BLDCFG_UMA_ALLOCATION_MODE UMA_SPECIFIED<br> //#define BLDCFG_UMA_ALLOCATION_SIZE 0x1000//0x1800//0x1000 /* (1000 << 16) = 256M*/<br>diff --git a/src/mainboard/msi/ms9185/mptable.c b/src/mainboard/msi/ms9185/mptable.c<br>index 38cc72b..e93602b 100644<br>--- a/src/mainboard/msi/ms9185/mptable.c<br>+++ b/src/mainboard/msi/ms9185/mptable.c<br>@@ -26,7 +26,7 @@<br> #include <device/pci.h><br> #include <string.h><br> #include <stdint.h><br>-#if CONFIG_LOGICAL_CPUS<br>+#if IS_ENABLED(CONFIG_LOGICAL_CPUS)<br> #include <cpu/amd/multicore.h><br> #endif<br> #include <cpu/amd/amdk8_sysconf.h><br>diff --git a/src/mainboard/msi/ms9185/romstage.c b/src/mainboard/msi/ms9185/romstage.c<br>index 56eaa6a..5d03179 100644<br>--- a/src/mainboard/msi/ms9185/romstage.c<br>+++ b/src/mainboard/msi/ms9185/romstage.c<br>@@ -123,7 +123,7 @@<br> setup_coherent_ht_domain();<br> <br> wait_all_core0_started();<br>-#if CONFIG_LOGICAL_CPUS<br>+#if IS_ENABLED(CONFIG_LOGICAL_CPUS)<br> // It is said that we should start core1 after all core0 launched<br> /* becase optimize_link_coherent_ht is moved out from setup_coherent_ht_domain,<br> * So here need to make sure last core0 is started, esp for two way system,<br>@@ -144,7 +144,7 @@<br> needs_reset |= optimize_link_incoherent_ht(sysinfo);<br> #endif<br> <br>-#if CONFIG_SET_FIDVID<br>+#if IS_ENABLED(CONFIG_SET_FIDVID)<br> {<br> msr_t msr;<br> msr = rdmsr(0xc0010042);<br>diff --git a/src/mainboard/msi/ms9282/romstage.c b/src/mainboard/msi/ms9282/romstage.c<br>index fd90491..4fa40bf 100644<br>--- a/src/mainboard/msi/ms9282/romstage.c<br>+++ b/src/mainboard/msi/ms9282/romstage.c<br>@@ -154,7 +154,7 @@<br> <br> wait_all_core0_started();<br> <br>-#if CONFIG_LOGICAL_CPUS<br>+#if IS_ENABLED(CONFIG_LOGICAL_CPUS)<br> // It is said that we should start core1 after all core0 launched<br> start_other_cores();<br> //wait_all_other_cores_started(bsp_apicid);<br>diff --git a/src/mainboard/msi/ms9652_fam10/romstage.c b/src/mainboard/msi/ms9652_fam10/romstage.c<br>index 4acb240..11e9bc0 100644<br>--- a/src/mainboard/msi/ms9652_fam10/romstage.c<br>+++ b/src/mainboard/msi/ms9652_fam10/romstage.c<br>@@ -178,7 +178,7 @@<br> */<br> wait_all_core0_started();<br> <br>-#if CONFIG_LOGICAL_CPUS<br>+#if IS_ENABLED(CONFIG_LOGICAL_CPUS)<br> /* Core0 on each node is configured. Now setup any additional cores. */<br> printk(BIOS_DEBUG, "start_other_cores()\n");<br> start_other_cores(bsp_apicid);<br>@@ -189,7 +189,7 @@<br> <br> post_code(0x38);<br> <br>-#if CONFIG_SET_FIDVID<br>+#if IS_ENABLED(CONFIG_SET_FIDVID)<br> msr = rdmsr(0xc0010071);<br> printk(BIOS_DEBUG, "\nBegin FIDVID MSR 0xc0010071 0x%08x 0x%08x\n", msr.hi, msr.lo);<br> <br>diff --git a/src/mainboard/nvidia/l1_2pvv/romstage.c b/src/mainboard/nvidia/l1_2pvv/romstage.c<br>index b80f4f3..9c04b1c 100644<br>--- a/src/mainboard/nvidia/l1_2pvv/romstage.c<br>+++ b/src/mainboard/nvidia/l1_2pvv/romstage.c<br>@@ -142,7 +142,7 @@<br> setup_coherent_ht_domain(); // routing table and start other core0<br> <br> wait_all_core0_started();<br>-#if CONFIG_LOGICAL_CPUS<br>+#if IS_ENABLED(CONFIG_LOGICAL_CPUS)<br> // It is said that we should start core1 after all core0 launched<br> /* becase optimize_link_coherent_ht is moved out from setup_coherent_ht_domain,<br> * So here need to make sure last core0 is started, esp for two way system,<br>@@ -155,7 +155,7 @@<br> /* it will set up chains and store link pair for optimization later */<br> ht_setup_chains_x(sysinfo); // it will init sblnk and sbbusn, nodes, sbdn<br> <br>-#if CONFIG_SET_FIDVID<br>+#if IS_ENABLED(CONFIG_SET_FIDVID)<br> {<br> msr_t msr;<br> msr = rdmsr(0xc0010042);<br>diff --git a/src/mainboard/samsung/lumpy/acpi_tables.c b/src/mainboard/samsung/lumpy/acpi_tables.c<br>index 828546c..65922f3 100644<br>--- a/src/mainboard/samsung/lumpy/acpi_tables.c<br>+++ b/src/mainboard/samsung/lumpy/acpi_tables.c<br>@@ -25,7 +25,7 @@<br> #include <device/pci.h><br> #include <device/pci_ids.h><br> #include <ec/acpi/ec.h><br>-#if CONFIG_CHROMEOS<br>+#if IS_ENABLED(CONFIG_CHROMEOS)<br> #include <vendorcode/google/chromeos/gnvs.h><br> #endif<br> <br>diff --git a/src/mainboard/samsung/lumpy/romstage.c b/src/mainboard/samsung/lumpy/romstage.c<br>index 2a4bb4c..3afb196 100644<br>--- a/src/mainboard/samsung/lumpy/romstage.c<br>+++ b/src/mainboard/samsung/lumpy/romstage.c<br>@@ -38,7 +38,7 @@<br> #include <cpu/x86/msr.h><br> #include <halt.h><br> #include "option_table.h"<br>-#if CONFIG_DRIVERS_UART_8250IO<br>+#if IS_ENABLED(CONFIG_DRIVERS_UART_8250IO)<br> #include <superio/smsc/lpc47n207/lpc47n207.h><br> #endif<br> <br>@@ -47,7 +47,7 @@<br> /* Set COM1/COM2 decode range */<br> pci_write_config16(PCH_LPC_DEV, LPC_IO_DEC, 0x0010);<br> <br>-#if CONFIG_DRIVERS_UART_8250IO<br>+#if IS_ENABLED(CONFIG_DRIVERS_UART_8250IO)<br> /* Enable SuperIO + EC + KBC + COM1 + lpc47n207 config*/<br> pci_write_config16(PCH_LPC_DEV, LPC_EN, CNF1_LPC_EN | MC_LPC_EN |<br> KBC_LPC_EN | CNF2_LPC_EN | COMA_LPC_EN);<br>diff --git a/src/mainboard/samsung/stumpy/romstage.c b/src/mainboard/samsung/stumpy/romstage.c<br>index c4df1e7..ec5368d 100644<br>--- a/src/mainboard/samsung/stumpy/romstage.c<br>+++ b/src/mainboard/samsung/stumpy/romstage.c<br>@@ -38,12 +38,12 @@<br> #include <cpu/x86/msr.h><br> #include <halt.h><br> #include <tpm.h><br>-#if CONFIG_DRIVERS_UART_8250IO<br>+#if IS_ENABLED(CONFIG_DRIVERS_UART_8250IO)<br> #include <superio/smsc/lpc47n207/lpc47n207.h><br> #endif<br> <br> /* Stumpy USB Reset Disable defined in cmos.layout */<br>-#if CONFIG_USE_OPTION_TABLE<br>+#if IS_ENABLED(CONFIG_USE_OPTION_TABLE)<br> #include "option_table.h"<br> #define CMOS_USB_RESET_DISABLE (CMOS_VSTART_stumpy_usb_reset_disable >> 3)<br> #else<br>@@ -60,7 +60,7 @@<br> /* Set COM1/COM2 decode range */<br> pci_write_config16(PCH_LPC_DEV, LPC_IO_DEC, 0x0010);<br> <br>-#if CONFIG_DRIVERS_UART_8250IO<br>+#if IS_ENABLED(CONFIG_DRIVERS_UART_8250IO)<br> /* Enable SuperIO + PS/2 Keyboard/Mouse + COM1 + lpc47n207 config*/<br> pci_write_config16(PCH_LPC_DEV, LPC_EN, CNF1_LPC_EN | KBC_LPC_EN |\<br> CNF2_LPC_EN | COMA_LPC_EN);<br>diff --git a/src/mainboard/siemens/mc_bdx1/mainboard.c b/src/mainboard/siemens/mc_bdx1/mainboard.c<br>index fe35fe1..f5ea3ab 100644<br>--- a/src/mainboard/siemens/mc_bdx1/mainboard.c<br>+++ b/src/mainboard/siemens/mc_bdx1/mainboard.c<br>@@ -21,7 +21,7 @@<br> #include <device/pci_def.h><br> #include <device/pci_ops.h><br> #include <console/console.h><br>-#if CONFIG_VGA_ROM_RUN<br>+#if IS_ENABLED(CONFIG_VGA_ROM_RUN)<br> #include <x86emu/x86emu.h><br> #endif<br> #include <pc80/mc146818rtc.h><br>diff --git a/src/mainboard/siemens/mc_tcu3/mainboard.c b/src/mainboard/siemens/mc_tcu3/mainboard.c<br>index a11ff26..df08471 100644<br>--- a/src/mainboard/siemens/mc_tcu3/mainboard.c<br>+++ b/src/mainboard/siemens/mc_tcu3/mainboard.c<br>@@ -21,7 +21,7 @@<br> #include <device/pci_def.h><br> #include <device/pci_ops.h><br> #include <console/console.h><br>-#if CONFIG_VGA_ROM_RUN<br>+#if IS_ENABLED(CONFIG_VGA_ROM_RUN)<br> #include <x86emu/x86emu.h><br> #endif<br> #include <pc80/mc146818rtc.h><br>diff --git a/src/mainboard/siemens/sitemp_g1p1/acpi_tables.c b/src/mainboard/siemens/sitemp_g1p1/acpi_tables.c<br>index 0582566..30f963e 100644<br>--- a/src/mainboard/siemens/sitemp_g1p1/acpi_tables.c<br>+++ b/src/mainboard/siemens/sitemp_g1p1/acpi_tables.c<br>@@ -65,7 +65,7 @@<br> /* Write SB600 IOAPIC, only one */<br> current += acpi_create_madt_ioapic((acpi_madt_ioapic_t *) current, 2,<br> IO_APIC_ADDR, 0);<br>-#if !CONFIG_LINT01_CONVERSION<br>+#if !IS_ENABLED(CONFIG_LINT01_CONVERSION)<br> current += acpi_create_madt_irqoverride((acpi_madt_irqoverride_t *)<br> current, 0, 0, 2, 0);<br> <br>diff --git a/src/mainboard/siemens/sitemp_g1p1/mainboard.c b/src/mainboard/siemens/sitemp_g1p1/mainboard.c<br>index 1f266a7..bc2c75b 100644<br>--- a/src/mainboard/siemens/sitemp_g1p1/mainboard.c<br>+++ b/src/mainboard/siemens/sitemp_g1p1/mainboard.c<br>@@ -30,7 +30,7 @@<br> #include <southbridge/amd/rs690/chip.h><br> #include <southbridge/amd/rs690/rs690.h><br> #include <superio/ite/it8712f/it8712f.h><br>-#if CONFIG_PCI_OPTION_ROM_RUN_YABEL<br>+#if IS_ENABLED(CONFIG_PCI_OPTION_ROM_RUN_YABEL)<br> #include <x86emu/x86emu.h><br> #endif<br> #include "int15_func.h"<br>@@ -215,7 +215,7 @@<br> u8 t_range;<br> };<br> /* ############################################################################################# */<br>-#if CONFIG_PCI_OPTION_ROM_RUN_YABEL<br>+#if IS_ENABLED(CONFIG_PCI_OPTION_ROM_RUN_YABEL)<br> static int int15_handler(void)<br> {<br> #define BOOT_DISPLAY_DEFAULT 0<br>@@ -779,14 +779,14 @@<br> <br> static void mainboard_init(device_t dev)<br> {<br>-#if CONFIG_PCI_OPTION_ROM_RUN_REALMODE<br>+#if IS_ENABLED(CONFIG_PCI_OPTION_ROM_RUN_REALMODE)<br> INT15_function_extensions int15_func;<br> #endif<br> <br> printk(BIOS_DEBUG, "%s %s[%x/%x] %s\n",<br> dev_name(dev), dev_path(dev), dev->subsystem_vendor, dev->subsystem_device, __func__);<br> <br>-#if CONFIG_PCI_OPTION_ROM_RUN_REALMODE<br>+#if IS_ENABLED(CONFIG_PCI_OPTION_ROM_RUN_REALMODE)<br> if (get_option(&int15_func.regs.func00_LCD_panel_id, "lcd_panel_id") != CB_SUCCESS)<br> int15_func.regs.func00_LCD_panel_id = PANEL_TABLE_ID_NO;<br> int15_func.regs.func05_TV_standard = TV_MODE_NO;<br>@@ -808,7 +808,7 @@<br> <br> printk(BIOS_INFO, "%s %s[%x/%x] %s\n",<br> dev_name(dev), dev_path(dev), dev->subsystem_vendor, dev->subsystem_device, __func__);<br>-#if CONFIG_PCI_OPTION_ROM_RUN_YABEL<br>+#if IS_ENABLED(CONFIG_PCI_OPTION_ROM_RUN_YABEL)<br> /* Install custom int15 handler for VGA OPROM */<br> mainboard_interrupt_handlers(0x15, &int15_handler);<br> #endif<br>diff --git a/src/mainboard/siemens/sitemp_g1p1/romstage.c b/src/mainboard/siemens/sitemp_g1p1/romstage.c<br>index 6ac79d1..52d9c23 100644<br>--- a/src/mainboard/siemens/sitemp_g1p1/romstage.c<br>+++ b/src/mainboard/siemens/sitemp_g1p1/romstage.c<br>@@ -117,7 +117,7 @@<br> <br> setup_coherent_ht_domain();<br> <br>-#if CONFIG_LOGICAL_CPUS<br>+#if IS_ENABLED(CONFIG_LOGICAL_CPUS)<br> /* It is said that we should start core1 after all core0 launched */<br> wait_all_core0_started();<br> start_other_cores();<br>diff --git a/src/mainboard/sunw/ultra40/romstage.c b/src/mainboard/sunw/ultra40/romstage.c<br>index 1345871..405439f 100644<br>--- a/src/mainboard/sunw/ultra40/romstage.c<br>+++ b/src/mainboard/sunw/ultra40/romstage.c<br>@@ -124,7 +124,7 @@<br> needs_reset = setup_coherent_ht_domain();<br> <br> wait_all_core0_started();<br>-#if CONFIG_LOGICAL_CPUS<br>+#if IS_ENABLED(CONFIG_LOGICAL_CPUS)<br> // It is said that we should start core1 after all core0 launched<br> start_other_cores();<br> wait_all_other_cores_started(bsp_apicid);<br>diff --git a/src/mainboard/sunw/ultra40m2/romstage.c b/src/mainboard/sunw/ultra40m2/romstage.c<br>index 44bf851..9145ca5 100644<br>--- a/src/mainboard/sunw/ultra40m2/romstage.c<br>+++ b/src/mainboard/sunw/ultra40m2/romstage.c<br>@@ -135,7 +135,7 @@<br> setup_coherent_ht_domain(); // routing table and start other core0<br> <br> wait_all_core0_started();<br>-#if CONFIG_LOGICAL_CPUS<br>+#if IS_ENABLED(CONFIG_LOGICAL_CPUS)<br> // It is said that we should start core1 after all core0 launched<br> /* becase optimize_link_coherent_ht is moved out from setup_coherent_ht_domain,<br> * So here need to make sure last core0 is started, esp for two way system,<br>@@ -148,7 +148,7 @@<br> /* it will set up chains and store link pair for optimization later */<br> ht_setup_chains_x(sysinfo); // it will init sblnk and sbbusn, nodes, sbdn<br> <br>-#if CONFIG_SET_FIDVID<br>+#if IS_ENABLED(CONFIG_SET_FIDVID)<br> {<br> msr_t msr;<br> msr = rdmsr(0xc0010042);<br>diff --git a/src/mainboard/supermicro/h8dme/romstage.c b/src/mainboard/supermicro/h8dme/romstage.c<br>index d0ab05e..f173d1a 100644<br>--- a/src/mainboard/supermicro/h8dme/romstage.c<br>+++ b/src/mainboard/supermicro/h8dme/romstage.c<br>@@ -154,13 +154,13 @@<br> printk(BIOS_DEBUG, "bsp_apicid=%02x\n", bsp_apicid);<br> <br> set_sysinfo_in_ram(0); // in BSP so could hold all ap until sysinfo is in ram<br>-#if CONFIG_DEBUG_SMBUS<br>+#if IS_ENABLED(CONFIG_DEBUG_SMBUS)<br> dump_smbus_registers();<br> #endif<br> setup_coherent_ht_domain(); // routing table and start other core0<br> <br> wait_all_core0_started();<br>-#if CONFIG_LOGICAL_CPUS<br>+#if IS_ENABLED(CONFIG_LOGICAL_CPUS)<br> // It is said that we should start core1 after all core0 launched<br> /* becase optimize_link_coherent_ht is moved out from setup_coherent_ht_domain,<br> * So here need to make sure last core0 is started, esp for two way system,<br>@@ -173,7 +173,7 @@<br> /* it will set up chains and store link pair for optimization later */<br> ht_setup_chains_x(sysinfo); // it will init sblnk and sbbusn, nodes, sbdn<br> <br>-#if CONFIG_SET_FIDVID<br>+#if IS_ENABLED(CONFIG_SET_FIDVID)<br> {<br> msr_t msr;<br> msr = rdmsr(0xc0010042);<br>diff --git a/src/mainboard/supermicro/h8dmr/romstage.c b/src/mainboard/supermicro/h8dmr/romstage.c<br>index e4ee1c8..3f01c92 100644<br>--- a/src/mainboard/supermicro/h8dmr/romstage.c<br>+++ b/src/mainboard/supermicro/h8dmr/romstage.c<br>@@ -137,7 +137,7 @@<br> setup_coherent_ht_domain(); // routing table and start other core0<br> <br> wait_all_core0_started();<br>-#if CONFIG_LOGICAL_CPUS<br>+#if IS_ENABLED(CONFIG_LOGICAL_CPUS)<br> // It is said that we should start core1 after all core0 launched<br> /* becase optimize_link_coherent_ht is moved out from setup_coherent_ht_domain,<br> * So here need to make sure last core0 is started, esp for two way system,<br>@@ -150,7 +150,7 @@<br> /* it will set up chains and store link pair for optimization later */<br> ht_setup_chains_x(sysinfo); // it will init sblnk and sbbusn, nodes, sbdn<br> <br>-#if CONFIG_SET_FIDVID<br>+#if IS_ENABLED(CONFIG_SET_FIDVID)<br> {<br> msr_t msr;<br> msr = rdmsr(0xc0010042);<br>diff --git a/src/mainboard/supermicro/h8dmr_fam10/romstage.c b/src/mainboard/supermicro/h8dmr_fam10/romstage.c<br>index d457f1b..e100876 100644<br>--- a/src/mainboard/supermicro/h8dmr_fam10/romstage.c<br>+++ b/src/mainboard/supermicro/h8dmr_fam10/romstage.c<br>@@ -173,7 +173,7 @@<br> */<br> <br> wait_all_core0_started();<br>-#if CONFIG_LOGICAL_CPUS<br>+#if IS_ENABLED(CONFIG_LOGICAL_CPUS)<br> /* Core0 on each node is configured. Now setup any additional cores. */<br> printk(BIOS_DEBUG, "start_other_cores()\n");<br> start_other_cores(bsp_apicid);<br>@@ -183,7 +183,7 @@<br> <br> post_code(0x38);<br> <br>-#if CONFIG_SET_FIDVID<br>+#if IS_ENABLED(CONFIG_SET_FIDVID)<br> msr = rdmsr(0xc0010071);<br> printk(BIOS_DEBUG, "\nBegin FIDVID MSR 0xc0010071 0x%08x 0x%08x\n",<br> msr.hi, msr.lo);<br>diff --git a/src/mainboard/supermicro/h8qgi/buildOpts.c b/src/mainboard/supermicro/h8qgi/buildOpts.c<br>index 4db2c6f..b146afe 100644<br>--- a/src/mainboard/supermicro/h8qgi/buildOpts.c<br>+++ b/src/mainboard/supermicro/h8qgi/buildOpts.c<br>@@ -426,10 +426,10 @@<br> */<br> <br> /*<br>-#if CONFIG_CPU_AMD_AGESA_FAMILY15<br>+#if IS_ENABLED(CONFIG_CPU_AMD_AGESA_FAMILY15)<br> #define BLDOPT_REMOVE_FAMILY_10_SUPPORT TRUE<br> #endif<br>-#if CONFIG_CPU_AMD_AGESA_FAMILY10<br>+#if IS_ENABLED(CONFIG_CPU_AMD_AGESA_FAMILY10)<br> #define BLDOPT_REMOVE_FAMILY_15_SUPPORT TRUE<br> #endif<br> */<br>diff --git a/src/mainboard/supermicro/h8qgi/rd890_cfg.h b/src/mainboard/supermicro/h8qgi/rd890_cfg.h<br>index 35ddfbb..6607094 100644<br>--- a/src/mainboard/supermicro/h8qgi/rd890_cfg.h<br>+++ b/src/mainboard/supermicro/h8qgi/rd890_cfg.h<br>@@ -27,10 +27,10 @@<br> * [12..15] - Sublink (1..2), If NB connected to full link than Sublink should be set to 0.<br> */<br> #ifndef DEFAULT_HT_PATH<br>-#if CONFIG_CPU_AMD_AGESA_FAMILY10<br>+#if IS_ENABLED(CONFIG_CPU_AMD_AGESA_FAMILY10)<br> #define DEFAULT_HT_PATH {0x0, 0x3}<br> #endif<br>-#if CONFIG_CPU_AMD_AGESA_FAMILY15<br>+#if IS_ENABLED(CONFIG_CPU_AMD_AGESA_FAMILY15)<br> #define DEFAULT_HT_PATH {0x0, 0x1}<br> #endif<br> #endif<br>diff --git a/src/mainboard/supermicro/h8qgi/sb700_cfg.h b/src/mainboard/supermicro/h8qgi/sb700_cfg.h<br>index a5f371d..62b618f 100644<br>--- a/src/mainboard/supermicro/h8qgi/sb700_cfg.h<br>+++ b/src/mainboard/supermicro/h8qgi/sb700_cfg.h<br>@@ -36,13 +36,13 @@<br> * before AGESA module get call.<br> */<br> #ifndef BIOS_SIZE<br>-#if CONFIG_COREBOOT_ROMSIZE_KB_1024<br>+#if IS_ENABLED(CONFIG_COREBOOT_ROMSIZE_KB_1024)<br> #define BIOS_SIZE BIOS_SIZE_1M<br>-#elif CONFIG_COREBOOT_ROMSIZE_KB_2048 == 1<br>+#elif IS_ENABLED(CONFIG_COREBOOT_ROMSIZE_KB_2048)<br> #define BIOS_SIZE BIOS_SIZE_2M<br>-#elif CONFIG_COREBOOT_ROMSIZE_KB_4096 == 1<br>+#elif IS_ENABLED(CONFIG_COREBOOT_ROMSIZE_KB_4096)<br> #define BIOS_SIZE BIOS_SIZE_4M<br>-#elif CONFIG_COREBOOT_ROMSIZE_KB_8192 == 1<br>+#elif IS_ENABLED(CONFIG_COREBOOT_ROMSIZE_KB_8192)<br> #define BIOS_SIZE BIOS_SIZE_8M<br> #endif<br> #endif<br>diff --git a/src/mainboard/supermicro/h8qme_fam10/romstage.c b/src/mainboard/supermicro/h8qme_fam10/romstage.c<br>index 26f3da7..3554a05 100644<br>--- a/src/mainboard/supermicro/h8qme_fam10/romstage.c<br>+++ b/src/mainboard/supermicro/h8qme_fam10/romstage.c<br>@@ -239,7 +239,7 @@<br> */<br> <br> wait_all_core0_started();<br>-#if CONFIG_LOGICAL_CPUS<br>+#if IS_ENABLED(CONFIG_LOGICAL_CPUS)<br> /* Core0 on each node is configured. Now setup any additional cores. */<br> printk(BIOS_DEBUG, "start_other_cores()\n");<br> start_other_cores(bsp_apicid);<br>@@ -249,7 +249,7 @@<br> <br> post_code(0x38);<br> <br>-#if CONFIG_SET_FIDVID<br>+#if IS_ENABLED(CONFIG_SET_FIDVID)<br> msr = rdmsr(0xc0010071);<br> printk(BIOS_DEBUG, "\nBegin FIDVID MSR 0xc0010071 0x%08x 0x%08x\n", msr.hi, msr.lo);<br> <br>diff --git a/src/mainboard/supermicro/h8scm/rd890_cfg.h b/src/mainboard/supermicro/h8scm/rd890_cfg.h<br>index 35ddfbb..6607094 100644<br>--- a/src/mainboard/supermicro/h8scm/rd890_cfg.h<br>+++ b/src/mainboard/supermicro/h8scm/rd890_cfg.h<br>@@ -27,10 +27,10 @@<br> * [12..15] - Sublink (1..2), If NB connected to full link than Sublink should be set to 0.<br> */<br> #ifndef DEFAULT_HT_PATH<br>-#if CONFIG_CPU_AMD_AGESA_FAMILY10<br>+#if IS_ENABLED(CONFIG_CPU_AMD_AGESA_FAMILY10)<br> #define DEFAULT_HT_PATH {0x0, 0x3}<br> #endif<br>-#if CONFIG_CPU_AMD_AGESA_FAMILY15<br>+#if IS_ENABLED(CONFIG_CPU_AMD_AGESA_FAMILY15)<br> #define DEFAULT_HT_PATH {0x0, 0x1}<br> #endif<br> #endif<br>diff --git a/src/mainboard/supermicro/h8scm/sb700_cfg.h b/src/mainboard/supermicro/h8scm/sb700_cfg.h<br>index c067095..62b618f 100644<br>--- a/src/mainboard/supermicro/h8scm/sb700_cfg.h<br>+++ b/src/mainboard/supermicro/h8scm/sb700_cfg.h<br>@@ -36,13 +36,13 @@<br> * before AGESA module get call.<br> */<br> #ifndef BIOS_SIZE<br>-#if CONFIG_COREBOOT_ROMSIZE_KB_1024 == 1<br>+#if IS_ENABLED(CONFIG_COREBOOT_ROMSIZE_KB_1024)<br> #define BIOS_SIZE BIOS_SIZE_1M<br>-#elif CONFIG_COREBOOT_ROMSIZE_KB_2048 == 1<br>+#elif IS_ENABLED(CONFIG_COREBOOT_ROMSIZE_KB_2048)<br> #define BIOS_SIZE BIOS_SIZE_2M<br>-#elif CONFIG_COREBOOT_ROMSIZE_KB_4096 == 1<br>+#elif IS_ENABLED(CONFIG_COREBOOT_ROMSIZE_KB_4096)<br> #define BIOS_SIZE BIOS_SIZE_4M<br>-#elif CONFIG_COREBOOT_ROMSIZE_KB_8192 == 1<br>+#elif IS_ENABLED(CONFIG_COREBOOT_ROMSIZE_KB_8192)<br> #define BIOS_SIZE BIOS_SIZE_8M<br> #endif<br> #endif<br>diff --git a/src/mainboard/supermicro/h8scm_fam10/romstage.c b/src/mainboard/supermicro/h8scm_fam10/romstage.c<br>index 091514d..60288e0 100644<br>--- a/src/mainboard/supermicro/h8scm_fam10/romstage.c<br>+++ b/src/mainboard/supermicro/h8scm_fam10/romstage.c<br>@@ -153,7 +153,7 @@<br> */<br> wait_all_core0_started();<br> <br>-#if CONFIG_LOGICAL_CPUS<br>+#if IS_ENABLED(CONFIG_LOGICAL_CPUS)<br> /* Core0 on each node is configured. Now setup any additional cores. */<br> printk(BIOS_DEBUG, "start_other_cores()\n");<br> start_other_cores(bsp_apicid);<br>@@ -167,7 +167,7 @@<br> sr5650_early_setup();<br> sb7xx_51xx_early_setup();<br> <br>-#if CONFIG_SET_FIDVID<br>+#if IS_ENABLED(CONFIG_SET_FIDVID)<br> msr = rdmsr(0xc0010071);<br> printk(BIOS_DEBUG, "\nBegin FIDVID MSR 0xc0010071 0x%08x 0x%08x\n", msr.hi, msr.lo);<br> <br>diff --git a/src/mainboard/technexion/tim5690/mainboard.c b/src/mainboard/technexion/tim5690/mainboard.c<br>index 8bc1075..edc1170 100644<br>--- a/src/mainboard/technexion/tim5690/mainboard.c<br>+++ b/src/mainboard/technexion/tim5690/mainboard.c<br>@@ -184,7 +184,7 @@<br> it8712f_exit_conf();<br> }<br> <br>-#if CONFIG_VGA_ROM_RUN<br>+#if IS_ENABLED(CONFIG_VGA_ROM_RUN)<br> /* The LCD's panel id seletion. */<br> static void lcd_panel_id(rs690_vbios_regs *vbios_regs, u8 num_id)<br> {<br>@@ -221,7 +221,7 @@<br> static void mainboard_enable(device_t dev)<br> {<br> u16 gpio_base = IT8712F_SIMPLE_IO_BASE;<br>-#if CONFIG_VGA_ROM_RUN<br>+#if IS_ENABLED(CONFIG_VGA_ROM_RUN)<br> rs690_vbios_regs vbios_regs;<br> u8 port2;<br> #endif<br>@@ -230,7 +230,7 @@<br> <br> mb_gpio_init(&gpio_base);<br> <br>-#if CONFIG_VGA_ROM_RUN<br>+#if IS_ENABLED(CONFIG_VGA_ROM_RUN)<br> /* The LCD's panel id seletion by switch. */<br> port2 = inb(gpio_base+1);<br> lcd_panel_id(&vbios_regs, ((~port2) & 0xf));<br>diff --git a/src/mainboard/technexion/tim5690/romstage.c b/src/mainboard/technexion/tim5690/romstage.c<br>index 3b4b4fd..744ea67 100644<br>--- a/src/mainboard/technexion/tim5690/romstage.c<br>+++ b/src/mainboard/technexion/tim5690/romstage.c<br>@@ -95,7 +95,7 @@<br> <br> setup_coherent_ht_domain();<br> <br>-#if CONFIG_LOGICAL_CPUS<br>+#if IS_ENABLED(CONFIG_LOGICAL_CPUS)<br> /* It is said that we should start core1 after all core0 launched */<br> wait_all_core0_started();<br> start_other_cores();<br>diff --git a/src/mainboard/technexion/tim8690/romstage.c b/src/mainboard/technexion/tim8690/romstage.c<br>index 6030864..18e3140 100644<br>--- a/src/mainboard/technexion/tim8690/romstage.c<br>+++ b/src/mainboard/technexion/tim8690/romstage.c<br>@@ -91,7 +91,7 @@<br> <br> setup_coherent_ht_domain();<br> <br>-#if CONFIG_LOGICAL_CPUS<br>+#if IS_ENABLED(CONFIG_LOGICAL_CPUS)<br> /* It is said that we should start core1 after all core0 launched */<br> wait_all_core0_started();<br> start_other_cores();<br>diff --git a/src/mainboard/thomson/ip1000/spd_table.h b/src/mainboard/thomson/ip1000/spd_table.h<br>index 0ecf1c0..1de05ed 100644<br>--- a/src/mainboard/thomson/ip1000/spd_table.h<br>+++ b/src/mainboard/thomson/ip1000/spd_table.h<br>@@ -16,11 +16,11 @@<br> <br> #include <spd.h><br> <br>-#if CONFIG_ONBOARD_MEMORY_64MB<br>+#if IS_ENABLED(CONFIG_ONBOARD_MEMORY_64MB)<br> <br> #define DENSITY 0x10<br> <br>-#elif CONFIG_ONBOARD_MEMORY_128MB<br>+#elif IS_ENABLED(CONFIG_ONBOARD_MEMORY_128MB)<br> <br> #define DENSITY 0x20<br> <br>diff --git a/src/mainboard/tyan/s2912/romstage.c b/src/mainboard/tyan/s2912/romstage.c<br>index 6a47612..89f3175 100644<br>--- a/src/mainboard/tyan/s2912/romstage.c<br>+++ b/src/mainboard/tyan/s2912/romstage.c<br>@@ -140,7 +140,7 @@<br> setup_coherent_ht_domain(); // routing table and start other core0<br> <br> wait_all_core0_started();<br>-#if CONFIG_LOGICAL_CPUS<br>+#if IS_ENABLED(CONFIG_LOGICAL_CPUS)<br> // It is said that we should start core1 after all core0 launched<br> /* becase optimize_link_coherent_ht is moved out from setup_coherent_ht_domain,<br> * So here need to make sure last core0 is started, esp for two way system,<br>@@ -153,7 +153,7 @@<br> /* it will set up chains and store link pair for optimization later */<br> ht_setup_chains_x(sysinfo); // it will init sblnk and sbbusn, nodes, sbdn<br> <br>-#if CONFIG_SET_FIDVID<br>+#if IS_ENABLED(CONFIG_SET_FIDVID)<br> {<br> msr_t msr;<br> msr = rdmsr(0xc0010042);<br>diff --git a/src/mainboard/tyan/s2912_fam10/romstage.c b/src/mainboard/tyan/s2912_fam10/romstage.c<br>index 4c8c19f..b449f77 100644<br>--- a/src/mainboard/tyan/s2912_fam10/romstage.c<br>+++ b/src/mainboard/tyan/s2912_fam10/romstage.c<br>@@ -174,7 +174,7 @@<br> */<br> wait_all_core0_started();<br> <br>-#if CONFIG_LOGICAL_CPUS<br>+#if IS_ENABLED(CONFIG_LOGICAL_CPUS)<br> /* Core0 on each node is configured. Now setup any additional cores. */<br> printk(BIOS_DEBUG, "start_other_cores()\n");<br> start_other_cores(bsp_apicid);<br>@@ -184,7 +184,7 @@<br> <br> post_code(0x38);<br> <br>-#if CONFIG_SET_FIDVID<br>+#if IS_ENABLED(CONFIG_SET_FIDVID)<br> msr = rdmsr(0xc0010071);<br> printk(BIOS_DEBUG, "\nBegin FIDVID MSR 0xc0010071 0x%08x 0x%08x\n", msr.hi, msr.lo);<br> <br>diff --git a/src/mainboard/tyan/s8226/buildOpts.c b/src/mainboard/tyan/s8226/buildOpts.c<br>index 1312892..e27ec16 100644<br>--- a/src/mainboard/tyan/s8226/buildOpts.c<br>+++ b/src/mainboard/tyan/s8226/buildOpts.c<br>@@ -426,10 +426,10 @@<br> */<br> <br> /*<br>-#if CONFIG_CPU_AMD_AGESA_FAMILY15<br>+#if IS_ENABLED(CONFIG_CPU_AMD_AGESA_FAMILY15)<br> #define BLDOPT_REMOVE_FAMILY_10_SUPPORT TRUE<br> #endif<br>-#if CONFIG_CPU_AMD_AGESA_FAMILY10<br>+#if IS_ENABLED(CONFIG_CPU_AMD_AGESA_FAMILY10)<br> #define BLDOPT_REMOVE_FAMILY_15_SUPPORT TRUE<br> #endif<br> */<br>diff --git a/src/mainboard/tyan/s8226/rd890_cfg.h b/src/mainboard/tyan/s8226/rd890_cfg.h<br>index 35ddfbb..6607094 100644<br>--- a/src/mainboard/tyan/s8226/rd890_cfg.h<br>+++ b/src/mainboard/tyan/s8226/rd890_cfg.h<br>@@ -27,10 +27,10 @@<br> * [12..15] - Sublink (1..2), If NB connected to full link than Sublink should be set to 0.<br> */<br> #ifndef DEFAULT_HT_PATH<br>-#if CONFIG_CPU_AMD_AGESA_FAMILY10<br>+#if IS_ENABLED(CONFIG_CPU_AMD_AGESA_FAMILY10)<br> #define DEFAULT_HT_PATH {0x0, 0x3}<br> #endif<br>-#if CONFIG_CPU_AMD_AGESA_FAMILY15<br>+#if IS_ENABLED(CONFIG_CPU_AMD_AGESA_FAMILY15)<br> #define DEFAULT_HT_PATH {0x0, 0x1}<br> #endif<br> #endif<br>diff --git a/src/mainboard/tyan/s8226/sb700_cfg.h b/src/mainboard/tyan/s8226/sb700_cfg.h<br>index 3f82931..bed9161 100644<br>--- a/src/mainboard/tyan/s8226/sb700_cfg.h<br>+++ b/src/mainboard/tyan/s8226/sb700_cfg.h<br>@@ -36,13 +36,13 @@<br> * before AGESA module get call.<br> */<br> #ifndef BIOS_SIZE<br>-#if CONFIG_COREBOOT_ROMSIZE_KB_1024<br>+#if IS_ENABLED(CONFIG_COREBOOT_ROMSIZE_KB_1024)<br> #define BIOS_SIZE BIOS_SIZE_1M<br>-#elif CONFIG_COREBOOT_ROMSIZE_KB_2048<br>+#elif IS_ENABLED(CONFIG_COREBOOT_ROMSIZE_KB_2048)<br> #define BIOS_SIZE BIOS_SIZE_2M<br>-#elif CONFIG_COREBOOT_ROMSIZE_KB_4096<br>+#elif IS_ENABLED(CONFIG_COREBOOT_ROMSIZE_KB_4096)<br> #define BIOS_SIZE BIOS_SIZE_4M<br>-#elif CONFIG_COREBOOT_ROMSIZE_KB_8192<br>+#elif IS_ENABLED(CONFIG_COREBOOT_ROMSIZE_KB_8192)<br> #define BIOS_SIZE BIOS_SIZE_8M<br> #endif<br> #endif<br>diff --git a/src/mainboard/via/epia-m850/mainboard.c b/src/mainboard/via/epia-m850/mainboard.c<br>index 335e86b..68c49bc 100644<br>--- a/src/mainboard/via/epia-m850/mainboard.c<br>+++ b/src/mainboard/via/epia-m850/mainboard.c<br>@@ -19,7 +19,7 @@<br> #include <device/pci_ops.h><br> #include <console/console.h><br> <br>-#if CONFIG_VGA_ROM_RUN<br>+#if IS_ENABLED(CONFIG_VGA_ROM_RUN)<br> <br> #include <arch/interrupt.h><br> #include <x86emu/x86emu.h><br>@@ -96,7 +96,7 @@<br> {<br> (void)dev;<br> <br>-#if CONFIG_VGA_ROM_RUN<br>+#if IS_ENABLED(CONFIG_VGA_ROM_RUN)<br> printk(BIOS_DEBUG, "Installing INT15 handler...\n");<br> mainboard_interrupt_handlers(0x15, &vx900_int15_handler);<br> #endif<br>diff --git a/src/mainboard/via/epia-m850/romstage.c b/src/mainboard/via/epia-m850/romstage.c<br>index 450f7d7..a79d419 100644<br>--- a/src/mainboard/via/epia-m850/romstage.c<br>+++ b/src/mainboard/via/epia-m850/romstage.c<br>@@ -90,7 +90,7 @@<br> printk(BIOS_DEBUG, "We passed RAM verify\n");<br> <br> /* We got RAM working, now we can write the timestamps to RAM */<br>-#if CONFIG_EARLY_CBMEM_INIT<br>+#if IS_ENABLED(CONFIG_EARLY_CBMEM_INIT)<br> cbmem_recovery(0);<br> #endif<br> /* FIXME: See if this is needed or take this out please */<br>diff --git a/src/mainboard/winent/mb6047/romstage.c b/src/mainboard/winent/mb6047/romstage.c<br>index 09de180..ddce5c6 100644<br>--- a/src/mainboard/winent/mb6047/romstage.c<br>+++ b/src/mainboard/winent/mb6047/romstage.c<br>@@ -37,7 +37,7 @@<br> #include <southbridge/nvidia/ck804/early_setup_ss.h><br> #include "southbridge/nvidia/ck804/early_setup_car.c"<br> #include "cpu/amd/model_fxx/init_cpus.c"<br>-#if CONFIG_SET_FIDVID<br>+#if IS_ENABLED(CONFIG_SET_FIDVID)<br> #include "cpu/amd/model_fxx/fidvid.c"<br> #endif<br> #include "northbridge/amd/amdk8/early_ht.c"<br>@@ -100,7 +100,7 @@<br> start_other_cores();<br> wait_all_other_cores_started(bsp_apicid);<br> <br>-#if CONFIG_SET_FIDVID<br>+#if IS_ENABLED(CONFIG_SET_FIDVID)<br> /* Check to see if processor is capable of changing FIDVID */<br> /* otherwise it will throw a GP# when reading FIDVID_STATUS */<br> if ((cpuid_edx(0x80000007) & 0x6) == 0x6) {<br></pre><p>To view, visit <a href="https://review.coreboot.org/20344">change 20344</a>. To unsubscribe, visit <a href="https://review.coreboot.org/settings">settings</a>.</p><div itemscope itemtype="http://schema.org/EmailMessage"><div itemscope itemprop="action" itemtype="http://schema.org/ViewAction"><link itemprop="url" href="https://review.coreboot.org/20344"/><meta itemprop="name" content="View Change"/></div></div>
<div style="display:none"> Gerrit-Project: coreboot </div>
<div style="display:none"> Gerrit-Branch: master </div>
<div style="display:none"> Gerrit-MessageType: newchange </div>
<div style="display:none"> Gerrit-Change-Id: Ifba3257b0328d0b6ad1bee9bf885683998df5851 </div>
<div style="display:none"> Gerrit-Change-Number: 20344 </div>
<div style="display:none"> Gerrit-PatchSet: 1 </div>
<div style="display:none"> Gerrit-Owner: Martin Roth <martinroth@google.com> </div>