<p>Martin Roth has uploaded this change for <strong>review</strong>.</p><p><a href="https://review.coreboot.org/20346">View Change</a></p><pre style="font-family: monospace,monospace; white-space: pre-wrap;">nb/intel: add IS_ENABLED() around Kconfig symbol references<br><br>Some of these can be changed from #if to if(), but that will happen<br>in a follow-on commmit.<br><br>Change-Id: Id5bc8b75b1fa372f31982b8636f1efa4975b61a5<br>Signed-off-by: Martin Roth <martinroth@google.com><br>---<br>M src/northbridge/intel/e7505/raminit.c<br>M src/northbridge/intel/fsp_sandybridge/acpi/sandybridge.asl<br>M src/northbridge/intel/fsp_sandybridge/early_init.c<br>M src/northbridge/intel/haswell/acpi/haswell.asl<br>M src/northbridge/intel/haswell/gma.c<br>M src/northbridge/intel/haswell/northbridge.c<br>M src/northbridge/intel/i440bx/debug.c<br>M src/northbridge/intel/i440bx/raminit.c<br>M src/northbridge/intel/i440bx/raminit.h<br>M src/northbridge/intel/i5000/raminit.c<br>M src/northbridge/intel/i82810/debug.c<br>M src/northbridge/intel/i82810/raminit.c<br>M src/northbridge/intel/i82810/raminit.h<br>M src/northbridge/intel/i82830/raminit.c<br>M src/northbridge/intel/i82830/smihandler.c<br>M src/northbridge/intel/i82830/vga.c<br>M src/northbridge/intel/i855/raminit.c<br>M src/northbridge/intel/i945/early_init.c<br>M src/northbridge/intel/i945/raminit.c<br>M src/northbridge/intel/i945/raminit.h<br>M src/northbridge/intel/nehalem/acpi/nehalem.asl<br>M src/northbridge/intel/nehalem/early_init.c<br>M src/northbridge/intel/nehalem/northbridge.c<br>M src/northbridge/intel/pineview/raminit.c<br>M src/northbridge/intel/sandybridge/acpi/sandybridge.asl<br>M src/northbridge/intel/sandybridge/early_init.c<br>M src/northbridge/intel/sandybridge/northbridge.c<br>M src/northbridge/intel/sandybridge/raminit_mrc.c<br>28 files changed, 48 insertions(+), 48 deletions(-)<br><br></pre><pre style="font-family: monospace,monospace; white-space: pre-wrap;">git pull ssh://review.coreboot.org:29418/coreboot refs/changes/46/20346/1</pre><pre style="font-family: monospace,monospace; white-space: pre-wrap;">diff --git a/src/northbridge/intel/e7505/raminit.c b/src/northbridge/intel/e7505/raminit.c<br>index 975a373..b38132a 100644<br>--- a/src/northbridge/intel/e7505/raminit.c<br>+++ b/src/northbridge/intel/e7505/raminit.c<br>@@ -41,7 +41,7 @@<br> // Unfortunately the code seems to chew up several K of space.<br> //#define VALIDATE_DIMM_COMPATIBILITY<br> <br>-#if CONFIG_DEBUG_RAM_SETUP<br>+#if IS_ENABLED(CONFIG_DEBUG_RAM_SETUP)<br> #define RAM_DEBUG_MESSAGE(x)    printk(BIOS_DEBUG, x)<br> #define RAM_DEBUG_HEX32(x)      printk(BIOS_DEBUG, "%08x", x)<br> #define RAM_DEBUG_HEX8(x)     printk(BIOS_DEBUG, "%02x", x)<br>@@ -1003,7 +1003,7 @@<br>                         ::: "edi"<br>          );<br> <br>-#if CONFIG_DEBUG_RAM_SETUP<br>+#if IS_ENABLED(CONFIG_DEBUG_RAM_SETUP)<br>           unsigned int a1, a2;<br>          asm volatile("movd %%xmm2, %%eax;" : "=a" (a1) ::);<br>               asm volatile("movd %%xmm3, %%eax;" : "=a" (a2) ::);<br>diff --git a/src/northbridge/intel/fsp_sandybridge/acpi/sandybridge.asl b/src/northbridge/intel/fsp_sandybridge/acpi/sandybridge.asl<br>index 79586cd..ea0dcf8 100644<br>--- a/src/northbridge/intel/fsp_sandybridge/acpi/sandybridge.asl<br>+++ b/src/northbridge/intel/fsp_sandybridge/acpi/sandybridge.asl<br>@@ -33,7 +33,7 @@<br>           Memory32Fixed(ReadWrite, 0xfed40000, 0x00005000) // Misc ICH<br>          Memory32Fixed(ReadWrite, 0xfed45000, 0x0004b000) // Misc ICH<br> <br>-#if CONFIG_CHROMEOS_RAMOOPS<br>+#if IS_ENABLED(CONFIG_CHROMEOS_RAMOOPS)<br>               Memory32Fixed(ReadWrite, CONFIG_CHROMEOS_RAMOOPS_RAM_START,<br>                                    CONFIG_CHROMEOS_RAMOOPS_RAM_SIZE)<br> #endif<br>diff --git a/src/northbridge/intel/fsp_sandybridge/early_init.c b/src/northbridge/intel/fsp_sandybridge/early_init.c<br>index 5071def..1afb6cd 100644<br>--- a/src/northbridge/intel/fsp_sandybridge/early_init.c<br>+++ b/src/northbridge/intel/fsp_sandybridge/early_init.c<br>@@ -42,7 +42,7 @@<br>       pci_write_config8(PCI_DEV(0, 0x00, 0), PAM5, 0x33);<br>   pci_write_config8(PCI_DEV(0, 0x00, 0), PAM6, 0x33);<br> <br>-#if CONFIG_ELOG_BOOT_COUNT<br>+#if IS_ENABLED(CONFIG_ELOG_BOOT_COUNT)<br>  /* Increment Boot Counter for non-S3 resume */<br>        if ((inw(DEFAULT_PMBASE + PM1_STS) & WAK_STS) &&<br>      ((inl(DEFAULT_PMBASE + PM1_CNT) >> 10) & 7) != SLP_TYP_S3)<br>@@ -51,7 +51,7 @@<br> <br>        printk(BIOS_DEBUG, " done.\n");<br> <br>-#if CONFIG_ELOG_BOOT_COUNT<br>+#if IS_ENABLED(CONFIG_ELOG_BOOT_COUNT)<br>    /* Increment Boot Counter except when resuming from S3 */<br>     if ((inw(DEFAULT_PMBASE + PM1_STS) & WAK_STS) &&<br>      ((inl(DEFAULT_PMBASE + PM1_CNT) >> 10) & 7) == SLP_TYP_S3)<br>diff --git a/src/northbridge/intel/haswell/acpi/haswell.asl b/src/northbridge/intel/haswell/acpi/haswell.asl<br>index 8395a95..726fbe4 100644<br>--- a/src/northbridge/intel/haswell/acpi/haswell.asl<br>+++ b/src/northbridge/intel/haswell/acpi/haswell.asl<br>@@ -33,7 +33,7 @@<br>          Memory32Fixed(ReadWrite, 0xfed40000, 0x00005000) // Misc ICH<br>          Memory32Fixed(ReadWrite, 0xfed45000, 0x0004b000) // Misc ICH<br> <br>-#if CONFIG_CHROMEOS_RAMOOPS<br>+#if IS_ENABLED(CONFIG_CHROMEOS_RAMOOPS)<br>               Memory32Fixed(ReadWrite, CONFIG_CHROMEOS_RAMOOPS_RAM_START,<br>                                    CONFIG_CHROMEOS_RAMOOPS_RAM_SIZE)<br> #endif<br>diff --git a/src/northbridge/intel/haswell/gma.c b/src/northbridge/intel/haswell/gma.c<br>index fa4dec9..76da5a0 100644<br>--- a/src/northbridge/intel/haswell/gma.c<br>+++ b/src/northbridge/intel/haswell/gma.c<br>@@ -30,7 +30,7 @@<br> #include "chip.h"<br> #include "haswell.h"<br> <br>-#if CONFIG_CHROMEOS<br>+#if IS_ENABLED(CONFIG_CHROMEOS)<br> #include <vendorcode/google/chromeos/chromeos.h><br> #endif<br> <br>diff --git a/src/northbridge/intel/haswell/northbridge.c b/src/northbridge/intel/haswell/northbridge.c<br>index 63cbb70..a8c8015 100644<br>--- a/src/northbridge/intel/haswell/northbridge.c<br>+++ b/src/northbridge/intel/haswell/northbridge.c<br>@@ -368,7 +368,7 @@<br>  mmio_resource(dev, index++, (0xa0000 >> 10), (0xc0000 - 0xa0000) >> 10);<br>  reserved_ram_resource(dev, index++, (0xc0000 >> 10),<br>                          (0x100000 - 0xc0000) >> 10);<br>-#if CONFIG_CHROMEOS_RAMOOPS<br>+#if IS_ENABLED(CONFIG_CHROMEOS_RAMOOPS)<br>      reserved_ram_resource(dev, index++,<br>                   CONFIG_CHROMEOS_RAMOOPS_RAM_START >> 10,<br>                        CONFIG_CHROMEOS_RAMOOPS_RAM_SIZE >> 10);<br>diff --git a/src/northbridge/intel/i440bx/debug.c b/src/northbridge/intel/i440bx/debug.c<br>index 064df5b..c69725b 100644<br>--- a/src/northbridge/intel/i440bx/debug.c<br>+++ b/src/northbridge/intel/i440bx/debug.c<br>@@ -5,7 +5,7 @@<br> #include <spd.h><br> #include <console/console.h><br> <br>-#if CONFIG_DEBUG_RAM_SETUP<br>+#if IS_ENABLED(CONFIG_DEBUG_RAM_SETUP)<br> void dump_spd_registers(void)<br> {<br>   int i;<br>diff --git a/src/northbridge/intel/i440bx/raminit.c b/src/northbridge/intel/i440bx/raminit.c<br>index e217c23..86e9595 100644<br>--- a/src/northbridge/intel/i440bx/raminit.c<br>+++ b/src/northbridge/intel/i440bx/raminit.c<br>@@ -32,7 +32,7 @@<br> #define NB PCI_DEV(0, 0, 0)<br> <br> /* Debugging macros. */<br>-#if CONFIG_DEBUG_RAM_SETUP<br>+#if IS_ENABLED(CONFIG_DEBUG_RAM_SETUP)<br> #define PRINT_DEBUG(x...) printk(BIOS_DEBUG, x)<br> #define DUMPNORTH()             dump_pci_device(NB)<br> #else<br>@@ -301,7 +301,7 @@<br>       *         0 = 3 clocks of RAS# precharge<br>      *         1 = 2 clocks of RAS# precharge<br>      */<br>-#if CONFIG_SDRAMPWR_4DIMM<br>+#if IS_ENABLED(CONFIG_SDRAMPWR_4DIMM)<br>       SDRAMC + 0, 0x00, 0x10, /* The board has 4 DIMM slots. */<br> #else<br>     SDRAMC + 0, 0x00, 0x00, /* The board has 3 DIMM slots. */<br>diff --git a/src/northbridge/intel/i440bx/raminit.h b/src/northbridge/intel/i440bx/raminit.h<br>index a10485a..609b591 100644<br>--- a/src/northbridge/intel/i440bx/raminit.h<br>+++ b/src/northbridge/intel/i440bx/raminit.h<br>@@ -26,7 +26,7 @@<br> void sdram_set_spd_registers(void);<br> void sdram_enable(void);<br> /* Debug */<br>-#if CONFIG_DEBUG_RAM_SETUP<br>+#if IS_ENABLED(CONFIG_DEBUG_RAM_SETUP)<br> void dump_spd_registers(void);<br> void dump_pci_device(unsigned dev);<br> #else<br>diff --git a/src/northbridge/intel/i5000/raminit.c b/src/northbridge/intel/i5000/raminit.c<br>index ffc2dc2..4c71a5a 100644<br>--- a/src/northbridge/intel/i5000/raminit.c<br>+++ b/src/northbridge/intel/i5000/raminit.c<br>@@ -1752,7 +1752,7 @@<br>         if (setup.branch[1].used)<br>             i5000_fbd_next_state(&setup.branch[1], I5000_FBDHPC_STATE_ACTIVE);<br> <br>-#if CONFIG_NORTHBRIDGE_INTEL_I5000_RAM_CHECK<br>+#if IS_ENABLED(CONFIG_NORTHBRIDGE_INTEL_I5000_RAM_CHECK)<br>   if (ram_check_nodie(0x000000, 0x0a0000) ||<br>        ram_check_nodie(0x100000, MIN(setup.totalmem * 1048576, 0xd0000000))) {<br>           i5000_try_restart("RAM verification failed");<br>diff --git a/src/northbridge/intel/i82810/debug.c b/src/northbridge/intel/i82810/debug.c<br>index 1b45bc2..d817138 100644<br>--- a/src/northbridge/intel/i82810/debug.c<br>+++ b/src/northbridge/intel/i82810/debug.c<br>@@ -5,7 +5,7 @@<br> #include <spd.h><br> #include <console/console.h><br> <br>-#if CONFIG_DEBUG_RAM_SETUP<br>+#if IS_ENABLED(CONFIG_DEBUG_RAM_SETUP)<br> void dump_spd_registers(void)<br> {<br>  int i;<br>diff --git a/src/northbridge/intel/i82810/raminit.c b/src/northbridge/intel/i82810/raminit.c<br>index cc8c328..6fe4fb5 100644<br>--- a/src/northbridge/intel/i82810/raminit.c<br>+++ b/src/northbridge/intel/i82810/raminit.c<br>@@ -30,7 +30,7 @@<br> -----------------------------------------------------------------------------*/<br> <br> /* Debugging macros. */<br>-#if CONFIG_DEBUG_RAM_SETUP<br>+#if IS_ENABLED(CONFIG_DEBUG_RAM_SETUP)<br> #define PRINT_DEBUG(x...)     printk(BIOS_DEBUG, x)<br> #define DUMPNORTH()             dump_pci_device(PCI_DEV(0, 0, 0))<br> #else<br>diff --git a/src/northbridge/intel/i82810/raminit.h b/src/northbridge/intel/i82810/raminit.h<br>index 3d263ec..6b9d175 100644<br>--- a/src/northbridge/intel/i82810/raminit.h<br>+++ b/src/northbridge/intel/i82810/raminit.h<br>@@ -26,7 +26,7 @@<br> void sdram_enable(void);<br> <br> /* Debug */<br>-#if CONFIG_DEBUG_RAM_SETUP<br>+#if IS_ENABLED(CONFIG_DEBUG_RAM_SETUP)<br> void dump_spd_registers(void);<br> void dump_pci_device(unsigned dev);<br> #else<br>diff --git a/src/northbridge/intel/i82830/raminit.c b/src/northbridge/intel/i82830/raminit.c<br>index 7850c87..e0f2c6e 100644<br>--- a/src/northbridge/intel/i82830/raminit.c<br>+++ b/src/northbridge/intel/i82830/raminit.c<br>@@ -25,7 +25,7 @@<br> -----------------------------------------------------------------------------*/<br> <br> /* Debugging macros. */<br>-#if CONFIG_DEBUG_RAM_SETUP<br>+#if IS_ENABLED(CONFIG_DEBUG_RAM_SETUP)<br> #define PRINTK_DEBUG(x...)    printk(BIOS_DEBUG, x)<br> #define DUMPNORTH()             dump_pci_device(PCI_DEV(0, 0, 0))<br> #else<br>diff --git a/src/northbridge/intel/i82830/smihandler.c b/src/northbridge/intel/i82830/smihandler.c<br>index cb35141..51841e5 100644<br>--- a/src/northbridge/intel/i82830/smihandler.c<br>+++ b/src/northbridge/intel/i82830/smihandler.c<br>@@ -31,7 +31,7 @@<br> /* If YABEL is enabled and it's not running at 0x00000000, we have to add some<br>  * offset to all our mbi object memory accesses<br>  */<br>-#if CONFIG_PCI_OPTION_ROM_RUN_YABEL && !CONFIG_YABEL_DIRECTHW<br>+#if IS_ENABLED(CONFIG_PCI_OPTION_ROM_RUN_YABEL) && !CONFIG_YABEL_DIRECTHW<br> #define OBJ_OFFSET CONFIG_YABEL_VIRTMEM_LOCATION<br> #else<br> #define OBJ_OFFSET 0x00000<br>diff --git a/src/northbridge/intel/i82830/vga.c b/src/northbridge/intel/i82830/vga.c<br>index e673170..20c9d0a 100644<br>--- a/src/northbridge/intel/i82830/vga.c<br>+++ b/src/northbridge/intel/i82830/vga.c<br>@@ -43,7 +43,7 @@<br>        printk(BIOS_INFO, "Graphics Initialization Complete\n");<br> <br>         /* Enable TV-Out */<br>-#if CONFIG_PCI_OPTION_ROM_RUN_YABEL<br>+#if IS_ENABLED(CONFIG_PCI_OPTION_ROM_RUN_YABEL)<br> #define PIPE_A_CRT        (1 << 0)<br> #define PIPE_A_LFP     (1 << 1)<br> #define PIPE_A_TV      (1 << 3)<br>diff --git a/src/northbridge/intel/i855/raminit.c b/src/northbridge/intel/i855/raminit.c<br>index 3fd5765..8041951 100644<br>--- a/src/northbridge/intel/i855/raminit.c<br>+++ b/src/northbridge/intel/i855/raminit.c<br>@@ -29,7 +29,7 @@<br> #define VALIDATE_DIMM_COMPATIBILITY<br> <br> /* Debugging macros. */<br>-#if CONFIG_DEBUG_RAM_SETUP<br>+#if IS_ENABLED(CONFIG_DEBUG_RAM_SETUP)<br> #define PRINTK_DEBUG(x...)      printk(BIOS_DEBUG, x)<br> #define DUMPNORTH()             dump_pci_device(NORTHBRIDGE_MMC)<br> #else<br>@@ -868,11 +868,11 @@<br> <br> static void spd_update(u8 reg, u32 new_value)<br> {<br>-#if CONFIG_DEBUG_RAM_SETUP<br>+#if IS_ENABLED(CONFIG_DEBUG_RAM_SETUP)<br>    u32 value1 = pci_read_config32(NORTHBRIDGE_MMC, reg);<br> #endif<br>        pci_write_config32(NORTHBRIDGE_MMC, reg, new_value);<br>-#if CONFIG_DEBUG_RAM_SETUP<br>+#if IS_ENABLED(CONFIG_DEBUG_RAM_SETUP)<br>    u32 value2 = pci_read_config32(NORTHBRIDGE_MMC, reg);<br>         PRINTK_DEBUG("update reg %02x, old: %08x, new: %08x, read back: %08x\n", reg, value1, new_value, value2);<br> #endif<br>diff --git a/src/northbridge/intel/i945/early_init.c b/src/northbridge/intel/i945/early_init.c<br>index 45501d1..1d473d3 100644<br>--- a/src/northbridge/intel/i945/early_init.c<br>+++ b/src/northbridge/intel/i945/early_init.c<br>@@ -944,9 +944,9 @@<br> <br>     i945_setup_root_complex_topology();<br> <br>-#if !CONFIG_HAVE_ACPI_RESUME<br>+#if !IS_ENABLED(CONFIG_HAVE_ACPI_RESUME)<br> #if CONFIG_DEFAULT_CONSOLE_LOGLEVEL > 8<br>-#if CONFIG_DEBUG_RAM_SETUP<br>+#if IS_ENABLED(CONFIG_DEBUG_RAM_SETUP)<br>   sdram_dump_mchbar_registers();<br> <br>     {<br>diff --git a/src/northbridge/intel/i945/raminit.c b/src/northbridge/intel/i945/raminit.c<br>index 1f07425..b4c7d13 100644<br>--- a/src/northbridge/intel/i945/raminit.c<br>+++ b/src/northbridge/intel/i945/raminit.c<br>@@ -30,7 +30,7 @@<br> #include <cbmem.h><br> <br> /* Debugging macros. */<br>-#if CONFIG_DEBUG_RAM_SETUP<br>+#if IS_ENABLED(CONFIG_DEBUG_RAM_SETUP)<br> #define PRINTK_DEBUG(x...)        printk(BIOS_DEBUG, x)<br> #else<br> #define PRINTK_DEBUG(x...)<br>@@ -93,7 +93,7 @@<br>         read32((void *)offset);<br> }<br> <br>-#if CONFIG_DEBUG_RAM_SETUP<br>+#if IS_ENABLED(CONFIG_DEBUG_RAM_SETUP)<br> void sdram_dump_mchbar_registers(void)<br> {<br>     int i;<br>@@ -1075,7 +1075,7 @@<br>         return nc;<br> }<br> <br>-#if CONFIG_NORTHBRIDGE_INTEL_SUBTYPE_I945GM<br>+#if IS_ENABLED(CONFIG_NORTHBRIDGE_INTEL_SUBTYPE_I945GM)<br> /* Strength multiplier tables */<br> static const u8 dual_channel_strength_multiplier[] = {<br>         0x44, 0x11, 0x11, 0x11, 0x44, 0x44, 0x44, 0x11,<br>@@ -1130,7 +1130,7 @@<br>        0x33, 0x00, 0x00, 0x11, 0x00, 0x44, 0x33, 0x11,<br>       0x33, 0x00, 0x11, 0x00, 0x44, 0x44, 0x33, 0x11<br> };<br>-#elif CONFIG_NORTHBRIDGE_INTEL_SUBTYPE_I945GC<br>+#elif IS_ENABLED(CONFIG_NORTHBRIDGE_INTEL_SUBTYPE_I945GC)<br> static const u8 dual_channel_strength_multiplier[] = {<br>      0x44, 0x22, 0x00, 0x00, 0x44, 0x44, 0x44, 0x22,<br>       0x44, 0x22, 0x00, 0x00, 0x44, 0x44, 0x44, 0x22,<br>@@ -2255,7 +2255,7 @@<br>        /**<br>    * We add the indices according to our clocks from CLKCFG.<br>     */<br>-#if CONFIG_NORTHBRIDGE_INTEL_SUBTYPE_I945GM<br>+#if IS_ENABLED(CONFIG_NORTHBRIDGE_INTEL_SUBTYPE_I945GM)<br>   static const u32 data_clock_crossing[] = {<br>            0x00100401, 0x00000000, /* DDR400 FSB400 */<br>           0xffffffff, 0xffffffff, /*  nonexistent  */<br>@@ -2300,7 +2300,7 @@<br>            0xffffffff, 0xffffffff, /*  nonexistent  */<br>   };<br> <br>-#elif CONFIG_NORTHBRIDGE_INTEL_SUBTYPE_I945GC<br>+#elif IS_ENABLED(CONFIG_NORTHBRIDGE_INTEL_SUBTYPE_I945GC)<br>     /* i945 G/P */<br>        static const u32 data_clock_crossing[] = {<br>            0xffffffff, 0xffffffff, /*  nonexistent  */<br>@@ -2520,7 +2520,7 @@<br>    if (sysinfo->interleaved) {<br> <br>             reg32 = MCHBAR32(DCC);<br>-#if CONFIG_CHANNEL_XOR_RANDOMIZATION<br>+#if IS_ENABLED(CONFIG_CHANNEL_XOR_RANDOMIZATION)<br>              reg32 &= ~(1 << 10);<br>                reg32 |= (1 << 9);<br> #else<br>@@ -2897,9 +2897,9 @@<br> {<br>   u8 clocks[2] = { 0, 0 };<br> <br>-#if CONFIG_NORTHBRIDGE_INTEL_SUBTYPE_I945GM<br>+#if IS_ENABLED(CONFIG_NORTHBRIDGE_INTEL_SUBTYPE_I945GM)<br> #define CLOCKS_WIDTH 2<br>-#elif CONFIG_NORTHBRIDGE_INTEL_SUBTYPE_I945GC<br>+#elif IS_ENABLED(CONFIG_NORTHBRIDGE_INTEL_SUBTYPE_I945GC)<br> #define CLOCKS_WIDTH 3<br> #endif<br>    if (sysinfo->dimm[0] != SYSINFO_DIMM_NOT_POPULATED)<br>@@ -2914,7 +2914,7 @@<br>         if (sysinfo->dimm[3] != SYSINFO_DIMM_NOT_POPULATED)<br>                clocks[1] |= ((1 << CLOCKS_WIDTH)-1) << CLOCKS_WIDTH;<br> <br>-#if CONFIG_OVERRIDE_CLOCK_DISABLE<br>+#if IS_ENABLED(CONFIG_OVERRIDE_CLOCK_DISABLE)<br>      /* Usually system firmware turns off system memory clock signals<br>       * to unused SO-DIMM slots to reduce EMI and power consumption.<br>        * However, the Kontron 986LCD-M does not like unused clock<br>diff --git a/src/northbridge/intel/i945/raminit.h b/src/northbridge/intel/i945/raminit.h<br>index 0554900..bc4491f 100644<br>--- a/src/northbridge/intel/i945/raminit.h<br>+++ b/src/northbridge/intel/i945/raminit.h<br>@@ -68,7 +68,7 @@<br> int fixup_i945_errata(void);<br> void udelay(u32 us);<br> <br>-#if CONFIG_DEBUG_RAM_SETUP<br>+#if IS_ENABLED(CONFIG_DEBUG_RAM_SETUP)<br> void sdram_dump_mchbar_registers(void);<br> #endif<br> #endif                              /* RAMINIT_H */<br>diff --git a/src/northbridge/intel/nehalem/acpi/nehalem.asl b/src/northbridge/intel/nehalem/acpi/nehalem.asl<br>index aa97a77..20165f3 100644<br>--- a/src/northbridge/intel/nehalem/acpi/nehalem.asl<br>+++ b/src/northbridge/intel/nehalem/acpi/nehalem.asl<br>@@ -33,7 +33,7 @@<br>           Memory32Fixed(ReadWrite, 0xfed40000, 0x00005000) // Misc ICH<br>          Memory32Fixed(ReadWrite, 0xfed45000, 0x0004b000) // Misc ICH<br> <br>-#if CONFIG_CHROMEOS_RAMOOPS<br>+#if IS_ENABLED(CONFIG_CHROMEOS_RAMOOPS)<br>               Memory32Fixed(ReadWrite, CONFIG_CHROMEOS_RAMOOPS_RAM_START,<br>                                    CONFIG_CHROMEOS_RAMOOPS_RAM_SIZE)<br> #endif<br>diff --git a/src/northbridge/intel/nehalem/early_init.c b/src/northbridge/intel/nehalem/early_init.c<br>index b2f4089..3f55140 100644<br>--- a/src/northbridge/intel/nehalem/early_init.c<br>+++ b/src/northbridge/intel/nehalem/early_init.c<br>@@ -72,7 +72,7 @@<br>       pci_write_config8(PCI_DEV(0xff, 0x00, 1), QPD0F1_PAM(5), 0x33);<br>       pci_write_config8(PCI_DEV(0xff, 0x00, 1), QPD0F1_PAM(6), 0x33);<br> <br>-#if CONFIG_ELOG_BOOT_COUNT<br>+#if IS_ENABLED(CONFIG_ELOG_BOOT_COUNT)<br>      /* Increment Boot Counter for non-S3 resume */<br>        if ((inw(DEFAULT_PMBASE + PM1_STS) & WAK_STS) &&<br>      ((inl(DEFAULT_PMBASE + PM1_CNT) >> 10) & 7) != SLP_TYP_S3)<br>@@ -81,7 +81,7 @@<br> <br>        printk(BIOS_DEBUG, " done.\n");<br> <br>-#if CONFIG_ELOG_BOOT_COUNT<br>+#if IS_ENABLED(CONFIG_ELOG_BOOT_COUNT)<br>    /* Increment Boot Counter except when resuming from S3 */<br>     if ((inw(DEFAULT_PMBASE + PM1_STS) & WAK_STS) &&<br>      ((inl(DEFAULT_PMBASE + PM1_CNT) >> 10) & 7) == SLP_TYP_S3)<br>diff --git a/src/northbridge/intel/nehalem/northbridge.c b/src/northbridge/intel/nehalem/northbridge.c<br>index 83c6506..b09460c 100644<br>--- a/src/northbridge/intel/nehalem/northbridge.c<br>+++ b/src/northbridge/intel/nehalem/northbridge.c<br>@@ -80,7 +80,7 @@<br>      reserved_ram_resource(dev, index++, 0xc0000 >> 10,<br>                            (0x100000 - 0xc0000) >> 10);<br> <br>-#if CONFIG_CHROMEOS_RAMOOPS<br>+#if IS_ENABLED(CONFIG_CHROMEOS_RAMOOPS)<br>   reserved_ram_resource(dev, index++,<br>                         CONFIG_CHROMEOS_RAMOOPS_RAM_START >> 10,<br>                        CONFIG_CHROMEOS_RAMOOPS_RAM_SIZE >> 10);<br>diff --git a/src/northbridge/intel/pineview/raminit.c b/src/northbridge/intel/pineview/raminit.c<br>index c811d38..8bf685d 100644<br>--- a/src/northbridge/intel/pineview/raminit.c<br>+++ b/src/northbridge/intel/pineview/raminit.c<br>@@ -28,7 +28,7 @@<br> #include <string.h><br> <br> /* Debugging macros. */<br>-#if CONFIG_DEBUG_RAM_SETUP<br>+#if IS_ENABLED(CONFIG_DEBUG_RAM_SETUP)<br> #define PRINTK_DEBUG(x...)    printk(BIOS_DEBUG, x)<br> #else<br> #define PRINTK_DEBUG(x...)<br>@@ -134,7 +134,7 @@<br>       d->tRCD = d->spd_data[29];<br>      d->tWR = d->spd_data[36];<br>       d->ranks = d->sides; // XXX<br>-#if CONFIG_DEBUG_RAM_SETUP<br>+#if IS_ENABLED(CONFIG_DEBUG_RAM_SETUP)<br>       const char *ubso[2] = { "UB", "SO" };<br> #endif<br>    PRINTK_DEBUG("%s-DIMM %d\n", &ubso[d->type][0], i);<br>@@ -318,7 +318,7 @@<br>     }<br> }<br> <br>-#if CONFIG_DEBUG_RAM_SETUP<br>+#if IS_ENABLED(CONFIG_DEBUG_RAM_SETUP)<br> static u32 fsb_reg_to_mhz(u32 speed)<br> {<br>     return (speed * 133) + 667;<br>diff --git a/src/northbridge/intel/sandybridge/acpi/sandybridge.asl b/src/northbridge/intel/sandybridge/acpi/sandybridge.asl<br>index 61537e8..609106f 100644<br>--- a/src/northbridge/intel/sandybridge/acpi/sandybridge.asl<br>+++ b/src/northbridge/intel/sandybridge/acpi/sandybridge.asl<br>@@ -33,7 +33,7 @@<br>               Memory32Fixed(ReadWrite, 0xfed40000, 0x00005000) // Misc ICH<br>          Memory32Fixed(ReadWrite, 0xfed45000, 0x0004b000) // Misc ICH<br> <br>-#if CONFIG_CHROMEOS_RAMOOPS<br>+#if IS_ENABLED(CONFIG_CHROMEOS_RAMOOPS)<br>               Memory32Fixed(ReadWrite, CONFIG_CHROMEOS_RAMOOPS_RAM_START,<br>                                    CONFIG_CHROMEOS_RAMOOPS_RAM_SIZE)<br> #endif<br>diff --git a/src/northbridge/intel/sandybridge/early_init.c b/src/northbridge/intel/sandybridge/early_init.c<br>index efe27b1..3580f35 100644<br>--- a/src/northbridge/intel/sandybridge/early_init.c<br>+++ b/src/northbridge/intel/sandybridge/early_init.c<br>@@ -60,7 +60,7 @@<br>       pci_write_config8(PCI_DEV(0, 0x00, 0), PAM5, 0x33);<br>   pci_write_config8(PCI_DEV(0, 0x00, 0), PAM6, 0x33);<br> <br>-#if CONFIG_ELOG_BOOT_COUNT<br>+#if IS_ENABLED(CONFIG_ELOG_BOOT_COUNT)<br>  /* Increment Boot Counter for non-S3 resume */<br>        if ((inw(DEFAULT_PMBASE + PM1_STS) & WAK_STS) &&<br>      ((inl(DEFAULT_PMBASE + PM1_CNT) >> 10) & 7) != SLP_TYP_S3)<br>@@ -69,7 +69,7 @@<br> <br>        printk(BIOS_DEBUG, " done.\n");<br> <br>-#if CONFIG_ELOG_BOOT_COUNT<br>+#if IS_ENABLED(CONFIG_ELOG_BOOT_COUNT)<br>    /* Increment Boot Counter except when resuming from S3 */<br>     if ((inw(DEFAULT_PMBASE + PM1_STS) & WAK_STS) &&<br>      ((inl(DEFAULT_PMBASE + PM1_CNT) >> 10) & 7) == SLP_TYP_S3)<br>diff --git a/src/northbridge/intel/sandybridge/northbridge.c b/src/northbridge/intel/sandybridge/northbridge.c<br>index 5c5f41a..51fa4fe 100644<br>--- a/src/northbridge/intel/sandybridge/northbridge.c<br>+++ b/src/northbridge/intel/sandybridge/northbridge.c<br>@@ -100,7 +100,7 @@<br>    reserved_ram_resource(dev, index++, 0xc0000 >> 10,<br>                      (0x100000 - 0xc0000) >> 10);<br> <br>-#if CONFIG_CHROMEOS_RAMOOPS<br>+#if IS_ENABLED(CONFIG_CHROMEOS_RAMOOPS)<br>         reserved_ram_resource(dev, index++,<br>                   CONFIG_CHROMEOS_RAMOOPS_RAM_START >> 10,<br>                        CONFIG_CHROMEOS_RAMOOPS_RAM_SIZE >> 10);<br>diff --git a/src/northbridge/intel/sandybridge/raminit_mrc.c b/src/northbridge/intel/sandybridge/raminit_mrc.c<br>index 09d82d6..3f7d1c6 100644<br>--- a/src/northbridge/intel/sandybridge/raminit_mrc.c<br>+++ b/src/northbridge/intel/sandybridge/raminit_mrc.c<br>@@ -39,7 +39,7 @@<br>  * MRC scrambler seed offsets should be reserved in<br>  * mainboard cmos.layout and not covered by checksum.<br>  */<br>-#if CONFIG_USE_OPTION_TABLE<br>+#if IS_ENABLED(CONFIG_USE_OPTION_TABLE)<br> #include "option_table.h"<br> #define CMOS_OFFSET_MRC_SEED     (CMOS_VSTART_mrc_scrambler_seed >> 3)<br> #define CMOS_OFFSET_MRC_SEED_S3  (CMOS_VSTART_mrc_scrambler_seed_s3 >> 3)<br>@@ -236,7 +236,7 @@<br>                die("UEFI PEI System Agent not found.\n");<br>  }<br> <br>-#if CONFIG_USBDEBUG_IN_ROMSTAGE<br>+#if IS_ENABLED(CONFIG_USBDEBUG_IN_ROMSTAGE)<br>  /* mrc.bin reconfigures USB, so reinit it to have debug */<br>    usbdebug_init();<br> #endif<br></pre><p>To view, visit <a href="https://review.coreboot.org/20346">change 20346</a>. To unsubscribe, visit <a href="https://review.coreboot.org/settings">settings</a>.</p><div itemscope itemtype="http://schema.org/EmailMessage"><div itemscope itemprop="action" itemtype="http://schema.org/ViewAction"><link itemprop="url" href="https://review.coreboot.org/20346"/><meta itemprop="name" content="View Change"/></div></div>

<div style="display:none"> Gerrit-Project: coreboot </div>
<div style="display:none"> Gerrit-Branch: master </div>
<div style="display:none"> Gerrit-MessageType: newchange </div>
<div style="display:none"> Gerrit-Change-Id: Id5bc8b75b1fa372f31982b8636f1efa4975b61a5 </div>
<div style="display:none"> Gerrit-Change-Number: 20346 </div>
<div style="display:none"> Gerrit-PatchSet: 1 </div>
<div style="display:none"> Gerrit-Owner: Martin Roth <martinroth@google.com> </div>