<p>Martin Roth has uploaded this change for <strong>review</strong>.</p><p><a href="https://review.coreboot.org/20356">View Change</a></p><pre style="font-family: monospace,monospace; white-space: pre-wrap;">src/cpu: add IS_ENABLED() around Kconfig symbol references<br><br>Some of these can be changed from #if to if(), but that will happen<br>in a follow-on commmit.<br><br>Change-Id: I4e5e585c3f98a129d89ef38b26d828d3bfeac7cf<br>Signed-off-by: Martin Roth <martinroth@google.com><br>---<br>M src/cpu/dmp/vortex86ex/biosdata_ex.S<br>M src/cpu/x86/lapic/apic_timer.c<br>M src/cpu/x86/lapic/boot_cpu.c<br>M src/cpu/x86/lapic/lapic_cpu_init.c<br>M src/cpu/x86/lapic/secondary.S<br>M src/cpu/x86/mtrr/mtrr.c<br>M src/cpu/x86/smm/smihandler.c<br>M src/cpu/x86/smm/smm_module_handler.c<br>M src/cpu/x86/smm/smmrelocate.S<br>M src/cpu/x86/tsc/delay_tsc.c<br>10 files changed, 40 insertions(+), 39 deletions(-)<br><br></pre><pre style="font-family: monospace,monospace; white-space: pre-wrap;">git pull ssh://review.coreboot.org:29418/coreboot refs/changes/56/20356/1</pre><pre style="font-family: monospace,monospace; white-space: pre-wrap;">diff --git a/src/cpu/dmp/vortex86ex/biosdata_ex.S b/src/cpu/dmp/vortex86ex/biosdata_ex.S<br>index 59d7ff1..6686bb7 100644<br>--- a/src/cpu/dmp/vortex86ex/biosdata_ex.S<br>+++ b/src/cpu/dmp/vortex86ex/biosdata_ex.S<br>@@ -38,7 +38,7 @@<br> 500/375/33 B4 53 0F 02 AF 09<br> */<br> <br>-#if CONFIG_PLL_200_200_33<br>+#if IS_ENABLED(CONFIG_PLL_200_200_33)<br> // 200/200/33 30 03 0F 02 8F 07<br> byte_fffb6 = 0x30<br> byte_fffb7 = 0x03<br>@@ -46,7 +46,7 @@<br> byte_fffbc = 0x02<br> byte_fffbe = 0xff<br> byte_fffbf = 0x07<br>-#elif CONFIG_PLL_300_300_33<br>+#elif IS_ENABLED(CONFIG_PLL_300_300_33)<br> // 300/300/33 48 03 0F 02 1F 07<br> byte_fffb6 = 0x48<br> byte_fffb7 = 0x03<br>@@ -54,7 +54,7 @@<br> byte_fffbc = 0x02<br> byte_fffbe = 0xff<br> byte_fffbf = 0x07<br>-#elif CONFIG_PLL_300_300_100<br>+#elif IS_ENABLED(CONFIG_PLL_300_300_100)<br> // 300/300/100 48 03 23 02 7F 07<br> byte_fffb6 = 0x48<br> byte_fffb7 = 0x03<br>@@ -62,7 +62,7 @@<br> byte_fffbc = 0x02<br> byte_fffbe = 0xff<br> byte_fffbf = 0x07<br>-#elif CONFIG_PLL_400_200_33<br>+#elif IS_ENABLED(CONFIG_PLL_400_200_33)<br> // 400/200/33 60 43 0F 02 3F 07 ; without 200MHz timing, so set 300MHz timing<br> byte_fffb6 = 0x60<br> byte_fffb7 = 0x43<br>@@ -70,7 +70,7 @@<br> byte_fffbc = 0x02<br> byte_fffbe = 0xff<br> byte_fffbf = 0x07<br>-#elif CONFIG_PLL_400_200_100<br>+#elif IS_ENABLED(CONFIG_PLL_400_200_100)<br> // 400/200/100 60 43 23 02 4F 07<br> byte_fffb6 = 0x60<br> byte_fffb7 = 0x43<br>@@ -78,7 +78,7 @@<br> byte_fffbc = 0x02<br> byte_fffbe = 0xff<br> byte_fffbf = 0x07<br>-#elif CONFIG_PLL_400_400_33<br>+#elif IS_ENABLED(CONFIG_PLL_400_400_33)<br> // 400/400/33 60 03 0F 02 BF 09<br> byte_fffb6 = 0x60<br> byte_fffb7 = 0x03<br>@@ -86,7 +86,7 @@<br> byte_fffbc = 0x02<br> byte_fffbe = 0xff<br> byte_fffbf = 0x09<br>-#elif CONFIG_PLL_500_250_33<br>+#elif IS_ENABLED(CONFIG_PLL_500_250_33)<br> // 500/250/33 50 42 0F 02 DF 07<br> byte_fffb6 = 0x50<br> byte_fffb7 = 0x42<br>@@ -94,7 +94,7 @@<br> byte_fffbc = 0x02<br> byte_fffbe = 0xff<br> byte_fffbf = 0x07<br>-#elif CONFIG_PLL_500_500_33<br>+#elif IS_ENABLED(CONFIG_PLL_500_500_33)<br> // 500/500/33 78 03 0F 02 4F 09<br> byte_fffb6 = 0x78<br> byte_fffb7 = 0x03<br>@@ -102,7 +102,7 @@<br> byte_fffbc = 0x02<br> byte_fffbe = 0xff<br> byte_fffbf = 0x09<br>-#elif CONFIG_PLL_400_300_33<br>+#elif IS_ENABLED(CONFIG_PLL_400_300_33)<br> // 400/300/33 90 53 0F 02 3F 07<br> byte_fffb6 = 0x90<br> byte_fffb7 = 0x53<br>@@ -110,7 +110,7 @@<br> byte_fffbc = 0x02<br> byte_fffbe = 0xff<br> byte_fffbf = 0x07<br>-#elif CONFIG_PLL_400_300_100<br>+#elif IS_ENABLED(CONFIG_PLL_400_300_100)<br> // 400/300/100 90 53 23 02 9F 07<br> byte_fffb6 = 0x90<br> byte_fffb7 = 0x53<br>@@ -118,7 +118,7 @@<br> byte_fffbc = 0x02<br> byte_fffbe = 0xff<br> byte_fffbf = 0x07<br>-#elif CONFIG_PLL_444_333_33<br>+#elif IS_ENABLED(CONFIG_PLL_444_333_33)<br> // 444/333/33 A0 53 0F 02 5F 08<br> byte_fffb6 = 0xa0<br> byte_fffb7 = 0x53<br>@@ -126,7 +126,7 @@<br> byte_fffbc = 0x02<br> byte_fffbe = 0xff<br> byte_fffbf = 0x08<br>-#elif CONFIG_PLL_466_350_33<br>+#elif IS_ENABLED(CONFIG_PLL_466_350_33)<br> // 466/350/33 A8 53 0F 02 DF 09<br> byte_fffb6 = 0xa8<br> byte_fffb7 = 0x53<br>@@ -134,7 +134,7 @@<br> byte_fffbc = 0x02<br> byte_fffbe = 0xff<br> byte_fffbf = 0x09<br>-#elif CONFIG_PLL_500_375_33<br>+#elif IS_ENABLED(CONFIG_PLL_500_375_33)<br> // 500/375/33 B4 53 0F 02 AF 09<br> byte_fffb6 = 0xb4<br> byte_fffb7 = 0x53<br>diff --git a/src/cpu/x86/lapic/apic_timer.c b/src/cpu/x86/lapic/apic_timer.c<br>index cddc5ad..254bb07 100644<br>--- a/src/cpu/x86/lapic/apic_timer.c<br>+++ b/src/cpu/x86/lapic/apic_timer.c<br>@@ -29,7 +29,7 @@<br> * memory init.<br> */<br> <br>-#if CONFIG_UDELAY_LAPIC_FIXED_FSB<br>+#if CONFIG_UDELAY_LAPIC_FIXED_FSB != 0<br> static inline u32 get_timer_fsb(void)<br> {<br> return CONFIG_UDELAY_LAPIC_FIXED_FSB;<br>@@ -136,7 +136,7 @@<br> } while ((start - value) < ticks);<br> }<br> <br>-#if CONFIG_LAPIC_MONOTONIC_TIMER && !defined(__PRE_RAM__)<br>+#if IS_ENABLED(CONFIG_LAPIC_MONOTONIC_TIMER) && !defined(__PRE_RAM__)<br> #include <timer.h><br> <br> static struct monotonic_counter {<br>diff --git a/src/cpu/x86/lapic/boot_cpu.c b/src/cpu/x86/lapic/boot_cpu.c<br>index 2942ff6..7ba21fe 100644<br>--- a/src/cpu/x86/lapic/boot_cpu.c<br>+++ b/src/cpu/x86/lapic/boot_cpu.c<br>@@ -14,7 +14,7 @@<br> #include <smp/node.h><br> #include <cpu/x86/msr.h><br> <br>-#if CONFIG_SMP<br>+#if IS_ENABLED(CONFIG_SMP)<br> int boot_cpu(void)<br> {<br> int bsp;<br>diff --git a/src/cpu/x86/lapic/lapic_cpu_init.c b/src/cpu/x86/lapic/lapic_cpu_init.c<br>index 427e537..83be53b 100644<br>--- a/src/cpu/x86/lapic/lapic_cpu_init.c<br>+++ b/src/cpu/x86/lapic/lapic_cpu_init.c<br>@@ -36,7 +36,7 @@<br> #include <cpu/intel/speedstep.h><br> #include <thread.h><br> <br>-#if CONFIG_SMP && CONFIG_MAX_CPUS > 1<br>+#if IS_ENABLED(CONFIG_SMP) && CONFIG_MAX_CPUS > 1<br> /* This is a lot more paranoid now, since Linux can NOT handle<br> * being told there is a CPU when none exists. So any errors<br> * will return 0, meaning no CPU.<br>@@ -148,8 +148,9 @@<br> }<br> return 0;<br> }<br>-#if !CONFIG_CPU_AMD_MODEL_10XXX && !CONFIG_CPU_INTEL_MODEL_206AX \<br>- && !CONFIG_CPU_INTEL_MODEL_2065X<br>+#if !IS_ENABLED(CONFIG_CPU_AMD_MODEL_10XXX) \<br>+ && !IS_ENABLED(CONFIG_CPU_INTEL_MODEL_206AX) \<br>+ && !IS_ENABLED(CONFIG_CPU_INTEL_MODEL_2065X)<br> mdelay(10);<br> #endif<br> <br>@@ -324,7 +325,7 @@<br> return result;<br> }<br> <br>-#if CONFIG_AP_IN_SIPI_WAIT<br>+#if IS_ENABLED(CONFIG_AP_IN_SIPI_WAIT)<br> <br> /**<br> * Sending INIT IPI to self is equivalent of asserting #INIT with a bit of<br>@@ -556,17 +557,17 @@<br> /* Find the device structure for the boot CPU */<br> info->cpu = alloc_find_dev(cpu_bus, &cpu_path);<br> <br>-#if CONFIG_SMP && CONFIG_MAX_CPUS > 1<br>+#if IS_ENABLED(CONFIG_SMP) && CONFIG_MAX_CPUS > 1<br> // why here? In case some day we can start core1 in amd_sibling_init<br> copy_secondary_start_to_lowest_1M();<br> #endif<br> <br>-#if CONFIG_HAVE_SMI_HANDLER<br>+#if IS_ENABLED(CONFIG_HAVE_SMI_HANDLER)<br> if (!IS_ENABLED(CONFIG_SERIALIZED_SMM_INITIALIZATION))<br> smm_init();<br> #endif<br> <br>-#if CONFIG_SMP && CONFIG_MAX_CPUS > 1<br>+#if IS_ENABLED(CONFIG_SMP) && CONFIG_MAX_CPUS > 1<br> /* start all aps at first, so we can init ECC all together */<br> if (IS_ENABLED(CONFIG_PARALLEL_CPU_INIT))<br> start_other_cpus(cpu_bus, info->cpu);<br>@@ -575,7 +576,7 @@<br> /* Initialize the bootstrap processor */<br> cpu_initialize(0);<br> <br>-#if CONFIG_SMP && CONFIG_MAX_CPUS > 1<br>+#if IS_ENABLED(CONFIG_SMP) && CONFIG_MAX_CPUS > 1<br> if (!IS_ENABLED(CONFIG_PARALLEL_CPU_INIT))<br> start_other_cpus(cpu_bus, info->cpu);<br> <br>@@ -588,13 +589,13 @@<br> * smm_init() will queue a pending SMI on all cpus<br> * and smm_other_cpus() will start them one by one */<br> smm_init();<br>-#if CONFIG_SMP && CONFIG_MAX_CPUS > 1<br>+#if IS_ENABLED(CONFIG_SMP) && CONFIG_MAX_CPUS > 1<br> last_cpu_index = 0;<br> smm_other_cpus(cpu_bus, info->cpu);<br> #endif<br> }<br> <br>-#if CONFIG_SMP && CONFIG_MAX_CPUS > 1<br>+#if IS_ENABLED(CONFIG_SMP) && CONFIG_MAX_CPUS > 1<br> recover_lowest_1M();<br> #endif<br> }<br>diff --git a/src/cpu/x86/lapic/secondary.S b/src/cpu/x86/lapic/secondary.S<br>index 0c4c0d0..a36502b 100644<br>--- a/src/cpu/x86/lapic/secondary.S<br>+++ b/src/cpu/x86/lapic/secondary.S<br>@@ -14,7 +14,7 @@<br> #include <cpu/x86/mtrr.h><br> #include <cpu/x86/lapic_def.h><br> <br>-#if CONFIG_SMP && CONFIG_MAX_CPUS > 1<br>+#if IS_ENABLED(CONFIG_SMP) && CONFIG_MAX_CPUS > 1<br> .text<br> .globl _secondary_start, _secondary_start_end, _secondary_gdt_addr<br> .balign 4096<br>diff --git a/src/cpu/x86/mtrr/mtrr.c b/src/cpu/x86/mtrr/mtrr.c<br>index 609d1e7..ef1bb31 100644<br>--- a/src/cpu/x86/mtrr/mtrr.c<br>+++ b/src/cpu/x86/mtrr/mtrr.c<br>@@ -36,7 +36,7 @@<br> #include <arch/cpu.h><br> #include <arch/acpi.h><br> #include <memrange.h><br>-#if CONFIG_X86_AMD_FIXED_MTRRS<br>+#if IS_ENABLED(CONFIG_X86_AMD_FIXED_MTRRS)<br> #include <cpu/amd/mtrr.h><br> #define MTRR_FIXED_WRBACK_BITS (MTRR_READ_MEM | MTRR_WRITE_MEM)<br> #else<br>diff --git a/src/cpu/x86/smm/smihandler.c b/src/cpu/x86/smm/smihandler.c<br>index 16415ba..089456e 100644<br>--- a/src/cpu/x86/smm/smihandler.c<br>+++ b/src/cpu/x86/smm/smihandler.c<br>@@ -19,7 +19,7 @@<br> #include <cpu/x86/cache.h><br> #include <cpu/x86/smm.h><br> <br>-#if CONFIG_SPI_FLASH_SMM<br>+#if IS_ENABLED(CONFIG_SPI_FLASH_SMM)<br> #include <spi-generic.h><br> #endif<br> <br>@@ -185,7 +185,7 @@<br> <br> /* Allow drivers to initialize variables in SMM context. */<br> if (do_driver_init) {<br>-#if CONFIG_SPI_FLASH_SMM<br>+#if IS_ENABLED(CONFIG_SPI_FLASH_SMM)<br> spi_init();<br> #endif<br> do_driver_init = 0;<br>diff --git a/src/cpu/x86/smm/smm_module_handler.c b/src/cpu/x86/smm/smm_module_handler.c<br>index 4bcd853..95f63a3 100644<br>--- a/src/cpu/x86/smm/smm_module_handler.c<br>+++ b/src/cpu/x86/smm/smm_module_handler.c<br>@@ -18,7 +18,7 @@<br> #include <cpu/x86/smm.h><br> #include <rmodule.h><br> <br>-#if CONFIG_SPI_FLASH_SMM<br>+#if IS_ENABLED(CONFIG_SPI_FLASH_SMM)<br> #include <spi-generic.h><br> #endif<br> <br>@@ -158,7 +158,7 @@<br> <br> /* Allow drivers to initialize variables in SMM context. */<br> if (do_driver_init) {<br>-#if CONFIG_SPI_FLASH_SMM<br>+#if IS_ENABLED(CONFIG_SPI_FLASH_SMM)<br> spi_init();<br> #endif<br> do_driver_init = 0;<br>diff --git a/src/cpu/x86/smm/smmrelocate.S b/src/cpu/x86/smm/smmrelocate.S<br>index 2fe0156..2a950f3 100644<br>--- a/src/cpu/x86/smm/smmrelocate.S<br>+++ b/src/cpu/x86/smm/smmrelocate.S<br>@@ -21,19 +21,19 @@<br> // can it be cleaned up so this include is not required?<br> // It's needed right now because we get our DEFAULT_PMBASE from<br> // here.<br>-#if CONFIG_SOUTHBRIDGE_INTEL_I82801GX<br>+#if IS_ENABLED(CONFIG_SOUTHBRIDGE_INTEL_I82801GX)<br> #include "../../../southbridge/intel/i82801gx/i82801gx.h"<br>-#elif CONFIG_SOUTHBRIDGE_INTEL_I82801DX<br>+#elif IS_ENABLED(CONFIG_SOUTHBRIDGE_INTEL_I82801DX)<br> #include "../../../southbridge/intel/i82801dx/i82801dx.h"<br>-#elif CONFIG_SOC_INTEL_SCH<br>+#elif IS_ENABLED(CONFIG_SOC_INTEL_SCH)<br> #include "../../../soc/intel/sch/sch.h"<br>-#elif CONFIG_SOUTHBRIDGE_INTEL_I82801IX<br>+#elif IS_ENABLED(CONFIG_SOUTHBRIDGE_INTEL_I82801IX)<br> #include "../../../southbridge/intel/i82801ix/i82801ix.h"<br> #else<br> #error "Southbridge needs SMM handler support."<br> #endif<br> <br>-#if CONFIG_SMM_TSEG<br>+#if IS_ENABLED(CONFIG_SMM_TSEG)<br> #error "Don't use this file with TSEG."<br> <br> #endif /* CONFIG_SMM_TSEG */<br>@@ -155,7 +155,7 @@<br> <br> /* End of southbridge specific section. */<br> <br>-#if CONFIG_DEBUG_SMM_RELOCATION<br>+#if IS_ENABLED(CONFIG_DEBUG_SMM_RELOCATION)<br> /* print [SMM-x] so we can determine if CPUx went to SMM */<br> movw $CONFIG_TTYS0_BASE, %dx<br> mov $'[', %al<br>diff --git a/src/cpu/x86/tsc/delay_tsc.c b/src/cpu/x86/tsc/delay_tsc.c<br>index b2e20f4..ec2f1d7 100644<br>--- a/src/cpu/x86/tsc/delay_tsc.c<br>+++ b/src/cpu/x86/tsc/delay_tsc.c<br>@@ -136,7 +136,7 @@<br> }<br> }<br> <br>-#if CONFIG_TSC_MONOTONIC_TIMER<br>+#if IS_ENABLED(CONFIG_TSC_MONOTONIC_TIMER)<br> #include <timer.h><br> <br> static struct monotonic_counter {<br></pre><p>To view, visit <a href="https://review.coreboot.org/20356">change 20356</a>. To unsubscribe, visit <a href="https://review.coreboot.org/settings">settings</a>.</p><div itemscope itemtype="http://schema.org/EmailMessage"><div itemscope itemprop="action" itemtype="http://schema.org/ViewAction"><link itemprop="url" href="https://review.coreboot.org/20356"/><meta itemprop="name" content="View Change"/></div></div>
<div style="display:none"> Gerrit-Project: coreboot </div>
<div style="display:none"> Gerrit-Branch: master </div>
<div style="display:none"> Gerrit-MessageType: newchange </div>
<div style="display:none"> Gerrit-Change-Id: I4e5e585c3f98a129d89ef38b26d828d3bfeac7cf </div>
<div style="display:none"> Gerrit-Change-Number: 20356 </div>
<div style="display:none"> Gerrit-PatchSet: 1 </div>
<div style="display:none"> Gerrit-Owner: Martin Roth <martinroth@google.com> </div>