<p>Martin Roth has uploaded this change for <strong>review</strong>.</p><p><a href="https://review.coreboot.org/20349">View Change</a></p><pre style="font-family: monospace,monospace; white-space: pre-wrap;">southbridge/amd: add IS_ENABLED() around Kconfig symbol references<br><br>Change-Id: I8fabb7331435eb518a5c95cb29c4ff5ca98560d2<br>Signed-off-by: Martin Roth <martinroth@google.com><br>---<br>M src/southbridge/amd/agesa/hudson/acpi/fch.asl<br>M src/southbridge/amd/agesa/hudson/acpi/usb.asl<br>M src/southbridge/amd/agesa/hudson/fadt.c<br>M src/southbridge/amd/agesa/hudson/hudson.c<br>M src/southbridge/amd/agesa/hudson/imc.c<br>M src/southbridge/amd/agesa/hudson/spi.c<br>M src/southbridge/amd/amd8111/acpi.c<br>M src/southbridge/amd/amd8111/lpc.c<br>M src/southbridge/amd/cimx/sb700/Platform.h<br>M src/southbridge/amd/cimx/sb800/SBPLATFORM.h<br>M src/southbridge/amd/cimx/sb800/bootblock.c<br>M src/southbridge/amd/cimx/sb800/late.c<br>M src/southbridge/amd/cimx/sb900/early.c<br>M src/southbridge/amd/cs5536/early_setup.c<br>M src/southbridge/amd/cs5536/pirq.c<br>M src/southbridge/amd/pi/hudson/acpi/fch.asl<br>M src/southbridge/amd/pi/hudson/acpi/sleepstates.asl<br>M src/southbridge/amd/pi/hudson/acpi/usb.asl<br>M src/southbridge/amd/pi/hudson/fadt.c<br>M src/southbridge/amd/rs690/cmn.c<br>M src/southbridge/amd/rs690/ht.c<br>M src/southbridge/amd/rs780/cmn.c<br>M src/southbridge/amd/rs780/early_setup.c<br>M src/southbridge/amd/rs780/gfx.c<br>M src/southbridge/amd/rs780/rs780.c<br>M src/southbridge/amd/sb700/early_setup.c<br>M src/southbridge/amd/sb700/lpc.c<br>M src/southbridge/amd/sb700/sata.c<br>M src/southbridge/amd/sb700/sb700.c<br>M src/southbridge/amd/sb700/usb.c<br>M src/southbridge/amd/sr5650/early_setup.c<br>31 files changed, 60 insertions(+), 57 deletions(-)<br><br></pre><pre style="font-family: monospace,monospace; white-space: pre-wrap;">git pull ssh://review.coreboot.org:29418/coreboot refs/changes/49/20349/1</pre><pre style="font-family: monospace,monospace; white-space: pre-wrap;">diff --git a/src/southbridge/amd/agesa/hudson/acpi/fch.asl b/src/southbridge/amd/agesa/hudson/acpi/fch.asl<br>index 7b0232a..bc9e4c1 100644<br>--- a/src/southbridge/amd/agesa/hudson/acpi/fch.asl<br>+++ b/src/southbridge/amd/agesa/hudson/acpi/fch.asl<br>@@ -62,7 +62,7 @@<br> Name(_ADR, 0x00140007)<br> } /* end SDCN */<br> <br>-#if !CONFIG_SOUTHBRIDGE_AMD_AGESA_YANGTZE<br>+#if !IS_ENABLED(CONFIG_SOUTHBRIDGE_AMD_AGESA_YANGTZE)<br> <br> /* 0:14.4 - PCI slot 1, 2, 3 */<br> Device(PIBR) {<br>@@ -175,7 +175,7 @@<br> /* Determine the OS we're running on */<br> OSFL()<br> <br>-#if defined(CONFIG_HUDSON_IMC_FWM) && CONFIG_HUDSON_IMC_FWM<br>+#if IS_ENABLED(CONFIG_HUDSON_IMC_FWM) && IS_ENABLED(CONFIG_HUDSON_IMC_FWM)<br> #include "acpi/AmdImc.asl" /* Hudson IMC function */<br> ITZE() /* enable IMC Fan Control*/<br> #endif<br>diff --git a/src/southbridge/amd/agesa/hudson/acpi/usb.asl b/src/southbridge/amd/agesa/hudson/acpi/usb.asl<br>index 0794bf3..d83b935 100644<br>--- a/src/southbridge/amd/agesa/hudson/acpi/usb.asl<br>+++ b/src/southbridge/amd/agesa/hudson/acpi/usb.asl<br>@@ -50,7 +50,7 @@<br> Name(_PRW, Package() {0x0B, 3})<br> } /* end UOH5 */<br> <br>-#if !CONFIG_SOUTHBRIDGE_AMD_AGESA_YANGTZE<br>+#if !IS_ENABLED(CONFIG_SOUTHBRIDGE_AMD_AGESA_YANGTZE)<br> /* 0:14.5 - OHCI */<br> Device(UEH1) {<br> Name(_ADR, 0x00140005)<br>@@ -64,7 +64,7 @@<br> Name(_PRW, Package() {0x0B, 4})<br> } /* end XHC0 */<br> <br>-#if !CONFIG_SOUTHBRIDGE_AMD_AGESA_YANGTZE<br>+#if !IS_ENABLED(CONFIG_SOUTHBRIDGE_AMD_AGESA_YANGTZE)<br> /* 0:10.1 - XHCI 1*/<br> Device(XHC1) {<br> Name(_ADR, 0x00100001)<br>diff --git a/src/southbridge/amd/agesa/hudson/fadt.c b/src/southbridge/amd/agesa/hudson/fadt.c<br>index 276ded2..c1d9b72 100644<br>--- a/src/southbridge/amd/agesa/hudson/fadt.c<br>+++ b/src/southbridge/amd/agesa/hudson/fadt.c<br>@@ -25,7 +25,7 @@<br> #include "hudson.h"<br> #include "smi.h"<br> <br>-#if CONFIG_HUDSON_LEGACY_FREE<br>+#if IS_ENABLED(CONFIG_HUDSON_LEGACY_FREE)<br> #define FADT_BOOT_ARCH ACPI_FADT_LEGACY_FREE<br> #else<br> #define FADT_BOOT_ARCH (ACPI_FADT_LEGACY_DEVICES | ACPI_FADT_8042)<br>diff --git a/src/southbridge/amd/agesa/hudson/hudson.c b/src/southbridge/amd/agesa/hudson/hudson.c<br>index 20af2e7..101f5d4 100644<br>--- a/src/southbridge/amd/agesa/hudson/hudson.c<br>+++ b/src/southbridge/amd/agesa/hudson/hudson.c<br>@@ -181,7 +181,7 @@<br> <br> static void hudson_final(void *chip_info)<br> {<br>-#if !CONFIG_ACPI_ENABLE_THERMAL_ZONE<br>+#if !IS_ENABLED(CONFIG_ACPI_ENABLE_THERMAL_ZONE)<br> #if IS_ENABLED(CONFIG_HUDSON_IMC_FWM)<br> /* AMD AGESA does not enable thermal zone, so we enable it here. */<br> enable_imc_thermal_zone();<br>diff --git a/src/southbridge/amd/agesa/hudson/imc.c b/src/southbridge/amd/agesa/hudson/imc.c<br>index 049eca95..799cc32 100644<br>--- a/src/southbridge/amd/agesa/hudson/imc.c<br>+++ b/src/southbridge/amd/agesa/hudson/imc.c<br>@@ -35,7 +35,7 @@<br> write8(VACPI_MMIO_VBASE + PMIO2_BASE + 0x03, 0xff);<br> write8(VACPI_MMIO_VBASE + PMIO2_BASE + 0x04, 0xff);<br> <br>-#if !CONFIG_SOUTHBRIDGE_AMD_AGESA_YANGTZE<br>+#if !IS_ENABLED(CONFIG_SOUTHBRIDGE_AMD_AGESA_YANGTZE)<br> write8(VACPI_MMIO_VBASE + PMIO2_BASE + 0x10, 0x06);<br> write8(VACPI_MMIO_VBASE + PMIO2_BASE + 0x11, 0x06);<br> write8(VACPI_MMIO_VBASE + PMIO2_BASE + 0x12, 0xf7);<br>@@ -43,7 +43,7 @@<br> write8(VACPI_MMIO_VBASE + PMIO2_BASE + 0x14, 0xff);<br> #endif<br> <br>-#if CONFIG_SOUTHBRIDGE_AMD_AGESA_YANGTZE<br>+#if IS_ENABLED(CONFIG_SOUTHBRIDGE_AMD_AGESA_YANGTZE)<br> UINT8 PciData;<br> PCI_ADDR PciAddress;<br> AMD_CONFIG_PARAMS StdHeader;<br>diff --git a/src/southbridge/amd/agesa/hudson/spi.c b/src/southbridge/amd/agesa/hudson/spi.c<br>index 71fddc6..46121db 100644<br>--- a/src/southbridge/amd/agesa/hudson/spi.c<br>+++ b/src/southbridge/amd/agesa/hudson/spi.c<br>@@ -110,7 +110,7 @@<br> <br> readoffby1 = bytesout ? 0 : 1;<br> <br>-#if CONFIG_SOUTHBRIDGE_AMD_AGESA_YANGTZE<br>+#if IS_ENABLED(CONFIG_SOUTHBRIDGE_AMD_AGESA_YANGTZE)<br> spi_write(0x1E, 5);<br> spi_write(0x1F, bytesout); /* SpiExtRegIndx [5] - TxByteCount */<br> spi_write(0x1E, 6);<br>diff --git a/src/southbridge/amd/amd8111/acpi.c b/src/southbridge/amd/amd8111/acpi.c<br>index 2a6cf8d..fd3fe49 100644<br>--- a/src/southbridge/amd/amd8111/acpi.c<br>+++ b/src/southbridge/amd/amd8111/acpi.c<br>@@ -89,7 +89,7 @@<br> }<br> <br> <br>-#if CONFIG_HAVE_ACPI_TABLES<br>+#if IS_ENABLED(CONFIG_HAVE_ACPI_TABLES)<br> unsigned pm_base;<br> #endif<br> <br>@@ -161,7 +161,7 @@<br> (on*12)+(on>>1),(on&1)*5);<br> }<br> <br>-#if CONFIG_HAVE_ACPI_TABLES<br>+#if IS_ENABLED(CONFIG_HAVE_ACPI_TABLES)<br> pm_base = pci_read_config16(dev, 0x58) & 0xff00;<br> printk(BIOS_DEBUG, "pm_base: 0x%04x\n",pm_base);<br> #endif<br>diff --git a/src/southbridge/amd/amd8111/lpc.c b/src/southbridge/amd/amd8111/lpc.c<br>index 8841760..00c56f6 100644<br>--- a/src/southbridge/amd/amd8111/lpc.c<br>+++ b/src/southbridge/amd/amd8111/lpc.c<br>@@ -129,7 +129,7 @@<br> }<br> <br> static void southbridge_acpi_fill_ssdt_generator(device_t device) {<br>-#if CONFIG_SET_FIDVID<br>+#if IS_ENABLED(CONFIG_SET_FIDVID)<br> amd_generate_powernow(pm_base + 0x10, 6, 1);<br> acpigen_write_mainboard_resources("\\_SB.PCI0.MBRS", "_CRS");<br> #endif<br>diff --git a/src/southbridge/amd/cimx/sb700/Platform.h b/src/southbridge/amd/cimx/sb700/Platform.h<br>index 7476cb9..08cff4a 100644<br>--- a/src/southbridge/amd/cimx/sb700/Platform.h<br>+++ b/src/southbridge/amd/cimx/sb700/Platform.h<br>@@ -59,7 +59,7 @@<br> #ifdef TRACE<br> #undef TRACE<br> #endif<br>- #if CONFIG_REDIRECT_SBCIMX_TRACE_TO_SERIAL<br>+ #if IS_ENABLED(CONFIG_REDIRECT_SBCIMX_TRACE_TO_SERIAL)<br> #define TRACE(Arguments) printk Arguments<br> #else<br> #define TRACE(Arguments) do {} while (0)<br>diff --git a/src/southbridge/amd/cimx/sb800/SBPLATFORM.h b/src/southbridge/amd/cimx/sb800/SBPLATFORM.h<br>index c933207..7d3c7de 100644<br>--- a/src/southbridge/amd/cimx/sb800/SBPLATFORM.h<br>+++ b/src/southbridge/amd/cimx/sb800/SBPLATFORM.h<br>@@ -49,7 +49,7 @@<br> #endif<br> #define FIXUP_PTR(ptr) ptr<br> <br>-#if CONFIG_SB800_IMC_FWM<br>+#if IS_ENABLED(CONFIG_SB800_IMC_FWM)<br> #define IMC_ENABLE_OVER_WRITE 0x01<br> #endif<br> <br>@@ -154,7 +154,7 @@<br> <br> #include "vendorcode/amd/cimx/sb800/AMDSBLIB.h"<br> <br>-#if CONFIG_HAVE_ACPI_RESUME<br>+#if IS_ENABLED(CONFIG_HAVE_ACPI_RESUME)<br> #include <spi-generic.h><br> #endif<br> <br>diff --git a/src/southbridge/amd/cimx/sb800/bootblock.c b/src/southbridge/amd/cimx/sb800/bootblock.c<br>index 008a19b..585d5a8 100644<br>--- a/src/southbridge/amd/cimx/sb800/bootblock.c<br>+++ b/src/southbridge/amd/cimx/sb800/bootblock.c<br>@@ -99,7 +99,7 @@<br> // change twice.<br> reg32 = *acpi_mmio;<br> reg32 &= ~((1 << 2) | (3 << 0)); // enable, 14 MHz (power up default)<br>-#if !CONFIG_SUPERIO_WANTS_14MHZ_CLOCK<br>+#if !IS_ENABLED(CONFIG_SUPERIO_WANTS_14MHZ_CLOCK)<br> reg32 |= 2 << 0; // Device_CLK1_sel = 48 MHz<br> #endif<br> *acpi_mmio = reg32;<br>diff --git a/src/southbridge/amd/cimx/sb800/late.c b/src/southbridge/amd/cimx/sb800/late.c<br>index f4b1769..6b3af0e 100644<br>--- a/src/southbridge/amd/cimx/sb800/late.c<br>+++ b/src/southbridge/amd/cimx/sb800/late.c<br>@@ -372,7 +372,7 @@<br> <br> case (0x14 << 3) | 0: /* 0:14:0 SMBUS */<br> clear_ioapic(VIO_APIC_VADDR);<br>-#if CONFIG_CPU_AMD_AGESA<br>+#if IS_ENABLED(CONFIG_CPU_AMD_AGESA)<br> /* Assign the ioapic ID the next available number after the processor core local APIC IDs */<br> setup_ioapic(VIO_APIC_VADDR, CONFIG_MAX_CPUS);<br> #else<br>@@ -406,9 +406,9 @@<br> <br> case (0x14 << 3) | 3: /* 0:14:3 LPC */<br> /* Initialize the fans */<br>-#if CONFIG_SB800_IMC_FAN_CONTROL<br>+#if IS_ENABLED(CONFIG_SB800_IMC_FAN_CONTROL)<br> init_sb800_IMC_fans(dev);<br>-#elif CONFIG_SB800_MANUAL_FAN_CONTROL<br>+#elif IS_ENABLED(CONFIG_SB800_MANUAL_FAN_CONTROL)<br> init_sb800_MANUAL_fans(dev);<br> #endif<br> break;<br>diff --git a/src/southbridge/amd/cimx/sb900/early.c b/src/southbridge/amd/cimx/sb900/early.c<br>index bee7d74..1f787f9 100644<br>--- a/src/southbridge/amd/cimx/sb900/early.c<br>+++ b/src/southbridge/amd/cimx/sb900/early.c<br>@@ -96,7 +96,7 @@<br> <br> void sb_After_Pci_Init(void)<br> {<br>-#if !CONFIG_BOARD_AMD_DINAR<br>+#if !IS_ENABLED(CONFIG_BOARD_AMD_DINAR)<br> AMDSBCFG sb_early_cfg;<br> <br> printk(BIOS_SPEW, "SB900 - Early.c - sb_After_Pci_Init - Start.\n");<br>@@ -128,7 +128,7 @@<br> <br> void sb_Late_Post(void)<br> {<br>-#if !CONFIG_BOARD_AMD_DINAR<br>+#if !IS_ENABLED(CONFIG_BOARD_AMD_DINAR)<br> AMDSBCFG sb_early_cfg;<br> u8 data;<br> <br>diff --git a/src/southbridge/amd/cs5536/early_setup.c b/src/southbridge/amd/cs5536/early_setup.c<br>index 013607b..6c69222 100644<br>--- a/src/southbridge/amd/cs5536/early_setup.c<br>+++ b/src/southbridge/amd/cs5536/early_setup.c<br>@@ -88,7 +88,7 @@<br> <br> static void cs5536_setup_power_button(void)<br> {<br>-#if CONFIG_ENABLE_POWER_BUTTON<br>+#if IS_ENABLED(CONFIG_ENABLE_POWER_BUTTON)<br> outl(0x40020000, PMS_IO_BASE + 0x40);<br> #endif<br> <br>diff --git a/src/southbridge/amd/cs5536/pirq.c b/src/southbridge/amd/cs5536/pirq.c<br>index 0352dbc..466a2dc 100644<br>--- a/src/southbridge/amd/cs5536/pirq.c<br>+++ b/src/southbridge/amd/cs5536/pirq.c<br>@@ -19,7 +19,7 @@<br> #include <device/pci.h><br> #include <device/pci_ids.h><br> <br>-#if (CONFIG_PIRQ_ROUTE == 1 && CONFIG_GENERATE_PIRQ_TABLE == 1)<br>+#if IS_ENABLED(CONFIG_PIRQ_ROUTE) && IS_ENABLED(CONFIG_GENERATE_PIRQ_TABLE)<br> void pirq_assign_irqs(const unsigned char pIntAtoD[4])<br> {<br> device_t pdev;<br>diff --git a/src/southbridge/amd/pi/hudson/acpi/fch.asl b/src/southbridge/amd/pi/hudson/acpi/fch.asl<br>index b8c0b35..5f00436 100644<br>--- a/src/southbridge/amd/pi/hudson/acpi/fch.asl<br>+++ b/src/southbridge/amd/pi/hudson/acpi/fch.asl<br>@@ -51,7 +51,7 @@<br> #include "usb.asl"<br> <br> /* 0:14.2 - HD Audio */<br>-#if !CONFIG_SOUTHBRIDGE_AMD_PI_KERN<br>+#if !IS_ENABLED(CONFIG_SOUTHBRIDGE_AMD_PI_KERN)<br> #include "audio.asl"<br> #endif<br> <br>diff --git a/src/southbridge/amd/pi/hudson/acpi/sleepstates.asl b/src/southbridge/amd/pi/hudson/acpi/sleepstates.asl<br>index d93f068..c8ad520 100644<br>--- a/src/southbridge/amd/pi/hudson/acpi/sleepstates.asl<br>+++ b/src/southbridge/amd/pi/hudson/acpi/sleepstates.asl<br>@@ -23,7 +23,7 @@<br> If (LAnd(SSFG, 0x02)) {<br> Name(\_S2, Package () {0x02, 0x02, 0x00, 0x00} ) /* (S2) - "light" Suspend to RAM */<br> }<br>-#if CONFIG_HAVE_ACPI_RESUME<br>+#if IS_ENABLED(CONFIG_HAVE_ACPI_RESUME)<br> If (LAnd(SSFG, 0x04)) {<br> Name(\_S3, Package () {0x03, 0x03, 0x00, 0x00} ) /* (S3) - Suspend to RAM */<br> }<br>diff --git a/src/southbridge/amd/pi/hudson/acpi/usb.asl b/src/southbridge/amd/pi/hudson/acpi/usb.asl<br>index 1989017..26192af 100644<br>--- a/src/southbridge/amd/pi/hudson/acpi/usb.asl<br>+++ b/src/southbridge/amd/pi/hudson/acpi/usb.asl<br>@@ -50,7 +50,7 @@<br> Name(_PRW, Package() {0x0B, 3})<br> } /* end UOH5 */<br> <br>-#if !CONFIG_SOUTHBRIDGE_AMD_PI_AVALON && !CONFIG_SOUTHBRIDGE_AMD_PI_KERN<br>+#if !IS_ENABLED(CONFIG_SOUTHBRIDGE_AMD_PI_AVALON) && !CONFIG_SOUTHBRIDGE_AMD_PI_KERN<br> /* 0:14.5 - OHCI */<br> Device(UEH1) {<br> Name(_ADR, 0x00140005)<br>@@ -64,7 +64,7 @@<br> Name(_PRW, Package() {0x0B, 4})<br> } /* end XHC0 */<br> <br>-#if !CONFIG_SOUTHBRIDGE_AMD_PI_AVALON && !CONFIG_SOUTHBRIDGE_AMD_PI_KERN<br>+#if !IS_ENABLED(CONFIG_SOUTHBRIDGE_AMD_PI_AVALON) && !CONFIG_SOUTHBRIDGE_AMD_PI_KERN<br> /* 0:10.1 - XHCI 1*/<br> Device(XHC1) {<br> Name(_ADR, 0x00100001)<br>diff --git a/src/southbridge/amd/pi/hudson/fadt.c b/src/southbridge/amd/pi/hudson/fadt.c<br>index ce8ce6d..84c6a1d 100644<br>--- a/src/southbridge/amd/pi/hudson/fadt.c<br>+++ b/src/southbridge/amd/pi/hudson/fadt.c<br>@@ -25,7 +25,7 @@<br> #include "hudson.h"<br> #include "smi.h"<br> <br>-#if CONFIG_HUDSON_LEGACY_FREE<br>+#if IS_ENABLED(CONFIG_HUDSON_LEGACY_FREE)<br> #define FADT_BOOT_ARCH ACPI_FADT_LEGACY_FREE<br> #else<br> #define FADT_BOOT_ARCH (ACPI_FADT_LEGACY_DEVICES | ACPI_FADT_8042)<br>diff --git a/src/southbridge/amd/rs690/cmn.c b/src/southbridge/amd/rs690/cmn.c<br>index 2ca92c3..7ef9ac0 100644<br>--- a/src/southbridge/amd/rs690/cmn.c<br>+++ b/src/southbridge/amd/rs690/cmn.c<br>@@ -308,7 +308,7 @@<br> void rs690_set_tom(device_t nb_dev)<br> {<br> /* set TOM */<br>-#if CONFIG_GFXUMA<br>+#if IS_ENABLED(CONFIG_GFXUMA)<br> pci_write_config32(nb_dev, 0x90, uma_memory_base);<br> nbmc_write_index(nb_dev, 0x1e, uma_memory_base);<br> #else<br>diff --git a/src/southbridge/amd/rs690/ht.c b/src/southbridge/amd/rs690/ht.c<br>index bbb33ef..3c56a37 100644<br>--- a/src/southbridge/amd/rs690/ht.c<br>+++ b/src/southbridge/amd/rs690/ht.c<br>@@ -24,7 +24,7 @@<br> <br> static void ht_dev_set_resources(device_t dev)<br> {<br>-#if CONFIG_EXT_CONF_SUPPORT<br>+#if IS_ENABLED(CONFIG_EXT_CONF_SUPPORT)<br> unsigned reg;<br> device_t k8_f1;<br> resource_t rbase, rend;<br>@@ -83,7 +83,7 @@<br> <br> unsigned long acpi_fill_mcfg(unsigned long current)<br> {<br>-#if CONFIG_EXT_CONF_SUPPORT<br>+#if IS_ENABLED(CONFIG_EXT_CONF_SUPPORT)<br> struct resource *res;<br> resource_t mmconf_base = EXT_CONF_BASE_ADDRESS; // default<br> <br>@@ -100,7 +100,7 @@<br> <br> static void ht_dev_read_resources(device_t dev)<br> {<br>-#if CONFIG_EXT_CONF_SUPPORT<br>+#if IS_ENABLED(CONFIG_EXT_CONF_SUPPORT)<br> struct resource *res;<br> <br> printk(BIOS_DEBUG,"%s %s\n", dev_path(dev), __func__);<br>@@ -109,7 +109,7 @@<br> <br> pci_dev_read_resources(dev);<br> <br>-#if CONFIG_EXT_CONF_SUPPORT<br>+#if IS_ENABLED(CONFIG_EXT_CONF_SUPPORT)<br> /* Add an MMCONFIG resource. */<br> res = new_resource(dev, 0x1C);<br> res->base = EXT_CONF_BASE_ADDRESS;<br>diff --git a/src/southbridge/amd/rs780/cmn.c b/src/southbridge/amd/rs780/cmn.c<br>index 49ba6eb..afa1aff 100644<br>--- a/src/southbridge/amd/rs780/cmn.c<br>+++ b/src/southbridge/amd/rs780/cmn.c<br>@@ -349,7 +349,7 @@<br> void rs780_set_tom(device_t nb_dev)<br> {<br> /* set TOM */<br>-#if CONFIG_GFXUMA<br>+#if IS_ENABLED(CONFIG_GFXUMA)<br> pci_write_config32(nb_dev, 0x90, uma_memory_base);<br> //nbmc_write_index(nb_dev, 0x1e, uma_memory_base);<br> #else<br>diff --git a/src/southbridge/amd/rs780/early_setup.c b/src/southbridge/amd/rs780/early_setup.c<br>index b0a40be..ec6c602 100644<br>--- a/src/southbridge/amd/rs780/early_setup.c<br>+++ b/src/southbridge/amd/rs780/early_setup.c<br>@@ -97,7 +97,7 @@<br> }<br> }<br> /* family 10 only, for reg > 0xFF */<br>-#if CONFIG_NORTHBRIDGE_AMD_AMDFAM10<br>+#if IS_ENABLED(CONFIG_NORTHBRIDGE_AMD_AMDFAM10)<br> static void set_fam10_ext_cfg_enable_bits(pci_devfn_t fam10_dev, u32 reg_pos,<br> u32 mask, u32 val)<br> {<br>@@ -143,7 +143,7 @@<br> return (cpuid_eax(1) & 0xff00000) != 0;<br> }<br> <br>-#if CONFIG_NORTHBRIDGE_AMD_AMDFAM10<br>+#if IS_ENABLED(CONFIG_NORTHBRIDGE_AMD_AMDFAM10)<br> static u8 l3_cache(void)<br> {<br> return (cpuid_edx(0x80000006) & (0x3FFF << 18)) != 0;<br>@@ -242,7 +242,7 @@<br> } else if ((cpu_ht_freq > 0x6) && (cpu_ht_freq < 0xf)) {<br> printk(BIOS_INFO, "rs780_htinit: HT3 mode\n");<br> <br>- #if CONFIG_NORTHBRIDGE_AMD_AMDFAM10<br>+ #if IS_ENABLED(CONFIG_NORTHBRIDGE_AMD_AMDFAM10)<br> /* HT3 mode, RPR 8.4.3 */<br> set_nbcfg_enable_bits(rs780_f0, 0x9c, 0x3 << 16, 0);<br> <br>@@ -282,7 +282,7 @@<br> }<br> }<br> <br>-#if !CONFIG_NORTHBRIDGE_AMD_AMDFAM10<br>+#if !IS_ENABLED(CONFIG_NORTHBRIDGE_AMD_AMDFAM10)<br> /*******************************************************<br> * Optimize k8 with UMA.<br> * See BKDG_NPT_0F guide for details.<br>@@ -338,7 +338,7 @@<br> #define k8_optimization() do {} while (0)<br> #endif /* !CONFIG_NORTHBRIDGE_AMD_AMDFAM10 */<br> <br>-#if CONFIG_NORTHBRIDGE_AMD_AMDFAM10<br>+#if IS_ENABLED(CONFIG_NORTHBRIDGE_AMD_AMDFAM10)<br> static void fam10_optimization(void)<br> {<br> pci_devfn_t cpu_f0, cpu_f2, cpu_f3;<br>diff --git a/src/southbridge/amd/rs780/gfx.c b/src/southbridge/amd/rs780/gfx.c<br>index 02be1f3..7f8bcb0 100644<br>--- a/src/southbridge/amd/rs780/gfx.c<br>+++ b/src/southbridge/amd/rs780/gfx.c<br>@@ -382,7 +382,7 @@<br> <br> /* GFX_InitFBAccess finished. */<br> <br>-#if CONFIG_GFXUMA /* for UMA mode. */<br>+#if IS_ENABLED(CONFIG_GFXUMA) /* for UMA mode. */<br> /* GFX_StartMC. */<br> set_nbmc_enable_bits(nb_dev, 0x02, 0x00000000, 0x80000000);<br> set_nbmc_enable_bits(nb_dev, 0x01, 0x00000000, 0x00000001);<br>@@ -444,7 +444,7 @@<br> vgainfo.sHeader.ucTableFormatRevision = 1;<br> vgainfo.sHeader.ucTableContentRevision = 2;<br> <br>-#if !CONFIG_GFXUMA /* SP mode. */<br>+#if !IS_ENABLED(CONFIG_GFXUMA) /* SP mode. */<br> // Side port support is incomplete, do not use it<br> // These parameters must match the motherboard<br> vgainfo.ulBootUpSidePortClock = 667*100;<br>@@ -629,7 +629,7 @@<br> /* Transfer the Table to VBIOS. */<br> pointer = (u32 *)&vgainfo;<br> for (i = 0; i < sizeof(ATOM_INTEGRATED_SYSTEM_INFO_V2); i+=4) {<br>-#if CONFIG_GFXUMA<br>+#if IS_ENABLED(CONFIG_GFXUMA)<br> *GpuF0MMReg = 0x80000000 + uma_memory_size - 512 + i;<br> #else<br> *GpuF0MMReg = 0x80000000 + 0x8000000 - 512 + i;<br>@@ -758,7 +758,7 @@<br> device_t nb_dev = dev_find_slot(0, 0);<br> msr_t sysmem;<br> <br>-#if !CONFIG_GFXUMA<br>+#if !IS_ENABLED(CONFIG_GFXUMA)<br> u32 FB_Start, FB_End;<br> #endif<br> <br>@@ -801,7 +801,7 @@<br> set_nbmc_enable_bits(nb_dev, 0x25, 0xffffffff, 0x111f111f);<br> set_htiu_enable_bits(nb_dev, 0x37, 1<<24, 1<<24);<br> <br>-#if CONFIG_GFXUMA<br>+#if IS_ENABLED(CONFIG_GFXUMA)<br> /* GFX_InitUMA. */<br> /* Copy CPU DDR Controller to NB MC. */<br> device_t k8_f1 = dev_find_slot(0, PCI_DEVFN(0x18, 1));<br>diff --git a/src/southbridge/amd/rs780/rs780.c b/src/southbridge/amd/rs780/rs780.c<br>index c2da54d..10263f2 100644<br>--- a/src/southbridge/amd/rs780/rs780.c<br>+++ b/src/southbridge/amd/rs780/rs780.c<br>@@ -206,7 +206,7 @@<br> <br> /* Program Straps. */<br> romstrap2 = 1 << 26; // enables audio function<br>-#if CONFIG_GFXUMA<br>+#if IS_ENABLED(CONFIG_GFXUMA)<br> // bits 7-9: aperture size<br> // 0-7: 128mb, 256mb, 64mb, 32mb, 512mb, 1g, 2g, 4g<br> if (uma_memory_size == 0x02000000) romstrap2 |= 3 << 7;<br>diff --git a/src/southbridge/amd/sb700/early_setup.c b/src/southbridge/amd/sb700/early_setup.c<br>index 3ed4cac..0cd65a6 100644<br>--- a/src/southbridge/amd/sb700/early_setup.c<br>+++ b/src/southbridge/amd/sb700/early_setup.c<br>@@ -152,7 +152,7 @@<br> reg32 |= 1 << 20;<br> pci_write_config32(dev, 0x64, reg32);<br> <br>-#if CONFIG_SOUTHBRIDGE_AMD_SUBTYPE_SP5100<br>+#if IS_ENABLED(CONFIG_SOUTHBRIDGE_AMD_SUBTYPE_SP5100)<br> post_code(0x66);<br> dev = pci_locate_device(PCI_ID(0x1002, 0x439d), 0); /* LPC Controller */<br> reg8 = pci_read_config8(dev, 0xBB);<br>@@ -166,7 +166,7 @@<br> // XXX Serial port decode on LPC is hardcoded to 0x3f8<br> reg8 = pci_read_config8(dev, 0x44);<br> reg8 |= 1 << 6;<br>-#if CONFIG_SOUTHBRIDGE_AMD_SUBTYPE_SP5100<br>+#if IS_ENABLED(CONFIG_SOUTHBRIDGE_AMD_SUBTYPE_SP5100)<br> #if CONFIG_TTYS0_BASE == 0x2f8<br> reg8 |= 1 << 7;<br> #endif<br>@@ -532,7 +532,7 @@<br> pci_write_config8(dev, 0x50, 0x01);<br> <br> if (!sata_ahci_mode){<br>-#if CONFIG_SOUTHBRIDGE_AMD_SUBTYPE_SP5100<br>+#if IS_ENABLED(CONFIG_SOUTHBRIDGE_AMD_SUBTYPE_SP5100)<br> /* SP5100 default SATA mode is RAID5 MODE */<br> dev = pci_locate_device(PCI_ID(0x1002, 0x4392), 0);<br> <br>@@ -688,7 +688,7 @@<br> byte |= 0xc0;<br> pmio_write(0xbb, byte);<br> <br>-#if CONFIG_SOUTHBRIDGE_AMD_SUBTYPE_SP5100<br>+#if IS_ENABLED(CONFIG_SOUTHBRIDGE_AMD_SUBTYPE_SP5100)<br> /* RPR 2.26 Alter CPU reset timing */<br> byte = pmio_read(0xb2);<br> byte |= 0x1 << 2; /* Enable CPU reset timing option */<br>diff --git a/src/southbridge/amd/sb700/lpc.c b/src/southbridge/amd/sb700/lpc.c<br>index fda30b8..8ee0395 100644<br>--- a/src/southbridge/amd/sb700/lpc.c<br>+++ b/src/southbridge/amd/sb700/lpc.c<br>@@ -47,7 +47,7 @@<br> pci_write_config32(sm_dev, 0x64, dword);<br> <br> /* Initialize isa dma */<br>-#if CONFIG_SOUTHBRIDGE_AMD_SB700_SKIP_ISA_DMA_INIT<br>+#if IS_ENABLED(CONFIG_SOUTHBRIDGE_AMD_SB700_SKIP_ISA_DMA_INIT)<br> printk(BIOS_DEBUG, "Skipping isa_dma_init() to avoid getting stuck.\n");<br> #else<br> isa_dma_init();<br>@@ -68,7 +68,7 @@<br> /* Disable LPC MSI Capability */<br> byte = pci_read_config8(dev, 0x78);<br> byte &= ~(1 << 1);<br>-#if CONFIG_SOUTHBRIDGE_AMD_SUBTYPE_SP5100<br>+#if IS_ENABLED(CONFIG_SOUTHBRIDGE_AMD_SUBTYPE_SP5100)<br> /* Disable FlowContrl, Always service the request from Host<br> * whenever there is a request from Host pending<br> */<br>diff --git a/src/southbridge/amd/sb700/sata.c b/src/southbridge/amd/sb700/sata.c<br>index 235278d..537c2c0 100644<br>--- a/src/southbridge/amd/sb700/sata.c<br>+++ b/src/southbridge/amd/sb700/sata.c<br>@@ -350,7 +350,7 @@<br> byte |= 7 << 0;<br> pci_write_config8(dev, 0x4, byte);<br> <br>-#if CONFIG_SOUTHBRIDGE_AMD_SUBTYPE_SP5100<br>+#if IS_ENABLED(CONFIG_SOUTHBRIDGE_AMD_SUBTYPE_SP5100)<br> /* Master Latency Timer */<br> pci_write_config32(dev, 0xC, 0x00004000);<br> #endif<br>diff --git a/src/southbridge/amd/sb700/sb700.c b/src/southbridge/amd/sb700/sb700.c<br>index 74650e7..1068721 100644<br>--- a/src/southbridge/amd/sb700/sb700.c<br>+++ b/src/southbridge/amd/sb700/sb700.c<br>@@ -222,7 +222,7 @@<br> }<br> }<br> <br>-#if CONFIG_SOUTHBRIDGE_AMD_SUBTYPE_SP5100<br>+#if IS_ENABLED(CONFIG_SOUTHBRIDGE_AMD_SUBTYPE_SP5100)<br> struct chip_operations southbridge_amd_sb700_ops = {<br> CHIP_NAME("ATI SP5100")<br> .enable_dev = sb7xx_51xx_enable,<br>diff --git a/src/southbridge/amd/sb700/usb.c b/src/southbridge/amd/sb700/usb.c<br>index 0fdff78..6276008 100644<br>--- a/src/southbridge/amd/sb700/usb.c<br>+++ b/src/southbridge/amd/sb700/usb.c<br>@@ -181,7 +181,7 @@<br> dword |= 1 << 8;<br> dword &= ~(1 << 27); /* 6.23 */<br> }<br>-#if CONFIG_SOUTHBRIDGE_AMD_SUBTYPE_SP5100<br>+#if IS_ENABLED(CONFIG_SOUTHBRIDGE_AMD_SUBTYPE_SP5100)<br> /* SP5100 Erratum 36 */<br> dword &= ~(1 << 26);<br> if (!ehci_async_data_cache)<br>diff --git a/src/southbridge/amd/sr5650/early_setup.c b/src/southbridge/amd/sr5650/early_setup.c<br>index fce25ab..6b4d81a 100644<br>--- a/src/southbridge/amd/sr5650/early_setup.c<br>+++ b/src/southbridge/amd/sr5650/early_setup.c<br>@@ -50,7 +50,8 @@<br> <br> <br> /* family 10 only, for reg > 0xFF */<br>-#if CONFIG_NORTHBRIDGE_AMD_AMDFAM10 || CONFIG_NORTHBRIDGE_AMD_AGESA_FAMILY10<br>+#if IS_ENABLED(CONFIG_NORTHBRIDGE_AMD_AMDFAM10) || \<br>+ IS_ENABLED(CONFIG_NORTHBRIDGE_AMD_AGESA_FAMILY10)<br> static void set_fam10_ext_cfg_enable_bits(device_t fam10_dev, u32 reg_pos, u32 mask,<br> u32 val)<br> {<br>@@ -221,7 +222,8 @@<br> /* Enable Protocol checker */<br> set_htiu_enable_bits(sr5650_f0, 0x1E, 0xFFFFFFFF, 0x7FFFFFFC);<br> <br>-#if CONFIG_NORTHBRIDGE_AMD_AMDFAM10 || CONFIG_NORTHBRIDGE_AMD_AGESA_FAMILY10 /* save some spaces */<br>+#if IS_ENABLED(CONFIG_NORTHBRIDGE_AMD_AMDFAM10) || \<br>+ IS_ENABLED(CONFIG_NORTHBRIDGE_AMD_AGESA_FAMILY10)<br> /* HT3 mode, RPR 5.4.3 */<br> set_nbcfg_enable_bits(sr5650_f0, 0x9c, 0x3 << 16, 0);<br> <br>@@ -299,7 +301,8 @@<br> }<br> }<br> <br>-#if CONFIG_NORTHBRIDGE_AMD_AMDFAM10 || CONFIG_NORTHBRIDGE_AMD_AGESA_FAMILY10 /* save some spaces */<br>+#if IS_ENABLED(CONFIG_NORTHBRIDGE_AMD_AMDFAM10) || \<br>+ IS_ENABLED(CONFIG_NORTHBRIDGE_AMD_AGESA_FAMILY10)<br> void fam10_optimization(void)<br> {<br> device_t cpu_f0, cpu_f2, cpu_f3;<br></pre><p>To view, visit <a href="https://review.coreboot.org/20349">change 20349</a>. To unsubscribe, visit <a href="https://review.coreboot.org/settings">settings</a>.</p><div itemscope itemtype="http://schema.org/EmailMessage"><div itemscope itemprop="action" itemtype="http://schema.org/ViewAction"><link itemprop="url" href="https://review.coreboot.org/20349"/><meta itemprop="name" content="View Change"/></div></div>
<div style="display:none"> Gerrit-Project: coreboot </div>
<div style="display:none"> Gerrit-Branch: master </div>
<div style="display:none"> Gerrit-MessageType: newchange </div>
<div style="display:none"> Gerrit-Change-Id: I8fabb7331435eb518a5c95cb29c4ff5ca98560d2 </div>
<div style="display:none"> Gerrit-Change-Number: 20349 </div>
<div style="display:none"> Gerrit-PatchSet: 1 </div>
<div style="display:none"> Gerrit-Owner: Martin Roth <martinroth@google.com> </div>