<p>Martin Roth has uploaded this change for <strong>review</strong>.</p><p><a href="https://review.coreboot.org/20345">View Change</a></p><pre style="font-family: monospace,monospace; white-space: pre-wrap;">nb/amd: add IS_ENABLED() around Kconfig symbol references<br><br>Some of these can be changed from #if to if(), but that will happen<br>in a follow-on commmit.<br><br>Change-Id: I763cbbc31dcd4cdd128c04793a742ab6daaf5f0c<br>Signed-off-by: Martin Roth <martinroth@google.com><br>---<br>M src/northbridge/amd/agesa/family10/northbridge.c<br>M src/northbridge/amd/agesa/family12/northbridge.c<br>M src/northbridge/amd/agesa/family14/northbridge.c<br>M src/northbridge/amd/agesa/family15/northbridge.c<br>M src/northbridge/amd/agesa/family15rl/northbridge.c<br>M src/northbridge/amd/agesa/family15tn/northbridge.c<br>M src/northbridge/amd/agesa/family16kb/northbridge.c<br>M src/northbridge/amd/amdfam10/debug.c<br>M src/northbridge/amd/amdfam10/debug.h<br>M src/northbridge/amd/amdfam10/early_ht.c<br>M src/northbridge/amd/amdfam10/northbridge.c<br>M src/northbridge/amd/amdht/h3finit.c<br>M src/northbridge/amd/amdk8/Makefile.inc<br>M src/northbridge/amd/amdk8/amdk8.h<br>M src/northbridge/amd/amdk8/coherent_ht.c<br>M src/northbridge/amd/amdk8/debug.c<br>M src/northbridge/amd/amdk8/incoherent_ht.c<br>M src/northbridge/amd/amdk8/misc_control.c<br>M src/northbridge/amd/amdk8/northbridge.c<br>M src/northbridge/amd/amdk8/raminit.c<br>M src/northbridge/amd/amdk8/raminit.h<br>M src/northbridge/amd/amdk8/raminit_f.c<br>M src/northbridge/amd/amdk8/raminit_f_dqs.c<br>M src/northbridge/amd/amdmct/wrappers/mcti_d.c<br>M src/northbridge/amd/cimx/rd890/NbPlatform.h<br>M src/northbridge/amd/pi/00630F01/northbridge.c<br>M src/northbridge/amd/pi/00660F01/northbridge.c<br>M src/northbridge/amd/pi/00670F00/northbridge.c<br>M src/northbridge/amd/pi/00730F01/northbridge.c<br>29 files changed, 147 insertions(+), 147 deletions(-)<br><br></pre><pre style="font-family: monospace,monospace; white-space: pre-wrap;">git pull ssh://review.coreboot.org:29418/coreboot refs/changes/45/20345/1</pre><pre style="font-family: monospace,monospace; white-space: pre-wrap;">diff --git a/src/northbridge/amd/agesa/family10/northbridge.c b/src/northbridge/amd/agesa/family10/northbridge.c<br>index 6f7a053..242a812 100644<br>--- a/src/northbridge/amd/agesa/family10/northbridge.c<br>+++ b/src/northbridge/amd/agesa/family10/northbridge.c<br>@@ -27,7 +27,7 @@<br> #include <cpu/x86/lapic.h><br> #include <cbmem.h><br> <br>-#if CONFIG_LOGICAL_CPUS<br>+#if IS_ENABLED(CONFIG_LOGICAL_CPUS)<br> #include <pc80/mc146818rtc.h><br> #endif<br> <br>@@ -496,7 +496,7 @@<br> * we only deal with the 'first' vga card */<br> for (link = dev->link_list; link; link = link->next) {<br> if (link->bridge_ctrl & PCI_BRIDGE_CTL_VGA) {<br>-#if CONFIG_MULTIPLE_VGA_ADAPTERS<br>+#if IS_ENABLED(CONFIG_MULTIPLE_VGA_ADAPTERS)<br> extern device_t vga_pri; // the primary vga device, defined in device.c<br> printk(BIOS_DEBUG, "VGA: vga_pri bus num = %d bus range [%d,%d]\n", vga_pri->bus->secondary,<br> link->secondary,link->subordinate);<br>@@ -800,7 +800,7 @@<br> ramtop = limitk * 1024;<br> }<br> <br>-#if CONFIG_GFXUMA<br>+#if IS_ENABLED(CONFIG_GFXUMA)<br> set_top_of_ram(uma_memory_base);<br> uma_resource(dev, 7, uma_memory_base >> 10, uma_memory_size >> 10);<br> #else<br>@@ -942,7 +942,7 @@<br> }<br> <br> disable_siblings = !CONFIG_LOGICAL_CPUS;<br>-#if CONFIG_LOGICAL_CPUS<br>+#if IS_ENABLED(CONFIG_LOGICAL_CPUS)<br> get_option(&disable_siblings, "multi_core");<br> #endif<br> <br>@@ -1117,7 +1117,7 @@<br> the global uma_memory variables already in its enable function. */<br> if (!done) {<br> setup_bsp_ramtop();<br>-#if CONFIG_GFXUMA<br>+#if IS_ENABLED(CONFIG_GFXUMA)<br> #error Northbridge does not set uma_memory_base or uma_memory_size.<br> setup_uma_memory();<br> #endif<br>diff --git a/src/northbridge/amd/agesa/family12/northbridge.c b/src/northbridge/amd/agesa/family12/northbridge.c<br>index c931bf0..00e7e5b 100644<br>--- a/src/northbridge/amd/agesa/family12/northbridge.c<br>+++ b/src/northbridge/amd/agesa/family12/northbridge.c<br>@@ -362,7 +362,7 @@<br> }<br> <br> <br>-#if CONFIG_CONSOLE_VGA_MULTI<br>+#if IS_ENABLED(CONFIG_CONSOLE_VGA_MULTI)<br> extern device_t vga_pri; // the primary vga device, defined in device.c<br> #endif<br> <br>@@ -376,7 +376,7 @@<br> * we only deal with the 'first' vga card */<br> for (link = dev->link_list; link; link = link->next) {<br> if (link->bridge_ctrl & PCI_BRIDGE_CTL_VGA) {<br>-#if CONFIG_CONSOLE_VGA_MULTI<br>+#if IS_ENABLED(CONFIG_CONSOLE_VGA_MULTI)<br> printk(BIOS_DEBUG, "VGA: vga_pri bus num = %d bus range [%d,%d]\n", vga_pri->bus->secondary,<br> link->secondary,link->subordinate);<br> /* We need to make sure the vga_pri is under the link */<br>@@ -600,7 +600,7 @@<br> printk(BIOS_DEBUG, "\nFam12h - northbridge.c - %s - Start.\n",__func__);<br> <br> /* Must be called after PCI enumeration and resource allocation */<br>-#if CONFIG_AMD_SB_CIMX<br>+#if IS_ENABLED(CONFIG_AMD_SB_CIMX)<br> sb_After_Pci_Init();<br> sb_Mid_Post_Init();<br> #endif<br>diff --git a/src/northbridge/amd/agesa/family14/northbridge.c b/src/northbridge/amd/agesa/family14/northbridge.c<br>index e570096..d5bf730 100644<br>--- a/src/northbridge/amd/agesa/family14/northbridge.c<br>+++ b/src/northbridge/amd/agesa/family14/northbridge.c<br>@@ -353,7 +353,7 @@<br> report_resource_stored(dev, resource, buf);<br> }<br> <br>-#if CONFIG_CONSOLE_VGA_MULTI<br>+#if IS_ENABLED(CONFIG_CONSOLE_VGA_MULTI)<br> extern device_t vga_pri; // the primary vga device, defined in device.c<br> #endif<br> <br>@@ -367,7 +367,7 @@<br> * we only deal with the 'first' vga card */<br> for (link = dev->link_list; link; link = link->next) {<br> if (link->bridge_ctrl & PCI_BRIDGE_CTL_VGA) {<br>-#if CONFIG_CONSOLE_VGA_MULTI<br>+#if IS_ENABLED(CONFIG_CONSOLE_VGA_MULTI)<br> printk(BIOS_DEBUG,<br> "VGA: vga_pri bus num = %d bus range [%d,%d]\n",<br> vga_pri->bus->secondary, link->secondary,<br>@@ -581,7 +581,7 @@<br> <br> static void domain_enable_resources(device_t dev)<br> {<br>-#if CONFIG_AMD_SB_CIMX<br>+#if IS_ENABLED(CONFIG_AMD_SB_CIMX)<br> if (!acpi_is_wakeup_s3()) {<br> sb_After_Pci_Init();<br> sb_Mid_Post_Init();<br>diff --git a/src/northbridge/amd/agesa/family15/northbridge.c b/src/northbridge/amd/agesa/family15/northbridge.c<br>index 5cb0f91..ff06f2c 100644<br>--- a/src/northbridge/amd/agesa/family15/northbridge.c<br>+++ b/src/northbridge/amd/agesa/family15/northbridge.c<br>@@ -391,7 +391,7 @@<br> * we only deal with the 'first' vga card */<br> for (link = dev->link_list; link; link = link->next) {<br> if (link->bridge_ctrl & PCI_BRIDGE_CTL_VGA) {<br>-#if CONFIG_MULTIPLE_VGA_ADAPTERS<br>+#if IS_ENABLED(CONFIG_MULTIPLE_VGA_ADAPTERS)<br> extern device_t vga_pri; // the primary vga device, defined in device.c<br> printk(BIOS_DEBUG, "VGA: vga_pri bus num = %d bus range [%d,%d]\n", vga_pri->bus->secondary,<br> link->secondary,link->subordinate);<br>@@ -640,7 +640,7 @@<br> /* Must be called after PCI enumeration and resource allocation */<br> printk(BIOS_DEBUG, "\nFam15 - %s: AmdInitMid.\n", __func__);<br> <br>-#if CONFIG_AMD_SB_CIMX<br>+#if IS_ENABLED(CONFIG_AMD_SB_CIMX)<br> sb_After_Pci_Init();<br> #endif<br> /* Enable MMIO on AMD CPU Address Map Controller */<br>@@ -1021,7 +1021,7 @@<br> lapicid_start = (lapicid_start + 1) * core_max;<br> printk(BIOS_SPEW, "lpaicid_start = 0x%x ", lapicid_start);<br> }<br>-#if CONFIG_CPU_AMD_SOCKET_G34<br>+#if IS_ENABLED(CONFIG_CPU_AMD_SOCKET_G34)<br> u32 apic_id = (i / 2 * core_max) + j + lapicid_start + (i % 2 ? siblings + 1 : 0);<br> #else<br> u32 apic_id = (i * core_max) + j + lapicid_start;<br>diff --git a/src/northbridge/amd/agesa/family15rl/northbridge.c b/src/northbridge/amd/agesa/family15rl/northbridge.c<br>index aa24a6a..1d53301 100644<br>--- a/src/northbridge/amd/agesa/family15rl/northbridge.c<br>+++ b/src/northbridge/amd/agesa/family15rl/northbridge.c<br>@@ -390,7 +390,7 @@<br> * we only deal with the 'first' vga card */<br> for (link = dev->link_list; link; link = link->next) {<br> if (link->bridge_ctrl & PCI_BRIDGE_CTL_VGA) {<br>-#if CONFIG_MULTIPLE_VGA_ADAPTERS<br>+#if IS_ENABLED(CONFIG_MULTIPLE_VGA_ADAPTERS)<br> extern struct device *vga_pri; // the primary vga device, defined in device.c<br> printk(BIOS_DEBUG, "VGA: vga_pri bus num = %d bus range [%d,%d]\n", vga_pri->bus->secondary,<br> link->secondary,link->subordinate);<br>diff --git a/src/northbridge/amd/agesa/family15tn/northbridge.c b/src/northbridge/amd/agesa/family15tn/northbridge.c<br>index 95787fc..93d3880 100644<br>--- a/src/northbridge/amd/agesa/family15tn/northbridge.c<br>+++ b/src/northbridge/amd/agesa/family15tn/northbridge.c<br>@@ -389,7 +389,7 @@<br> * we only deal with the 'first' vga card */<br> for (link = dev->link_list; link; link = link->next) {<br> if (link->bridge_ctrl & PCI_BRIDGE_CTL_VGA) {<br>-#if CONFIG_MULTIPLE_VGA_ADAPTERS<br>+#if IS_ENABLED(CONFIG_MULTIPLE_VGA_ADAPTERS)<br> extern device_t vga_pri; // the primary vga device, defined in device.c<br> printk(BIOS_DEBUG, "VGA: vga_pri bus num = %d bus range [%d,%d]\n", vga_pri->bus->secondary,<br> link->secondary,link->subordinate);<br>diff --git a/src/northbridge/amd/agesa/family16kb/northbridge.c b/src/northbridge/amd/agesa/family16kb/northbridge.c<br>index f91448a..f56dcb9 100644<br>--- a/src/northbridge/amd/agesa/family16kb/northbridge.c<br>+++ b/src/northbridge/amd/agesa/family16kb/northbridge.c<br>@@ -389,7 +389,7 @@<br> * we only deal with the 'first' vga card */<br> for (link = dev->link_list; link; link = link->next) {<br> if (link->bridge_ctrl & PCI_BRIDGE_CTL_VGA) {<br>-#if CONFIG_MULTIPLE_VGA_ADAPTERS<br>+#if IS_ENABLED(CONFIG_MULTIPLE_VGA_ADAPTERS)<br> extern device_t vga_pri; // the primary vga device, defined in device.c<br> printk(BIOS_DEBUG, "VGA: vga_pri bus num = %d bus range [%d,%d]\n", vga_pri->bus->secondary,<br> link->secondary,link->subordinate);<br>diff --git a/src/northbridge/amd/amdfam10/debug.c b/src/northbridge/amd/amdfam10/debug.c<br>index ed2b539..067c299 100644<br>--- a/src/northbridge/amd/amdfam10/debug.c<br>+++ b/src/northbridge/amd/amdfam10/debug.c<br>@@ -21,7 +21,7 @@<br> <br> void print_debug_addr(const char *str, void *val)<br> {<br>-#if CONFIG_DEBUG_CAR<br>+#if IS_ENABLED(CONFIG_DEBUG_CAR)<br> printk(BIOS_DEBUG, "------Address debug: %s%p------\n", str, val);<br> #endif<br> }<br>@@ -205,7 +205,7 @@<br> }<br> }<br> <br>-#if CONFIG_DEBUG_SMBUS<br>+#if IS_ENABLED(CONFIG_DEBUG_SMBUS)<br> void dump_spd_registers(const struct mem_controller *ctrl)<br> {<br> int i;<br>@@ -315,14 +315,14 @@<br> #if IS_ENABLED(CONFIG_DIMM_DDR2)<br> void print_tx(const char *strval, u32 val)<br> {<br>-#if CONFIG_DEBUG_RAM_SETUP<br>+#if IS_ENABLED(CONFIG_DEBUG_RAM_SETUP)<br> printk(BIOS_DEBUG, "%s%08x\n", strval, val);<br> #endif<br> }<br> <br> void print_t(const char *strval)<br> {<br>-#if CONFIG_DEBUG_RAM_SETUP<br>+#if IS_ENABLED(CONFIG_DEBUG_RAM_SETUP)<br> printk(BIOS_DEBUG, "%s", strval);<br> #endif<br> }<br>@@ -330,7 +330,7 @@<br> <br> void print_tf(const char *func, const char *strval)<br> {<br>-#if CONFIG_DEBUG_RAM_SETUP<br>+#if IS_ENABLED(CONFIG_DEBUG_RAM_SETUP)<br> printk(BIOS_DEBUG, "%s: %s", func, strval);<br> #endif<br> }<br>diff --git a/src/northbridge/amd/amdfam10/debug.h b/src/northbridge/amd/amdfam10/debug.h<br>index df1f3a0..a4ecfe9 100644<br>--- a/src/northbridge/amd/amdfam10/debug.h<br>+++ b/src/northbridge/amd/amdfam10/debug.h<br>@@ -32,7 +32,7 @@<br> void dump_pci_devices(void);<br> void dump_pci_devices_on_bus(u32 busn);<br> <br>-#if CONFIG_DEBUG_SMBUS<br>+#if IS_ENABLED(CONFIG_DEBUG_SMBUS)<br> void dump_spd_registers(const struct mem_controller *ctrl);<br> void dump_smbus_registers(void);<br> #endif<br>diff --git a/src/northbridge/amd/amdfam10/early_ht.c b/src/northbridge/amd/amdfam10/early_ht.c<br>index c3b02d7..c68b0c4 100644<br>--- a/src/northbridge/amd/amdfam10/early_ht.c<br>+++ b/src/northbridge/amd/amdfam10/early_ht.c<br>@@ -22,7 +22,7 @@<br> // mmconf is not ready yet<br> void set_bsp_node_CHtExtNodeCfgEn(void)<br> {<br>-#if CONFIG_EXT_RT_TBL_SUPPORT<br>+#if IS_ENABLED(CONFIG_EXT_RT_TBL_SUPPORT)<br> u32 dword;<br> dword = pci_io_read_config32(PCI_DEV(0, 0x18, 0), 0x68);<br> dword |= (1<<27) | (1<<25);<br>diff --git a/src/northbridge/amd/amdfam10/northbridge.c b/src/northbridge/amd/amdfam10/northbridge.c<br>index a306d25..7d02e9a 100644<br>--- a/src/northbridge/amd/amdfam10/northbridge.c<br>+++ b/src/northbridge/amd/amdfam10/northbridge.c<br>@@ -36,7 +36,7 @@<br> #include <cpu/amd/msr.h><br> #include <cpu/amd/family_10h-family_15h/ram_calc.h><br> <br>-#if CONFIG_LOGICAL_CPUS<br>+#if IS_ENABLED(CONFIG_LOGICAL_CPUS)<br> #include <cpu/amd/multicore.h><br> #include <pc80/mc146818rtc.h><br> #endif<br>@@ -50,7 +50,7 @@<br> #include <cpu/amd/model_10xxx_rev.h><br> #endif<br> <br>-#if CONFIG_AMD_SB_CIMX<br>+#if IS_ENABLED(CONFIG_AMD_SB_CIMX)<br> #include <sb_cimx.h><br> #endif<br> <br>@@ -320,7 +320,7 @@<br> {<br> struct bus *link;<br> <br>-#if CONFIG_CPU_AMD_SOCKET_G34_NON_AGESA<br>+#if IS_ENABLED(CONFIG_CPU_AMD_SOCKET_G34_NON_AGESA)<br> if (is_fam15h()) {<br> uint8_t current_link_number = 0;<br> <br>@@ -585,7 +585,7 @@<br> * we only deal with the 'first' vga card */<br> for (link = dev->link_list; link; link = link->next) {<br> if (link->bridge_ctrl & PCI_BRIDGE_CTL_VGA) {<br>-#if CONFIG_MULTIPLE_VGA_ADAPTERS<br>+#if IS_ENABLED(CONFIG_MULTIPLE_VGA_ADAPTERS)<br> extern device_t vga_pri; // the primary vga device, defined in device.c<br> printk(BIOS_DEBUG, "VGA: vga_pri bus num = %d bus range [%d,%d]\n", vga_pri->bus->secondary,<br> link->secondary,link->subordinate);<br>@@ -890,7 +890,7 @@<br> <br> static void setup_uma_memory(void)<br> {<br>-#if CONFIG_GFXUMA<br>+#if IS_ENABLED(CONFIG_GFXUMA)<br> uint32_t topmem = (uint32_t) bsp_topmem();<br> uma_memory_size = get_uma_memory_size(topmem);<br> uma_memory_base = topmem - uma_memory_size; /* TOP_MEM1 */<br>@@ -989,7 +989,7 @@<br> i, mmio_basek, basek, limitk);<br> }<br> <br>-#if CONFIG_GFXUMA<br>+#if IS_ENABLED(CONFIG_GFXUMA)<br> uma_resource(dev, 7, uma_memory_base >> 10, uma_memory_size >> 10);<br> #endif<br> <br>@@ -1330,7 +1330,7 @@<br> #if IS_ENABLED(CONFIG_HAVE_ACPI_TABLES)<br> .acpi_name = amdfam10_domain_acpi_name,<br> #endif<br>-#if CONFIG_GENERATE_SMBIOS_TABLES<br>+#if IS_ENABLED(CONFIG_GENERATE_SMBIOS_TABLES)<br> .get_smbios_data = amdfam10_get_smbios_data,<br> #endif<br> };<br>@@ -1359,7 +1359,7 @@<br> sysconf.bsp_apicid = lapicid();<br> sysconf.apicid_offset = sysconf.bsp_apicid;<br> <br>-#if CONFIG_ENABLE_APIC_EXT_ID<br>+#if IS_ENABLED(CONFIG_ENABLE_APIC_EXT_ID)<br> if (pci_read_config32(dev, 0x68) & (HTTC_APIC_EXT_ID|HTTC_APIC_EXT_BRD_CST))<br> {<br> sysconf.enabled_apic_ext_id = 1;<br>@@ -1454,7 +1454,7 @@<br> }<br> <br> disable_siblings = !CONFIG_LOGICAL_CPUS;<br>-#if CONFIG_LOGICAL_CPUS<br>+#if IS_ENABLED(CONFIG_LOGICAL_CPUS)<br> get_option(&disable_siblings, "multi_core");<br> #endif<br> <br>@@ -1659,7 +1659,7 @@<br> }<br> }<br> <br>-#if CONFIG_ENABLE_APIC_EXT_ID && (CONFIG_APIC_ID_OFFSET > 0)<br>+#if IS_ENABLED(CONFIG_ENABLE_APIC_EXT_ID) && (CONFIG_APIC_ID_OFFSET > 0)<br> if (sysconf.enabled_apic_ext_id) {<br> if (apic_id != 0 || sysconf.lift_bsp_apicid) {<br> apic_id += sysconf.apicid_offset;<br>@@ -1955,7 +1955,7 @@<br> detect_and_enable_probe_filter(dev);<br> detect_and_enable_cache_partitioning(dev);<br> initialize_cpus(dev->link_list);<br>-#if CONFIG_AMD_SB_CIMX<br>+#if IS_ENABLED(CONFIG_AMD_SB_CIMX)<br> sb_After_Pci_Init();<br> sb_Mid_Post_Init();<br> #endif<br>diff --git a/src/northbridge/amd/amdht/h3finit.c b/src/northbridge/amd/amdht/h3finit.c<br>index 6a9d898..fc0c2d2 100644<br>--- a/src/northbridge/amd/amdht/h3finit.c<br>+++ b/src/northbridge/amd/amdht/h3finit.c<br>@@ -1492,13 +1492,13 @@<br> cbPCBFreqLimit = ht_speed_mhz_to_hw(pDat->HtBlock->ht_link_configuration->ht_speed_limit);<br> cbPCBFreqLimit = min(cbPCBFreqLimit, cbPCBFreqLimit_NVRAM);<br> <br>-#if CONFIG_LIMIT_HT_DOWN_WIDTH_8<br>+#if IS_ENABLED(CONFIG_LIMIT_HT_DOWN_WIDTH_8)<br> cbPCBABDownstreamWidth = 8;<br> #else<br> cbPCBABDownstreamWidth = 16;<br> #endif<br> <br>-#if CONFIG_LIMIT_HT_UP_WIDTH_8<br>+#if IS_ENABLED(CONFIG_LIMIT_HT_UP_WIDTH_8)<br> cbPCBBAUpstreamWidth = 8;<br> #else<br> cbPCBBAUpstreamWidth = 16;<br>diff --git a/src/northbridge/amd/amdk8/Makefile.inc b/src/northbridge/amd/amdk8/Makefile.inc<br>index c6b1ac6..263e06f 100644<br>--- a/src/northbridge/amd/amdk8/Makefile.inc<br>+++ b/src/northbridge/amd/amdk8/Makefile.inc<br>@@ -20,7 +20,7 @@<br> <br> # Not sure what to do with these yet. How did raminit_test even work?<br> # Should be a target in -y form.<br>-#if CONFIG_K8_REV_F_SUPPORT<br>+#if IS_ENABLED(CONFIG_K8_REV_F_SUPPORT)<br> #<br> #makerule raminit_test<br> # depends "$(TOP)/src/northbridge/amd/amdk8/raminit_test.c"<br>diff --git a/src/northbridge/amd/amdk8/amdk8.h b/src/northbridge/amd/amdk8/amdk8.h<br>index e335a98..65b6fb6 100644<br>--- a/src/northbridge/amd/amdk8/amdk8.h<br>+++ b/src/northbridge/amd/amdk8/amdk8.h<br>@@ -2,7 +2,7 @@<br> <br> #define AMDK8_H<br> <br>-#if CONFIG_K8_REV_F_SUPPORT<br>+#if IS_ENABLED(CONFIG_K8_REV_F_SUPPORT)<br> <br> #define K8_REV_F_SUPPORT_F0_F1_WORKAROUND 0<br> <br>@@ -26,7 +26,7 @@<br> void fill_mem_ctrl(int controllers, struct mem_controller *ctrl_a, const uint16_t *spd_addr);<br> int optimize_link_coherent_ht(void);<br> unsigned int get_nodes(void);<br>-#if CONFIG_RAMINIT_SYSINFO<br>+#if IS_ENABLED(CONFIG_RAMINIT_SYSINFO)<br> void setup_coherent_ht_domain(void);<br> #else<br> int setup_coherent_ht_domain(void);<br>diff --git a/src/northbridge/amd/amdk8/coherent_ht.c b/src/northbridge/amd/amdk8/coherent_ht.c<br>index 10ca6ee..b0865fb 100644<br>--- a/src/northbridge/amd/amdk8/coherent_ht.c<br>+++ b/src/northbridge/amd/amdk8/coherent_ht.c<br>@@ -73,7 +73,7 @@<br> #include <stdint.h><br> #include <arch/io.h><br> #include <pc80/mc146818rtc.h><br>-#if CONFIG_HAVE_OPTION_TABLE<br>+#if IS_ENABLED(CONFIG_HAVE_OPTION_TABLE)<br> #include "option_table.h"<br> #endif<br> <br>@@ -258,8 +258,8 @@<br> freq_cap = pci_read_config16(dev, pos);<br> freq_cap &= ~(1 << HT_FREQ_VENDOR); /* Ignore Vendor HT frequencies */<br> <br>-#if CONFIG_K8_HT_FREQ_1G_SUPPORT<br>- #if !CONFIG_K8_REV_F_SUPPORT<br>+#if IS_ENABLED(CONFIG_K8_HT_FREQ_1G_SUPPORT)<br>+ #if !IS_ENABLED(CONFIG_K8_REV_F_SUPPORT)<br> if (!is_cpu_pre_e0())<br> #endif<br> {<br>@@ -633,7 +633,7 @@<br> static void setup_uniprocessor(void)<br> {<br> printk(BIOS_SPEW, "Enabling UP settings\n");<br>-#if CONFIG_LOGICAL_CPUS<br>+#if IS_ENABLED(CONFIG_LOGICAL_CPUS)<br> unsigned tmp = (pci_read_config32(NODE_MC(0), 0xe8) >> 12) & 3;<br> if (tmp > 0) return;<br> #endif<br>@@ -1516,7 +1516,7 @@<br> }<br> #endif /* CONFIG_MAX_PHYSICAL_CPUS > 1 */<br> <br>-#if CONFIG_LOGICAL_CPUS<br>+#if IS_ENABLED(CONFIG_LOGICAL_CPUS)<br> static unsigned verify_dualcore(unsigned nodes)<br> {<br> unsigned node, totalcpus, tmp;<br>@@ -1535,10 +1535,10 @@<br> static void coherent_ht_finalize(unsigned nodes)<br> {<br> unsigned node;<br>-#if !CONFIG_K8_REV_F_SUPPORT<br>+#if !IS_ENABLED(CONFIG_K8_REV_F_SUPPORT)<br> int rev_a0;<br> #endif<br>-#if CONFIG_LOGICAL_CPUS<br>+#if IS_ENABLED(CONFIG_LOGICAL_CPUS)<br> unsigned total_cpus;<br> <br> if (read_option(multi_core, 0) == 0) { /* multi_core */<br>@@ -1556,7 +1556,7 @@<br> */<br> <br> printk(BIOS_SPEW, "coherent_ht_finalize\n");<br>-#if !CONFIG_K8_REV_F_SUPPORT<br>+#if !IS_ENABLED(CONFIG_K8_REV_F_SUPPORT)<br> rev_a0 = is_cpu_rev_a0();<br> #endif<br> for (node = 0; node < nodes; node++) {<br>@@ -1567,7 +1567,7 @@<br> /* Set the Total CPU and Node count in the system */<br> val = pci_read_config32(dev, 0x60);<br> val &= (~0x000F0070);<br>-#if CONFIG_LOGICAL_CPUS<br>+#if IS_ENABLED(CONFIG_LOGICAL_CPUS)<br> val |= ((total_cpus-1)<<16)|((nodes-1)<<4);<br> #else<br> val |= ((nodes-1)<<16)|((nodes-1)<<4);<br>@@ -1587,7 +1587,7 @@<br> (3 << HTTC_HI_PRI_BYP_CNT_SHIFT);<br> pci_write_config32(dev, HT_TRANSACTION_CONTROL, val);<br> <br>-#if !CONFIG_K8_REV_F_SUPPORT<br>+#if !IS_ENABLED(CONFIG_K8_REV_F_SUPPORT)<br> if (rev_a0) {<br> pci_write_config32(dev, 0x94, 0);<br> pci_write_config32(dev, 0xb4, 0);<br>@@ -1607,7 +1607,7 @@<br> pci_devfn_t dev;<br> uint32_t cmd;<br> dev = NODE_MC(node);<br>-#if !CONFIG_K8_REV_F_SUPPORT<br>+#if !IS_ENABLED(CONFIG_K8_REV_F_SUPPORT)<br> if (is_cpu_pre_c0()) {<br> <br> /* Errata 66<br>@@ -1652,7 +1652,7 @@<br> #endif<br> <br> <br>-#if !CONFIG_K8_REV_F_SUPPORT<br>+#if !IS_ENABLED(CONFIG_K8_REV_F_SUPPORT)<br> /* I can't touch this msr on early buggy cpus, and cannot apply either 169 or 131 */<br> if (!is_cpu_pre_b3())<br> #endif<br>@@ -1770,7 +1770,7 @@<br> return needs_reset;<br> }<br> <br>-#if CONFIG_RAMINIT_SYSINFO<br>+#if IS_ENABLED(CONFIG_RAMINIT_SYSINFO)<br> void setup_coherent_ht_domain(void)<br> #else<br> int setup_coherent_ht_domain(void)<br>@@ -1792,7 +1792,7 @@<br> }<br> coherent_ht_finalize(nodes);<br> <br>-#if !CONFIG_RAMINIT_SYSINFO<br>+#if !IS_ENABLED(CONFIG_RAMINIT_SYSINFO)<br> return optimize_link_coherent_ht();<br> #endif<br> }<br>diff --git a/src/northbridge/amd/amdk8/debug.c b/src/northbridge/amd/amdk8/debug.c<br>index e1eade4..fd24bd5 100644<br>--- a/src/northbridge/amd/amdk8/debug.c<br>+++ b/src/northbridge/amd/amdk8/debug.c<br>@@ -11,7 +11,7 @@<br> <br> void print_debug_addr(const char *str, void *val)<br> {<br>-#if CONFIG_DEBUG_CAR<br>+#if IS_ENABLED(CONFIG_DEBUG_CAR)<br> printk(BIOS_DEBUG, "------Address debug: %s%p------\n", str, val);<br> #endif<br> }<br>@@ -63,7 +63,7 @@<br> printk(BIOS_DEBUG, "\n");<br> }<br> <br>-#if CONFIG_K8_REV_F_SUPPORT<br>+#if IS_ENABLED(CONFIG_K8_REV_F_SUPPORT)<br> void dump_pci_device_index_wait(unsigned dev, uint32_t index_reg)<br> {<br> int i;<br>@@ -135,7 +135,7 @@<br> }<br> }<br> <br>-#if CONFIG_DEBUG_SMBUS<br>+#if IS_ENABLED(CONFIG_DEBUG_SMBUS)<br> <br> void dump_spd_registers(const struct mem_controller *ctrl)<br> {<br>diff --git a/src/northbridge/amd/amdk8/incoherent_ht.c b/src/northbridge/amd/amdk8/incoherent_ht.c<br>index d65af96..c1b6802 100644<br>--- a/src/northbridge/amd/amdk8/incoherent_ht.c<br>+++ b/src/northbridge/amd/amdk8/incoherent_ht.c<br>@@ -131,8 +131,8 @@<br> <br> /* AMD K8 Unsupported 1GHz? */<br> if (id == (PCI_VENDOR_ID_AMD | (0x1100 << 16))) {<br>- #if CONFIG_K8_HT_FREQ_1G_SUPPORT<br>- #if !CONFIG_K8_REV_F_SUPPORT<br>+ #if IS_ENABLED(CONFIG_K8_HT_FREQ_1G_SUPPORT)<br>+ #if !IS_ENABLED(CONFIG_K8_REV_F_SUPPORT)<br> if (is_cpu_pre_e0()) { // only E0 later support 1GHz<br> freq_cap &= ~(1 << HT_FREQ_1000Mhz);<br> }<br>@@ -144,7 +144,7 @@<br> <br> printk(BIOS_SPEW, "pos=0x%x, filtered freq_cap=0x%x\n", pos, freq_cap);<br> <br>-#if CONFIG_SOUTHBRIDGE_VIA_SUBTYPE_K8M890<br>+#if IS_ENABLED(CONFIG_SOUTHBRIDGE_VIA_SUBTYPE_K8M890)<br> freq_cap &= 0x3f;<br> printk(BIOS_INFO, "Limiting HT to 800/600/400/200 MHz until K8M890 HT1000 is fixed.\n");<br> #endif<br>@@ -283,7 +283,7 @@<br> return needs_reset;<br> }<br> <br>-#if CONFIG_RAMINIT_SYSINFO<br>+#if IS_ENABLED(CONFIG_RAMINIT_SYSINFO)<br> static void ht_setup_chainx(pci_devfn_t udev, uint8_t upos, uint8_t bus,<br> unsigned offset_unitid, struct sys_info *sysinfo)<br> #else<br>@@ -296,7 +296,7 @@<br> uint8_t next_unitid, last_unitid;<br> unsigned uoffs;<br> <br>-#if !CONFIG_RAMINIT_SYSINFO<br>+#if !IS_ENABLED(CONFIG_RAMINIT_SYSINFO)<br> int reset_needed = 0;<br> #endif<br> <br>@@ -403,7 +403,7 @@<br> flags = pci_read_config16(dev, pos + PCI_CAP_FLAGS);<br> offs = ((flags>>10) & 1) ? PCI_HT_SLAVE1_OFFS : PCI_HT_SLAVE0_OFFS;<br> <br>- #if CONFIG_RAMINIT_SYSINFO<br>+ #if IS_ENABLED(CONFIG_RAMINIT_SYSINFO)<br> /* store the link pair here and we will Setup the Hypertransport link later, after we get final FID/VID */<br> {<br> struct link_pair_st *link_pair = &sysinfo->link_pair[sysinfo->link_pair_num];<br>@@ -439,7 +439,7 @@<br> flags |= CONFIG_HT_CHAIN_END_UNITID_BASE & 0x1f;<br> pci_write_config16(PCI_DEV(bus, real_last_unitid, 0), real_last_pos + PCI_CAP_FLAGS, flags);<br> <br>- #if CONFIG_RAMINIT_SYSINFO<br>+ #if IS_ENABLED(CONFIG_RAMINIT_SYSINFO)<br> // Here need to change the dev in the array<br> int i;<br> for (i = 0; i < sysinfo->link_pair_num; i++)<br>@@ -458,7 +458,7 @@<br> }<br> #endif<br> <br>-#if !CONFIG_RAMINIT_SYSINFO<br>+#if !IS_ENABLED(CONFIG_RAMINIT_SYSINFO)<br> return reset_needed;<br> #endif<br> <br>@@ -527,7 +527,7 @@<br> return reset_needed;<br> }<br> <br>-#if CONFIG_SOUTHBRIDGE_NVIDIA_CK804 // || CONFIG_SOUTHBRIDGE_NVIDIA_MCP55<br>+#if IS_ENABLED(CONFIG_SOUTHBRIDGE_NVIDIA_CK804)<br> static int set_ht_link_buffer_count(uint8_t node, uint8_t linkn, uint8_t linkt, unsigned val)<br> {<br> uint32_t dword;<br>@@ -587,7 +587,7 @@<br> }<br> #endif<br> <br>-#if CONFIG_RAMINIT_SYSINFO<br>+#if IS_ENABLED(CONFIG_RAMINIT_SYSINFO)<br> static void ht_setup_chains(uint8_t ht_c_num, struct sys_info *sysinfo)<br> #else<br> static int ht_setup_chains(uint8_t ht_c_num)<br>@@ -602,7 +602,7 @@<br> pci_devfn_t udev;<br> uint8_t i;<br> <br>-#if !CONFIG_RAMINIT_SYSINFO<br>+#if !IS_ENABLED(CONFIG_RAMINIT_SYSINFO)<br> int reset_needed = 0;<br> #else<br> sysinfo->link_pair_num = 0;<br>@@ -634,7 +634,7 @@<br> upos = ((reg & 0xf00)>>8) * 0x20 + 0x80;<br> udev = PCI_DEV(0, devpos, 0);<br> <br>-#if CONFIG_RAMINIT_SYSINFO<br>+#if IS_ENABLED(CONFIG_RAMINIT_SYSINFO)<br> ht_setup_chainx(udev,upos,busn, offset_unit_id(i == 0), sysinfo); // all not<br> #else<br> reset_needed |= ht_setup_chainx(udev,upos,busn, offset_unit_id(i == 0)); //all not<br>@@ -642,7 +642,7 @@<br> <br> }<br> <br>-#if !CONFIG_RAMINIT_SYSINFO<br>+#if !IS_ENABLED(CONFIG_RAMINIT_SYSINFO)<br> reset_needed |= optimize_link_read_pointers_chain(ht_c_num);<br> <br> return reset_needed;<br>@@ -650,7 +650,7 @@<br> <br> }<br> <br>-#if CONFIG_RAMINIT_SYSINFO<br>+#if IS_ENABLED(CONFIG_RAMINIT_SYSINFO)<br> static void ht_setup_chains_x(struct sys_info *sysinfo)<br> #else<br> static int ht_setup_chains_x(void)<br>@@ -662,7 +662,7 @@<br> uint8_t next_busn;<br> uint8_t ht_c_num;<br> uint8_t nodes;<br>-#if CONFIG_K8_ALLOCATE_IO_RANGE<br>+#if IS_ENABLED(CONFIG_K8_ALLOCATE_IO_RANGE)<br> unsigned next_io_base;<br> #endif<br> <br>@@ -672,7 +672,7 @@<br> reg = pci_read_config32(PCI_DEV(0, 0x18, 0), 0x64);<br> /* update PCI_DEV(0, 0x18, 1) 0xe0 to 0x05000m03, and next_busn = 0x3f+1 */<br> print_linkn_in("SBLink=", ((reg>>8) & 3));<br>-#if CONFIG_RAMINIT_SYSINFO<br>+#if IS_ENABLED(CONFIG_RAMINIT_SYSINFO)<br> sysinfo->sblk = (reg>>8) & 3;<br> sysinfo->sbbusn = 0;<br> sysinfo->nodes = nodes;<br>@@ -682,7 +682,7 @@<br> <br> next_busn = 0x3f+1; /* 0 will be used ht chain with SB we need to keep SB in bus0 in auto stage*/<br> <br>-#if CONFIG_K8_ALLOCATE_IO_RANGE<br>+#if IS_ENABLED(CONFIG_K8_ALLOCATE_IO_RANGE)<br> /* io range allocation */<br> tempreg = 0 | (((reg>>8) & 0x3) << 4)| (0x3<<12); //limit<br> pci_write_config32(PCI_DEV(0, 0x18, 1), 0xC4, tempreg);<br>@@ -695,7 +695,7 @@<br> for (ht_c_num = 1;ht_c_num < 4; ht_c_num++) {<br> pci_write_config32(PCI_DEV(0, 0x18, 1), 0xe0 + ht_c_num * 4, 0);<br> <br>-#if CONFIG_K8_ALLOCATE_IO_RANGE<br>+#if IS_ENABLED(CONFIG_K8_ALLOCATE_IO_RANGE)<br> /* io range allocation */<br> pci_write_config32(PCI_DEV(0, 0x18, 1), 0xc4 + ht_c_num * 8, 0);<br> pci_write_config32(PCI_DEV(0, 0x18, 1), 0xc0 + ht_c_num * 8, 0);<br>@@ -728,7 +728,7 @@<br> pci_write_config32(PCI_DEV(0, 0x18, 1), 0xe0 + ht_c_num * 4, tempreg);<br> next_busn+=0x3f+1;<br> <br>-#if CONFIG_K8_ALLOCATE_IO_RANGE<br>+#if IS_ENABLED(CONFIG_K8_ALLOCATE_IO_RANGE)<br> /* io range allocation */<br> tempreg = nodeid | (linkn<<4) | ((next_io_base+0x3)<<12); //limit<br> pci_write_config32(PCI_DEV(0, 0x18, 1), 0xC4 + ht_c_num * 8, tempreg);<br>@@ -752,7 +752,7 @@<br> pci_write_config32(dev, regpos, reg);<br> }<br> <br>-#if CONFIG_K8_ALLOCATE_IO_RANGE<br>+#if IS_ENABLED(CONFIG_K8_ALLOCATE_IO_RANGE)<br> /* io range allocation */<br> for (i = 0; i < 4; i++) {<br> unsigned regpos;<br>@@ -778,7 +778,7 @@<br> }<br> }<br> <br>-#if CONFIG_RAMINIT_SYSINFO<br>+#if IS_ENABLED(CONFIG_RAMINIT_SYSINFO)<br> sysinfo->ht_c_num = i;<br> ht_setup_chains(i, sysinfo);<br> sysinfo->sbdn = get_sbdn(sysinfo->sbbusn);<br>@@ -788,7 +788,7 @@<br> <br> }<br> <br>-#if CONFIG_RAMINIT_SYSINFO<br>+#if IS_ENABLED(CONFIG_RAMINIT_SYSINFO)<br> static int optimize_link_incoherent_ht(struct sys_info *sysinfo)<br> {<br> // We need to use recorded link pair info to optimize the link<br>diff --git a/src/northbridge/amd/amdk8/misc_control.c b/src/northbridge/amd/amdk8/misc_control.c<br>index 3cbeb04..c472edf 100644<br>--- a/src/northbridge/amd/amdk8/misc_control.c<br>+++ b/src/northbridge/amd/amdk8/misc_control.c<br>@@ -121,7 +121,7 @@<br> cmd = pci_read_config32(dev, 0x44);<br> cmd |= (1<<6) | (1<<25);<br> pci_write_config32(dev, 0x44, cmd);<br>-#if !CONFIG_K8_REV_F_SUPPORT<br>+#if !IS_ENABLED(CONFIG_K8_REV_F_SUPPORT)<br> if (is_cpu_pre_c0()) {<br> <br> /* Errata 58<br>diff --git a/src/northbridge/amd/amdk8/northbridge.c b/src/northbridge/amd/amdk8/northbridge.c<br>index c957af0..b001a0f 100644<br>--- a/src/northbridge/amd/amdk8/northbridge.c<br>+++ b/src/northbridge/amd/amdk8/northbridge.c<br>@@ -25,7 +25,7 @@<br> #include <cpu/amd/mtrr.h><br> <br> #include <cpu/amd/multicore.h><br>-#if CONFIG_LOGICAL_CPUS<br>+#if IS_ENABLED(CONFIG_LOGICAL_CPUS)<br> #include <pc80/mc146818rtc.h><br> #endif<br> <br>@@ -484,7 +484,7 @@<br> * we only deal with the 'first' vga card */<br> for (link = dev->link_list; link; link = link->next) {<br> if (link->bridge_ctrl & PCI_BRIDGE_CTL_VGA) {<br>-#if CONFIG_MULTIPLE_VGA_ADAPTERS<br>+#if IS_ENABLED(CONFIG_MULTIPLE_VGA_ADAPTERS)<br> extern device_t vga_pri; // the primary vga device, defined in device.c<br> printk(BIOS_DEBUG, "VGA: vga_pri bus num = %d link bus range [%d,%d]\n", vga_pri->bus->secondary,<br> link->secondary,link->subordinate);<br>@@ -811,10 +811,10 @@<br> <br> static void setup_uma_memory(void)<br> {<br>-#if CONFIG_GFXUMA<br>+#if IS_ENABLED(CONFIG_GFXUMA)<br> uint32_t topmem = (uint32_t) bsp_topmem();<br> <br>-#if !CONFIG_BOARD_ASROCK_939A785GMH && !CONFIG_BOARD_AMD_MAHOGANY<br>+#if !IS_ENABLED(CONFIG_BOARD_ASROCK_939A785GMH) && !CONFIG_BOARD_AMD_MAHOGANY<br> <br> switch (topmem) {<br> case 0x10000000: /* 256M system memory */<br>@@ -885,7 +885,7 @@<br> * if mmio_basek is bigger that hole_basek and will use hole_basek as mmio_basek and we don't need to reset hole.<br> * otherwise We reset the hole to the mmio_basek<br> */<br>- #if !CONFIG_K8_REV_F_SUPPORT<br>+ #if !IS_ENABLED(CONFIG_K8_REV_F_SUPPORT)<br> if (!is_cpu_pre_e0()) {<br> #endif<br> <br>@@ -903,7 +903,7 @@<br> disable_hoist_memory(mem_hole.hole_startk, mem_hole.node_id);<br> }<br> <br>- #if CONFIG_HW_MEM_HOLE_SIZE_AUTO_INC<br>+ #if IS_ENABLED(CONFIG_HW_MEM_HOLE_SIZE_AUTO_INC)<br> //We need to double check if the mmio_basek is valid for hole setting, if it is equal to basek, we need to decrease it some<br> u32 basek_pri;<br> for (i = 0; i < fx_devs; i++) {<br>@@ -924,7 +924,7 @@<br> #endif<br> }<br> <br>-#if !CONFIG_K8_REV_F_SUPPORT<br>+#if !IS_ENABLED(CONFIG_K8_REV_F_SUPPORT)<br> } // is_cpu_pre_e0<br> #endif<br> <br>@@ -953,7 +953,7 @@<br> }<br> <br> <br>-#if CONFIG_GFXUMA<br>+#if IS_ENABLED(CONFIG_GFXUMA)<br> printk(BIOS_DEBUG, "node %d : uma_memory_base/1024=0x%08llx, mmio_basek=0x%08lx, basek=0x%08x, limitk=0x%08x\n", i, uma_memory_base >> 10, mmio_basek, basek, limitk);<br> if ((uma_memory_base >> 10) < mmio_basek)<br> printk(BIOS_ALERT, "node %d: UMA memory starts below mmio_basek\n", i);<br>@@ -973,7 +973,7 @@<br> }<br> #if CONFIG_HW_MEM_HOLE_SIZEK != 0<br> if (reset_memhole)<br>- #if !CONFIG_K8_REV_F_SUPPORT<br>+ #if !IS_ENABLED(CONFIG_K8_REV_F_SUPPORT)<br> if (!is_cpu_pre_e0())<br> #endif<br> sizek += hoist_memory(mmio_basek,i);<br>@@ -998,7 +998,7 @@<br> ramtop = limitk * 1024;<br> }<br> <br>-#if CONFIG_GFXUMA<br>+#if IS_ENABLED(CONFIG_GFXUMA)<br> set_late_cbmem_top(uma_memory_base);<br> uma_resource(dev, 7, uma_memory_base >> 10, uma_memory_size >> 10);<br> #else<br>@@ -1128,7 +1128,7 @@<br> sysconf.apicid_offset = bsp_apicid;<br> <br> disable_siblings = !CONFIG_LOGICAL_CPUS;<br>-#if CONFIG_LOGICAL_CPUS<br>+#if IS_ENABLED(CONFIG_LOGICAL_CPUS)<br> get_option(&disable_siblings, "multi_core");<br> #endif<br> <br>@@ -1201,7 +1201,7 @@<br> // That is the typical case<br> <br> if (j == 0) {<br>- #if !CONFIG_K8_REV_F_SUPPORT<br>+ #if !IS_ENABLED(CONFIG_K8_REV_F_SUPPORT)<br> e0_later_single_core = is_e0_later_in_bsp(i); // single core<br> #else<br> e0_later_single_core = is_cpu_f0_in_bsp(i); // We can read cpuid(1) from Func3<br>@@ -1250,7 +1250,7 @@<br> <br> static void cpu_bus_init(device_t dev)<br> {<br>-#if CONFIG_WAIT_BEFORE_CPUS_INIT<br>+#if IS_ENABLED(CONFIG_WAIT_BEFORE_CPUS_INIT)<br> cpus_ready_for_init();<br> #endif<br> initialize_cpus(dev->link_list);<br>diff --git a/src/northbridge/amd/amdk8/raminit.c b/src/northbridge/amd/amdk8/raminit.c<br>index 43229ea..dae1584 100644<br>--- a/src/northbridge/amd/amdk8/raminit.c<br>+++ b/src/northbridge/amd/amdk8/raminit.c<br>@@ -15,7 +15,7 @@<br> #include <reset.h><br> #include "raminit.h"<br> #include "amdk8.h"<br>-#if CONFIG_HAVE_OPTION_TABLE<br>+#if IS_ENABLED(CONFIG_HAVE_OPTION_TABLE)<br> #include "option_table.h"<br> #endif<br> <br>@@ -43,7 +43,7 @@<br> return pci_read_config32(ctrl->f0, 0) == 0x11001022;<br> }<br> <br>-#if CONFIG_RAMINIT_SYSINFO<br>+#if IS_ENABLED(CONFIG_RAMINIT_SYSINFO)<br> void sdram_set_registers(const struct mem_controller *ctrl, struct sys_info *sysinfo)<br> #else<br> void sdram_set_registers(const struct mem_controller *ctrl)<br>@@ -592,7 +592,7 @@<br> unsigned long side2;<br> unsigned long rows;<br> unsigned long col;<br>-#if CONFIG_QRANK_DIMM_SUPPORT<br>+#if IS_ENABLED(CONFIG_QRANK_DIMM_SUPPORT)<br> unsigned long rank;<br> #endif<br> };<br>@@ -606,7 +606,7 @@<br> sz.side2 = 0;<br> sz.rows = 0;<br> sz.col = 0;<br>-#if CONFIG_QRANK_DIMM_SUPPORT<br>+#if IS_ENABLED(CONFIG_QRANK_DIMM_SUPPORT)<br> sz.rank = 0;<br> #endif<br> <br>@@ -650,7 +650,7 @@<br> if ((value != 2) && (value != 4)) {<br> goto val_err;<br> }<br>-#if CONFIG_QRANK_DIMM_SUPPORT<br>+#if IS_ENABLED(CONFIG_QRANK_DIMM_SUPPORT)<br> sz.rank = value;<br> #endif<br> <br>@@ -679,7 +679,7 @@<br> sz.side2 = 0;<br> sz.rows = 0;<br> sz.col = 0;<br>-#if CONFIG_QRANK_DIMM_SUPPORT<br>+#if IS_ENABLED(CONFIG_QRANK_DIMM_SUPPORT)<br> sz.rank = 0;<br> #endif<br> out:<br>@@ -727,7 +727,7 @@<br> /* Set the appropriate DIMM base address register */<br> pci_write_config32(ctrl->f2, DRAM_CSBASE + (((index << 1)+0)<<2), base0);<br> pci_write_config32(ctrl->f2, DRAM_CSBASE + (((index << 1)+1)<<2), base1);<br>-#if CONFIG_QRANK_DIMM_SUPPORT<br>+#if IS_ENABLED(CONFIG_QRANK_DIMM_SUPPORT)<br> if (sz.rank == 4) {<br> pci_write_config32(ctrl->f2, DRAM_CSBASE + (((index << 1)+4)<<2), base0);<br> pci_write_config32(ctrl->f2, DRAM_CSBASE + (((index << 1)+5)<<2), base1);<br>@@ -738,7 +738,7 @@<br> if (base0) {<br> dch = pci_read_config32(ctrl->f2, DRAM_CONFIG_HIGH);<br> dch |= DCH_MEMCLK_EN0 << index;<br>-#if CONFIG_QRANK_DIMM_SUPPORT<br>+#if IS_ENABLED(CONFIG_QRANK_DIMM_SUPPORT)<br> if (sz.rank == 4) {<br> dch |= DCH_MEMCLK_EN0 << (index + 2);<br> }<br>@@ -760,7 +760,7 @@<br> <br> map = pci_read_config32(ctrl->f2, DRAM_BANK_ADDR_MAP);<br> map &= ~(0xf << (index * 4));<br>-#if CONFIG_QRANK_DIMM_SUPPORT<br>+#if IS_ENABLED(CONFIG_QRANK_DIMM_SUPPORT)<br> if (sz.rank == 4) {<br> map &= ~(0xf << ((index + 2) * 4));<br> }<br>@@ -771,7 +771,7 @@<br> if (sz.side1 >= (25 +3)) {<br> if (is_cpu_pre_d0()) {<br> map |= (sz.side1 - (25 + 3)) << (index *4);<br>-#if CONFIG_QRANK_DIMM_SUPPORT<br>+#if IS_ENABLED(CONFIG_QRANK_DIMM_SUPPORT)<br> if (sz.rank == 4) {<br> map |= (sz.side1 - (25 + 3)) << ((index + 2) * 4);<br> }<br>@@ -779,7 +779,7 @@<br> }<br> else {<br> map |= cs_map_aa[(sz.rows - 12) * 5 + (sz.col - 8) ] << (index*4);<br>-#if CONFIG_QRANK_DIMM_SUPPORT<br>+#if IS_ENABLED(CONFIG_QRANK_DIMM_SUPPORT)<br> if (sz.rank == 4) {<br> map |= cs_map_aa[(sz.rows - 12) * 5 + (sz.col - 8) ] << ((index + 2) * 4);<br> }<br>@@ -1164,7 +1164,7 @@<br> if (unbuffered) {<br> if ((has_dualch) && (!is_cpu_pre_d0())) {<br> dcl |= DCL_UnBuffDimm;<br>-#if CONFIG_CPU_AMD_SOCKET_939<br>+#if IS_ENABLED(CONFIG_CPU_AMD_SOCKET_939)<br> if ((cpuid_eax(1) & 0x30) == 0x30) {<br> /* CS[7:4] is copy of CS[3:0], should be set for 939 socket */<br> dcl |= DCL_UpperCSMap;<br>@@ -1375,7 +1375,7 @@<br> static int spd_dimm_loading_socket(const struct mem_controller *ctrl, long dimm_mask, int *freq_1t)<br> {<br> <br>-#if CONFIG_CPU_AMD_SOCKET_939<br>+#if IS_ENABLED(CONFIG_CPU_AMD_SOCKET_939)<br> <br> /* + 1 raise so we detect 0 as bad field */<br> #define DDR200 (NBCAP_MEMCLK_100MHZ + 1)<br>@@ -1488,7 +1488,7 @@<br> return NBCAP_MEMCLK_200MHZ;<br> }<br> <br>-#elif CONFIG_CPU_AMD_SOCKET_754<br>+#elif IS_ENABLED(CONFIG_CPU_AMD_SOCKET_754)<br> <br> #define CFGIDX(DIMM1,DIMM2,DIMM3) ((DIMM3)*9+(DIMM2)*3+(DIMM1))<br> <br>@@ -1657,7 +1657,7 @@<br> if (freq == sizeof(cl_at_freq))<br> goto hw_error;<br> <br>-#if CONFIG_CPU_AMD_SOCKET_754<br>+#if IS_ENABLED(CONFIG_CPU_AMD_SOCKET_754)<br> if (freq < max_freq_1t || CONFIG_K8_FORCE_2T_DRAM_TIMING) {<br> pci_write_config32(ctrl->f2, DRAM_CONFIG_LOW,<br> pci_read_config32(ctrl->f2, DRAM_CONFIG_LOW) | DCL_En2T);<br>@@ -1899,7 +1899,7 @@<br> {<br> uint32_t dcl;<br> int value;<br>-#if CONFIG_QRANK_DIMM_SUPPORT<br>+#if IS_ENABLED(CONFIG_QRANK_DIMM_SUPPORT)<br> int rank;<br> #endif<br> int dimm;<br>@@ -1908,7 +1908,7 @@<br> return -1;<br> }<br> <br>-#if CONFIG_QRANK_DIMM_SUPPORT<br>+#if IS_ENABLED(CONFIG_QRANK_DIMM_SUPPORT)<br> rank = spd_read_byte(ctrl->channel0[i], 5); /* number of physical banks */<br> if (rank < 0) {<br> return -1;<br>@@ -1916,7 +1916,7 @@<br> #endif<br> <br> dimm = 1<<(DCL_x4DIMM_SHIFT+i);<br>-#if CONFIG_QRANK_DIMM_SUPPORT<br>+#if IS_ENABLED(CONFIG_QRANK_DIMM_SUPPORT)<br> if (rank == 4) {<br> dimm |= 1<<(DCL_x4DIMM_SHIFT+i+2);<br> }<br>@@ -2168,7 +2168,7 @@<br> return dimm_mask;<br> }<br> <br>-#if CONFIG_RAMINIT_SYSINFO<br>+#if IS_ENABLED(CONFIG_RAMINIT_SYSINFO)<br> void sdram_set_spd_registers(const struct mem_controller *ctrl, struct sys_info *sysinfo)<br> #else<br> void sdram_set_spd_registers(const struct mem_controller *ctrl)<br>@@ -2277,7 +2277,7 @@<br> hole_startk = 4*1024*1024 - CONFIG_HW_MEM_HOLE_SIZEK;<br> <br> printk(BIOS_SPEW, "Handling memory hole at 0x%08x (default)\n", hole_startk);<br>-#if CONFIG_HW_MEM_HOLE_SIZE_AUTO_INC<br>+#if IS_ENABLED(CONFIG_HW_MEM_HOLE_SIZE_AUTO_INC)<br> /* We need to double check if hole_startk is valid.<br> * If it is equal to the dram base address in K (base_k),<br> * we need to decrease it.<br>@@ -2327,7 +2327,7 @@<br> <br> #endif<br> <br>-#if CONFIG_RAMINIT_SYSINFO<br>+#if IS_ENABLED(CONFIG_RAMINIT_SYSINFO)<br> void sdram_enable(int controllers, const struct mem_controller *ctrl, struct sys_info *sysinfo)<br> #else<br> void sdram_enable(int controllers, const struct mem_controller *ctrl)<br>diff --git a/src/northbridge/amd/amdk8/raminit.h b/src/northbridge/amd/amdk8/raminit.h<br>index 0f4636b..4db0862 100644<br>--- a/src/northbridge/amd/amdk8/raminit.h<br>+++ b/src/northbridge/amd/amdk8/raminit.h<br>@@ -26,7 +26,7 @@<br> <br> #define TIMEOUT_LOOPS 300000<br> <br>-#if defined(__PRE_RAM__) && CONFIG_RAMINIT_SYSINFO<br>+#if defined(__PRE_RAM__) && IS_ENABLED(CONFIG_RAMINIT_SYSINFO)<br> void sdram_initialize(int controllers, const struct mem_controller *ctrl, void *sysinfo);<br> void sdram_enable(int controllers, const struct mem_controller *ctrl,<br> struct sys_info *sysinfo);<br>diff --git a/src/northbridge/amd/amdk8/raminit_f.c b/src/northbridge/amd/amdk8/raminit_f.c<br>index a979896..39c5ad8 100644<br>--- a/src/northbridge/amd/amdk8/raminit_f.c<br>+++ b/src/northbridge/amd/amdk8/raminit_f.c<br>@@ -33,11 +33,11 @@<br> #include "raminit.h"<br> #include "f.h"<br> #include <spd_ddr2.h><br>-#if CONFIG_HAVE_OPTION_TABLE<br>+#if IS_ENABLED(CONFIG_HAVE_OPTION_TABLE)<br> #include "option_table.h"<br> #endif<br> <br>-#if CONFIG_DEBUG_RAM_SETUP<br>+#if IS_ENABLED(CONFIG_DEBUG_RAM_SETUP)<br> #define printk_raminit(args...) printk(BIOS_DEBUG, args)<br> #else<br> #define printk_raminit(args...)<br>@@ -845,7 +845,7 @@<br> /* Set the appropriate DIMM base address register */<br> pci_write_config32(ctrl->f2, DRAM_CSBASE + (((index << 1) + 0) << 2), base0);<br> pci_write_config32(ctrl->f2, DRAM_CSBASE + (((index << 1) + 1) << 2), base1);<br>-#if CONFIG_QRANK_DIMM_SUPPORT<br>+#if IS_ENABLED(CONFIG_QRANK_DIMM_SUPPORT)<br> if (sz->rank == 4) {<br> pci_write_config32(ctrl->f2, DRAM_CSBASE + (((index << 1) + 4) << 2), base0);<br> pci_write_config32(ctrl->f2, DRAM_CSBASE + (((index << 1) + 5) << 2), base1);<br>@@ -873,7 +873,7 @@<br> } else {<br> dword = pci_read_config32(ctrl->f2, DRAM_TIMING_LOW); //Channel A<br> dword &= ~(ClkDis0 >> index);<br>-#if CONFIG_QRANK_DIMM_SUPPORT<br>+#if IS_ENABLED(CONFIG_QRANK_DIMM_SUPPORT)<br> if (sz->rank == 4) {<br> dword &= ~(ClkDis0 >> (index+2));<br> }<br>@@ -883,7 +883,7 @@<br> if (meminfo->is_Width128) { // ChannelA+B<br> dword = pci_read_config32(ctrl->f2, DRAM_CTRL_MISC);<br> dword &= ~(ClkDis0 >> index);<br>-#if CONFIG_QRANK_DIMM_SUPPORT<br>+#if IS_ENABLED(CONFIG_QRANK_DIMM_SUPPORT)<br> if (sz->rank == 4) {<br> dword &= ~(ClkDis0 >> (index+2));<br> }<br>@@ -936,7 +936,7 @@<br> }<br> map = pci_read_config32(ctrl->f2, DRAM_BANK_ADDR_MAP);<br> map &= ~(0xf << (index * 4));<br>-#if CONFIG_QRANK_DIMM_SUPPORT<br>+#if IS_ENABLED(CONFIG_QRANK_DIMM_SUPPORT)<br> if (sz->rank == 4) {<br> map &= ~(0xf << ((index + 2) * 4));<br> }<br>@@ -947,7 +947,7 @@<br> unsigned temp_map;<br> temp_map = cs_map_aaa[(sz->bank-2)*3*4 + (sz->rows - 13)*3 + (sz->col - 9) ];<br> map |= temp_map << (index*4);<br>-#if CONFIG_QRANK_DIMM_SUPPORT<br>+#if IS_ENABLED(CONFIG_QRANK_DIMM_SUPPORT)<br> if (sz->rank == 4) {<br> map |= temp_map << ((index + 2) * 4);<br> }<br>@@ -1291,7 +1291,7 @@<br> } else {<br> pci_write_config32(ctrl->f2, DRAM_CSBASE + (((index << 1) + 0) << 2), 0);<br> pci_write_config32(ctrl->f2, DRAM_CSBASE + (((index << 1) + 1) << 2), 0);<br>-#if CONFIG_QRANK_DIMM_SUPPORT<br>+#if IS_ENABLED(CONFIG_QRANK_DIMM_SUPPORT)<br> if (meminfo->sz[index].rank == 4) {<br> pci_write_config32(ctrl->f2, DRAM_CSBASE + (((index << 1) + 4) << 2), 0);<br> pci_write_config32(ctrl->f2, DRAM_CSBASE + (((index << 1) + 5) << 2), 0);<br>@@ -2173,7 +2173,7 @@<br> static void set_4RankRDimm(const struct mem_controller *ctrl,<br> const struct mem_param *param, struct mem_info *meminfo)<br> {<br>-#if CONFIG_QRANK_DIMM_SUPPORT<br>+#if IS_ENABLED(CONFIG_QRANK_DIMM_SUPPORT)<br> int value;<br> int i;<br> long dimm_mask = meminfo->dimm_mask;<br>@@ -2213,7 +2213,7 @@<br> uint32_t mask_single_rank;<br> uint32_t mask_page_1k;<br> int value;<br>-#if CONFIG_QRANK_DIMM_SUPPORT<br>+#if IS_ENABLED(CONFIG_QRANK_DIMM_SUPPORT)<br> int rank;<br> #endif<br> <br>@@ -2246,20 +2246,20 @@<br> <br> value = spd_read_byte(spd_device, SPD_PRI_WIDTH);<br> <br>- #if CONFIG_QRANK_DIMM_SUPPORT<br>+ #if IS_ENABLED(CONFIG_QRANK_DIMM_SUPPORT)<br> rank = meminfo->sz[i].rank;<br> #endif<br> <br> if (value == 4) {<br> mask_x4 |= (1<<i);<br>- #if CONFIG_QRANK_DIMM_SUPPORT<br>+ #if IS_ENABLED(CONFIG_QRANK_DIMM_SUPPORT)<br> if (rank == 4) {<br> mask_x4 |= 1<<(i+2);<br> }<br> #endif<br> } else if (value == 16) {<br> mask_x16 |= (1<<i);<br>- #if CONFIG_QRANK_DIMM_SUPPORT<br>+ #if IS_ENABLED(CONFIG_QRANK_DIMM_SUPPORT)<br> if (rank == 4) {<br> mask_x16 |= 1<<(i+2);<br> }<br>@@ -2348,7 +2348,7 @@<br> dcl &= ~DCL_DimmEccEn;<br> }<br> #else // CMOS_VSTART_ECC_memory not defined<br>-#if !CONFIG_ECC_MEMORY<br>+#if !IS_ENABLED(CONFIG_ECC_MEMORY)<br> dcl &= ~DCL_DimmEccEn;<br> #endif<br> #endif<br>@@ -2932,7 +2932,7 @@<br> hole_startk = 4*1024*1024 - CONFIG_HW_MEM_HOLE_SIZEK;<br> <br> printk_raminit("Handling memory hole at 0x%08x (default)\n", hole_startk);<br>-#if CONFIG_HW_MEM_HOLE_SIZE_AUTO_INC<br>+#if IS_ENABLED(CONFIG_HW_MEM_HOLE_SIZE_AUTO_INC)<br> /* We need to double check if the hole_startk is valid, if it is equal<br> to basek, we need to decrease it some */<br> uint32_t basek_pri;<br>diff --git a/src/northbridge/amd/amdk8/raminit_f_dqs.c b/src/northbridge/amd/amdk8/raminit_f_dqs.c<br>index c470b25..64b0c64 100644<br>--- a/src/northbridge/amd/amdk8/raminit_f_dqs.c<br>+++ b/src/northbridge/amd/amdk8/raminit_f_dqs.c<br>@@ -1782,7 +1782,7 @@<br> #endif<br> }<br> <br>-#if CONFIG_HAVE_ACPI_RESUME<br>+#if IS_ENABLED(CONFIG_HAVE_ACPI_RESUME)<br> <br> #if CONFIG_MEM_TRAIN_SEQ == 0<br> static int save_index_to_pos(unsigned int dev, int size, int index, int nvram_pos)<br>@@ -1937,7 +1937,7 @@<br> if (train_DqsRcvrEn(ctrl+i, 2, sysinfo)) goto out;<br> printk(BIOS_DEBUG, " done\n");<br> sysinfo->mem_trained[i]=1;<br>-#if CONFIG_HAVE_ACPI_RESUME<br>+#if IS_ENABLED(CONFIG_HAVE_ACPI_RESUME)<br> dqs_save_MC_NVRAM((ctrl+i)->f2);<br> #endif<br> }<br>diff --git a/src/northbridge/amd/amdmct/wrappers/mcti_d.c b/src/northbridge/amd/amdmct/wrappers/mcti_d.c<br>index 0b08c20..306f3a7 100644<br>--- a/src/northbridge/amd/amdmct/wrappers/mcti_d.c<br>+++ b/src/northbridge/amd/amdmct/wrappers/mcti_d.c<br>@@ -128,16 +128,16 @@<br> //val = 2; /* S4 (Unbuffered SO-DIMMS) */<br> break;<br> case NV_BYPMAX:<br>-#if !CONFIG_GFXUMA<br>+#if !IS_ENABLED(CONFIG_GFXUMA)<br> val = 4;<br>-#elif CONFIG_GFXUMA<br>+#elif IS_ENABLED(CONFIG_GFXUMA)<br> val = 7;<br> #endif<br> break;<br> case NV_RDWRQBYP:<br>-#if !CONFIG_GFXUMA<br>+#if !IS_ENABLED(CONFIG_GFXUMA)<br> val = 2;<br>-#elif CONFIG_GFXUMA<br>+#elif IS_ENABLED(CONFIG_GFXUMA)<br> val = 3;<br> #endif<br> break;<br>@@ -191,9 +191,9 @@<br> val = !!nvram;<br> break;<br> case NV_BurstLen32:<br>-#if !CONFIG_GFXUMA<br>+#if !IS_ENABLED(CONFIG_GFXUMA)<br> val = 0; /* 64 byte mode */<br>-#elif CONFIG_GFXUMA<br>+#elif IS_ENABLED(CONFIG_GFXUMA)<br> val = 1; /* 32 byte mode */<br> #endif<br> break;<br>@@ -212,9 +212,9 @@<br> case NV_BottomIO:<br> case NV_BottomUMA:<br> /* address bits [31:24] */<br>-#if !CONFIG_GFXUMA<br>+#if !IS_ENABLED(CONFIG_GFXUMA)<br> val = (CONFIG_MMCONF_BASE_ADDRESS >> 24);<br>-#elif CONFIG_GFXUMA<br>+#elif IS_ENABLED(CONFIG_GFXUMA)<br> #if (CONFIG_MMCONF_BASE_ADDRESS < (MAXIMUM_GFXUMA_SIZE + MINIMUM_DRAM_BELOW_4G))<br> #error "MMCONF_BASE_ADDRESS is too small"<br> #endif<br>diff --git a/src/northbridge/amd/cimx/rd890/NbPlatform.h b/src/northbridge/amd/cimx/rd890/NbPlatform.h<br>index 9e75cb6..3efa84d 100644<br>--- a/src/northbridge/amd/cimx/rd890/NbPlatform.h<br>+++ b/src/northbridge/amd/cimx/rd890/NbPlatform.h<br>@@ -26,7 +26,7 @@<br> <br> #ifdef CIMX_TRACE_SUPPORT<br> #define CIMX_INIT_TRACE(Arguments)<br>- #if CONFIG_REDIRECT_NBCIMX_TRACE_TO_SERIAL<br>+ #if IS_ENABLED(CONFIG_REDIRECT_NBCIMX_TRACE_TO_SERIAL)<br> #define TRACE_DATA(Ptr, Level) BIOS_DEBUG //always enable<br> #define CIMX_TRACE(Argument) do {do_printk Argument;} while (0)<br> #else<br>diff --git a/src/northbridge/amd/pi/00630F01/northbridge.c b/src/northbridge/amd/pi/00630F01/northbridge.c<br>index 5ba0e44..42df652 100644<br>--- a/src/northbridge/amd/pi/00630F01/northbridge.c<br>+++ b/src/northbridge/amd/pi/00630F01/northbridge.c<br>@@ -46,7 +46,7 @@<br> <br> #define MAX_NODE_NUMS (MAX_NODES * MAX_DIES)<br> <br>-#if (defined CONFIG_EXT_CONF_SUPPORT) && CONFIG_EXT_CONF_SUPPORT == 1<br>+#if (defined CONFIG_EXT_CONF_SUPPORT) && IS_ENABLED(CONFIG_EXT_CONF_SUPPORT)<br> #error CONFIG_EXT_CONF_SUPPORT == 1 not support anymore!<br> #endif<br> <br>diff --git a/src/northbridge/amd/pi/00660F01/northbridge.c b/src/northbridge/amd/pi/00660F01/northbridge.c<br>index f085d5c..f964c04 100644<br>--- a/src/northbridge/amd/pi/00660F01/northbridge.c<br>+++ b/src/northbridge/amd/pi/00660F01/northbridge.c<br>@@ -45,7 +45,7 @@<br> <br> #define MAX_NODE_NUMS (MAX_NODES * MAX_DIES)<br> <br>-#if (defined CONFIG_EXT_CONF_SUPPORT) && CONFIG_EXT_CONF_SUPPORT == 1<br>+#if (defined CONFIG_EXT_CONF_SUPPORT) && IS_ENABLED(CONFIG_EXT_CONF_SUPPORT)<br> #error CONFIG_EXT_CONF_SUPPORT == 1 not support anymore!<br> #endif<br> <br>@@ -381,7 +381,7 @@<br> * we only deal with the 'first' vga card */<br> for (link = dev->link_list; link; link = link->next) {<br> if (link->bridge_ctrl & PCI_BRIDGE_CTL_VGA) {<br>-#if CONFIG_MULTIPLE_VGA_ADAPTERS<br>+#if IS_ENABLED(CONFIG_MULTIPLE_VGA_ADAPTERS)<br> extern device_t vga_pri; // the primary vga device, defined in device.c<br> printk(BIOS_DEBUG, "VGA: vga_pri bus num = %d bus range [%d,%d]\n", vga_pri->bus->secondary,<br> link->secondary,link->subordinate);<br>diff --git a/src/northbridge/amd/pi/00670F00/northbridge.c b/src/northbridge/amd/pi/00670F00/northbridge.c<br>index 006bc48..02c4d72 100644<br>--- a/src/northbridge/amd/pi/00670F00/northbridge.c<br>+++ b/src/northbridge/amd/pi/00670F00/northbridge.c<br>@@ -45,7 +45,7 @@<br> <br> #define MAX_NODE_NUMS (MAX_NODES * MAX_DIES)<br> <br>-#if (defined CONFIG_EXT_CONF_SUPPORT) && CONFIG_EXT_CONF_SUPPORT == 1<br>+#if (defined CONFIG_EXT_CONF_SUPPORT) && IS_ENABLED(CONFIG_EXT_CONF_SUPPORT)<br> #error CONFIG_EXT_CONF_SUPPORT == 1 not support anymore!<br> #endif<br> <br>@@ -381,7 +381,7 @@<br> * we only deal with the 'first' vga card */<br> for (link = dev->link_list; link; link = link->next) {<br> if (link->bridge_ctrl & PCI_BRIDGE_CTL_VGA) {<br>-#if CONFIG_MULTIPLE_VGA_ADAPTERS<br>+#if IS_ENABLED(CONFIG_MULTIPLE_VGA_ADAPTERS)<br> extern device_t vga_pri; // the primary vga device, defined in device.c<br> printk(BIOS_DEBUG, "VGA: vga_pri bus num = %d bus range [%d,%d]\n", vga_pri->bus->secondary,<br> link->secondary,link->subordinate);<br>diff --git a/src/northbridge/amd/pi/00730F01/northbridge.c b/src/northbridge/amd/pi/00730F01/northbridge.c<br>index 960078e..de2059d 100644<br>--- a/src/northbridge/amd/pi/00730F01/northbridge.c<br>+++ b/src/northbridge/amd/pi/00730F01/northbridge.c<br>@@ -391,7 +391,7 @@<br> * we only deal with the 'first' vga card */<br> for (link = dev->link_list; link; link = link->next) {<br> if (link->bridge_ctrl & PCI_BRIDGE_CTL_VGA) {<br>-#if CONFIG_MULTIPLE_VGA_ADAPTERS<br>+#if IS_ENABLED(CONFIG_MULTIPLE_VGA_ADAPTERS)<br> extern device_t vga_pri; // the primary vga device, defined in device.c<br> printk(BIOS_DEBUG, "VGA: vga_pri bus num = %d bus range [%d,%d]\n", vga_pri->bus->secondary,<br> link->secondary,link->subordinate);<br></pre><p>To view, visit <a href="https://review.coreboot.org/20345">change 20345</a>. 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<div style="display:none"> Gerrit-Project: coreboot </div>
<div style="display:none"> Gerrit-Branch: master </div>
<div style="display:none"> Gerrit-MessageType: newchange </div>
<div style="display:none"> Gerrit-Change-Id: I763cbbc31dcd4cdd128c04793a742ab6daaf5f0c </div>
<div style="display:none"> Gerrit-Change-Number: 20345 </div>
<div style="display:none"> Gerrit-PatchSet: 1 </div>
<div style="display:none"> Gerrit-Owner: Martin Roth <martinroth@google.com> </div>