<p>Martin Roth has uploaded this change for <strong>review</strong>.</p><p><a href="https://review.coreboot.org/20355">View Change</a></p><pre style="font-family: monospace,monospace; white-space: pre-wrap;">src/soc: add IS_ENABLED() around Kconfig symbol references<br><br>Change-Id: I2e7b756296e861e08cea846297f687a880daaf45<br>Signed-off-by: Martin Roth <martinroth@google.com><br>---<br>M src/soc/broadcom/cygnus/ddr_init.c<br>M src/soc/dmp/vortex86ex/ide_sd_sata.c<br>M src/soc/dmp/vortex86ex/raminit.c<br>M src/soc/dmp/vortex86ex/southbridge.c<br>M src/soc/mediatek/mt8173/i2c.c<br>M src/soc/mediatek/mt8173/include/soc/dramc_pi_api.h<br>M src/soc/mediatek/mt8173/mt6391.c<br>M src/soc/nvidia/tegra210/include/soc/mtc.h<br>M src/soc/nvidia/tegra210/romstage.c<br>9 files changed, 53 insertions(+), 53 deletions(-)<br><br></pre><pre style="font-family: monospace,monospace; white-space: pre-wrap;">git pull ssh://review.coreboot.org:29418/coreboot refs/changes/55/20355/1</pre><pre style="font-family: monospace,monospace; white-space: pre-wrap;">diff --git a/src/soc/broadcom/cygnus/ddr_init.c b/src/soc/broadcom/cygnus/ddr_init.c<br>index 5c4c985..1a5fd86 100644<br>--- a/src/soc/broadcom/cygnus/ddr_init.c<br>+++ b/src/soc/broadcom/cygnus/ddr_init.c<br>@@ -475,7 +475,7 @@<br> {<br> int ddr32 = 0;<br> <br>-#if (CONFIG_CYGNUS_SHMOO_REUSE_DDR_32BIT)<br>+#if IS_ENABLED(CONFIG_CYGNUS_SHMOO_REUSE_DDR_32BIT)<br> ddr32=1;<br> #endif /* (CONFIG_CYGNUS_SHMOO_REUSE_DDR_32BIT) */<br> <br>@@ -966,7 +966,7 @@<br> reg = (uint32_t *)(*flptr++);<br> val = (uint32_t *)(*flptr++);<br> if ( (((uint32_t)reg >= DDR_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE_RD_EN) && ((uint32_t)reg <= (DDR_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE_RD_EN + 0x114)))<br>-#if (CONFIG_CYGNUS_SHMOO_REUSE_DDR_32BIT || defined(CONFIG_NS_PLUS))<br>+#if IS_ENABLED(CONFIG_CYGNUS_SHMOO_REUSE_DDR_32BIT) || defined(CONFIG_NS_PLUS)<br> || (((uint32_t)reg >= DDR_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE_RD_EN) && ((uint32_t)reg <= (DDR_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE_RD_EN + 0x114)))<br> #endif<br> #ifdef CONFIG_IPROC_DDR_ECC<br>@@ -1068,7 +1068,7 @@<br> *ptr++ = val;<br> chksum += val;<br> }<br>-#if (CONFIG_CYGNUS_SHMOO_REUSE_DDR_32BIT || defined(CONFIG_NS_PLUS))<br>+#if IS_ENABLED(CONFIG_CYGNUS_SHMOO_REUSE_DDR_32BIT) || defined(CONFIG_NS_PLUS)<br> if (is_ddr_32bit()) {<br> for (i=0; i<sizeof(ddr_phy_wl_regs) / sizeof(ddr_phy_wl_regs[0]); i++) {<br> reg = (uint32_t)DDR_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE_RD_EN + ddr_phy_wl_regs[i];<br>@@ -1479,7 +1479,7 @@<br> }<br> }<br> <br>-#if CONFIG_CYGNUS_DDR_AUTO_SELF_REFRESH_ENABLE<br>+#if IS_ENABLED(CONFIG_CYGNUS_DDR_AUTO_SELF_REFRESH_ENABLE)<br> #if (DDR_AUTO_SELF_REFRESH_IDLE_COUNT > 0) & (DDR_AUTO_SELF_REFRESH_IDLE_COUNT <= 0xff)<br> /* Enable auto self-refresh */<br> reg32_set_bits((unsigned int *)DDR_DENALI_CTL_57,<br>diff --git a/src/soc/dmp/vortex86ex/ide_sd_sata.c b/src/soc/dmp/vortex86ex/ide_sd_sata.c<br>index 936505e..c60018a 100644<br>--- a/src/soc/dmp/vortex86ex/ide_sd_sata.c<br>+++ b/src/soc/dmp/vortex86ex/ide_sd_sata.c<br>@@ -80,20 +80,20 @@<br> u16 ata_timing_pri, ata_timing_sec;<br> u32 ata_timing_reg32;<br> /* Primary channel is SD. */<br>-#if CONFIG_IDE1_ENABLE<br>+#if IS_ENABLED(CONFIG_IDE1_ENABLE)<br> ata_timing_pri = 0x8000;<br> #else<br> ata_timing_pri = 0x0000; // Disable this channel.<br> #endif<br> /* Secondary channel is SATA. */<br>-#if CONFIG_IDE2_ENABLE<br>+#if IS_ENABLED(CONFIG_IDE2_ENABLE)<br> ata_timing_sec = 0xa30f; // This setting value works well.<br> #else<br> ata_timing_sec = 0x0000; // Disable this channel.<br> #endif<br> ata_timing_reg32 = (ata_timing_sec << 16) | ata_timing_pri;<br> pci_write_config32(dev, 0x40, ata_timing_reg32);<br>-#if CONFIG_IDE_NATIVE_MODE<br>+#if IS_ENABLED(CONFIG_IDE_NATIVE_MODE)<br> /* Set both IDE channels to native mode. */<br> u8 prog_if;<br> prog_if = pci_read_config8(dev, 0x09);<br>@@ -110,7 +110,7 @@<br> <br> static void setup_std_ide_compatible(struct device *dev)<br> {<br>-#if CONFIG_IDE_STANDARD_COMPATIBLE<br>+#if IS_ENABLED(CONFIG_IDE_STANDARD_COMPATIBLE)<br> // Misc Control Register (MCR) Offset 90h<br> // bit 0 = Vendor ID Access, bit 1 = Device ID Access.<br> u8 mcr;<br>diff --git a/src/soc/dmp/vortex86ex/raminit.c b/src/soc/dmp/vortex86ex/raminit.c<br>index 1ccdb27..0d4b5b5 100644<br>--- a/src/soc/dmp/vortex86ex/raminit.c<br>+++ b/src/soc/dmp/vortex86ex/raminit.c<br>@@ -253,7 +253,7 @@<br> <br> static void print_ddr3_memory_setup(void)<br> {<br>-#if CONFIG_DEBUG_RAM_SETUP<br>+#if IS_ENABLED(CONFIG_DEBUG_RAM_SETUP)<br> printk(BIOS_DEBUG, "DDR3 Timing Reg 0-3:\n");<br> printk(BIOS_DEBUG, "NB 6e : ");<br> print_debug_hex16(pci_read_config16(NB, 0x6e));<br>diff --git a/src/soc/dmp/vortex86ex/southbridge.c b/src/soc/dmp/vortex86ex/southbridge.c<br>index 05702d1..451aea6 100644<br>--- a/src/soc/dmp/vortex86ex/southbridge.c<br>+++ b/src/soc/dmp/vortex86ex/southbridge.c<br>@@ -207,7 +207,7 @@<br> ext_int_routing |= irq_to_int_routing[CAN_IRQ] << CAN_IRQ_SHIFT;<br> ext_int_routing |= irq_to_int_routing[HDA_IRQ] << HDA_IRQ_SHIFT;<br> ext_int_routing |= irq_to_int_routing[USBD_IRQ] << USBD_IRQ_SHIFT;<br>-#if CONFIG_IDE_NATIVE_MODE<br>+#if IS_ENABLED(CONFIG_IDE_NATIVE_MODE)<br> /* IDE in native mode, only uses one IRQ. */<br> ext_int_routing |= irq_to_int_routing[0] << SIDE_IRQ_SHIFT;<br> ext_int_routing |= irq_to_int_routing[PIDE_IRQ] << PIDE_IRQ_SHIFT;<br>@@ -250,21 +250,21 @@<br> {<br> u32 lpt_reg = 0;<br> <br>-#if CONFIG_LPT_ENABLE<br>+#if IS_ENABLED(CONFIG_LPT_ENABLE)<br> int ppmod = 0;<br>-#if CONFIG_LPT_MODE_BPP<br>+#if IS_ENABLED(CONFIG_LPT_MODE_BPP)<br> ppmod = 0;<br>-#elif CONFIG_LPT_MODE_EPP_19_AND_SPP<br>+#elif IS_ENABLED(CONFIG_LPT_MODE_EPP_19_AND_SPP)<br> ppmod = 1;<br>-#elif CONFIG_LPT_MODE_ECP<br>+#elif IS_ENABLED(CONFIG_LPT_MODE_ECP)<br> ppmod = 2;<br>-#elif CONFIG_LPT_MODE_ECP_AND_EPP_19<br>+#elif IS_ENABLED(CONFIG_LPT_MODE_ECP_AND_EPP_19)<br> ppmod = 3;<br>-#elif CONFIG_LPT_MODE_SPP<br>+#elif IS_ENABLED(CONFIG_LPT_MODE_SPP)<br> ppmod = 4;<br>-#elif CONFIG_LPT_MODE_EPP_17_AND_SPP<br>+#elif IS_ENABLED(CONFIG_LPT_MODE_EPP_17_AND_SPP)<br> ppmod = 5;<br>-#elif CONFIG_LPT_MODE_ECP_AND_EPP_17<br>+#elif IS_ENABLED(CONFIG_LPT_MODE_ECP_AND_EPP_17)<br> ppmod = 7;<br> #else<br> #error CONFIG_LPT_MODE error.<br>@@ -303,67 +303,67 @@<br> * Bit 31-16 : DBA, GPIO direction base address.<br> * Bit 15-0 : DPBA, GPIO data port base address.<br> * */<br>-#if CONFIG_GPIO_P0_ENABLE<br>+#if IS_ENABLED(CONFIG_GPIO_P0_ENABLE)<br> SETUP_GPIO_ADDR(0)<br> #endif<br>-#if CONFIG_GPIO_P1_ENABLE<br>+#if IS_ENABLED(CONFIG_GPIO_P1_ENABLE)<br> SETUP_GPIO_ADDR(1)<br> #endif<br>-#if CONFIG_GPIO_P2_ENABLE<br>+#if IS_ENABLED(CONFIG_GPIO_P2_ENABLE)<br> SETUP_GPIO_ADDR(2)<br> #endif<br>-#if CONFIG_GPIO_P3_ENABLE<br>+#if IS_ENABLED(CONFIG_GPIO_P3_ENABLE)<br> SETUP_GPIO_ADDR(3)<br> #endif<br>-#if CONFIG_GPIO_P4_ENABLE<br>+#if IS_ENABLED(CONFIG_GPIO_P4_ENABLE)<br> SETUP_GPIO_ADDR(4)<br> #endif<br>-#if CONFIG_GPIO_P5_ENABLE<br>+#if IS_ENABLED(CONFIG_GPIO_P5_ENABLE)<br> SETUP_GPIO_ADDR(5)<br> #endif<br>-#if CONFIG_GPIO_P6_ENABLE<br>+#if IS_ENABLED(CONFIG_GPIO_P6_ENABLE)<br> SETUP_GPIO_ADDR(6)<br> #endif<br>-#if CONFIG_GPIO_P7_ENABLE<br>+#if IS_ENABLED(CONFIG_GPIO_P7_ENABLE)<br> SETUP_GPIO_ADDR(7)<br> #endif<br>-#if CONFIG_GPIO_P8_ENABLE<br>+#if IS_ENABLED(CONFIG_GPIO_P8_ENABLE)<br> SETUP_GPIO_ADDR(8)<br> #endif<br>-#if CONFIG_GPIO_P9_ENABLE<br>+#if IS_ENABLED(CONFIG_GPIO_P9_ENABLE)<br> SETUP_GPIO_ADDR(9)<br> #endif<br> /* Enable GPIO port 0~9. */<br> outl(gpio_enable_mask, base);<br> /* Set GPIO port 0-9 initial dir and data. */<br>-#if CONFIG_GPIO_P0_ENABLE<br>+#if IS_ENABLED(CONFIG_GPIO_P0_ENABLE)<br> INIT_GPIO(0)<br> #endif<br>-#if CONFIG_GPIO_P1_ENABLE<br>+#if IS_ENABLED(CONFIG_GPIO_P1_ENABLE)<br> INIT_GPIO(1)<br> #endif<br>-#if CONFIG_GPIO_P2_ENABLE<br>+#if IS_ENABLED(CONFIG_GPIO_P2_ENABLE)<br> INIT_GPIO(2)<br> #endif<br>-#if CONFIG_GPIO_P3_ENABLE<br>+#if IS_ENABLED(CONFIG_GPIO_P3_ENABLE)<br> INIT_GPIO(3)<br> #endif<br>-#if CONFIG_GPIO_P4_ENABLE<br>+#if IS_ENABLED(CONFIG_GPIO_P4_ENABLE)<br> INIT_GPIO(4)<br> #endif<br>-#if CONFIG_GPIO_P5_ENABLE<br>+#if IS_ENABLED(CONFIG_GPIO_P5_ENABLE)<br> INIT_GPIO(5)<br> #endif<br>-#if CONFIG_GPIO_P6_ENABLE<br>+#if IS_ENABLED(CONFIG_GPIO_P6_ENABLE)<br> INIT_GPIO(6)<br> #endif<br>-#if CONFIG_GPIO_P7_ENABLE<br>+#if IS_ENABLED(CONFIG_GPIO_P7_ENABLE)<br> INIT_GPIO(7)<br> #endif<br>-#if CONFIG_GPIO_P8_ENABLE<br>+#if IS_ENABLED(CONFIG_GPIO_P8_ENABLE)<br> INIT_GPIO(8)<br> #endif<br>-#if CONFIG_GPIO_P9_ENABLE<br>+#if IS_ENABLED(CONFIG_GPIO_P9_ENABLE)<br> INIT_GPIO(9)<br> #endif<br> /* Disable GPIO Port Config IO Base Address. */<br>@@ -391,34 +391,34 @@<br> /* S/B register 61h - 60h : UART Config IO Base Address */<br> pci_write_config16(dev, SB_REG_UART_CFG_IO_BASE, base | 1);<br> /* setup UART */<br>-#if CONFIG_UART1_ENABLE<br>+#if IS_ENABLED(CONFIG_UART1_ENABLE)<br> SETUP_UART(1)<br> #endif<br>-#if CONFIG_UART2_ENABLE<br>+#if IS_ENABLED(CONFIG_UART2_ENABLE)<br> SETUP_UART(2)<br> #endif<br>-#if CONFIG_UART3_ENABLE<br>+#if IS_ENABLED(CONFIG_UART3_ENABLE)<br> SETUP_UART(3)<br> #endif<br>-#if CONFIG_UART4_ENABLE<br>+#if IS_ENABLED(CONFIG_UART4_ENABLE)<br> SETUP_UART(4)<br> #endif<br>-#if CONFIG_UART5_ENABLE<br>+#if IS_ENABLED(CONFIG_UART5_ENABLE)<br> SETUP_UART(5)<br> #endif<br>-#if CONFIG_UART6_ENABLE<br>+#if IS_ENABLED(CONFIG_UART6_ENABLE)<br> SETUP_UART(6)<br> #endif<br>-#if CONFIG_UART7_ENABLE<br>+#if IS_ENABLED(CONFIG_UART7_ENABLE)<br> SETUP_UART(7)<br> #endif<br>-#if CONFIG_UART8_ENABLE<br>+#if IS_ENABLED(CONFIG_UART8_ENABLE)<br> SETUP_UART(8)<br> #endif<br>-#if CONFIG_UART9_ENABLE<br>+#if IS_ENABLED(CONFIG_UART9_ENABLE)<br> SETUP_UART(9)<br> #endif<br>-#if CONFIG_UART10_ENABLE<br>+#if IS_ENABLED(CONFIG_UART10_ENABLE)<br> SETUP_UART(10)<br> #endif<br> /* Keep UART Config I/O base address */<br>diff --git a/src/soc/mediatek/mt8173/i2c.c b/src/soc/mediatek/mt8173/i2c.c<br>index 6c04ec3..f07ffc9 100644<br>--- a/src/soc/mediatek/mt8173/i2c.c<br>+++ b/src/soc/mediatek/mt8173/i2c.c<br>@@ -70,7 +70,7 @@<br> <br> #define I2CTAG "[I2C][PL] "<br> <br>-#if CONFIG_DEBUG_I2C<br>+#if IS_ENABLED(CONFIG_DEBUG_I2C)<br> #define I2CLOG(fmt, arg...) printk(BIOS_INFO, I2CTAG fmt, ##arg)<br> #else<br> #define I2CLOG(fmt, arg...)<br>diff --git a/src/soc/mediatek/mt8173/include/soc/dramc_pi_api.h b/src/soc/mediatek/mt8173/include/soc/dramc_pi_api.h<br>index 1411d39..8d449f7 100644<br>--- a/src/soc/mediatek/mt8173/include/soc/dramc_pi_api.h<br>+++ b/src/soc/mediatek/mt8173/include/soc/dramc_pi_api.h<br>@@ -178,7 +178,7 @@<br> void tx_delay_for_wrleveling(u32 channel, struct dqs_perbit_dly *dqdqs_perbit_dly,<br> u8 *ave_dqdly_byte, u8 *max_dqsdly_byte);<br> <br>-#if CONFIG_DEBUG_DRAM<br>+#if IS_ENABLED(CONFIG_DEBUG_DRAM)<br> #define dramc_dbg_msg(_x_...) printk(BIOS_DEBUG, _x_)<br> #else<br> #define dramc_dbg_msg(_x_...)<br>diff --git a/src/soc/mediatek/mt8173/mt6391.c b/src/soc/mediatek/mt8173/mt6391.c<br>index ec7fabc..9ba3503 100644<br>--- a/src/soc/mediatek/mt8173/mt6391.c<br>+++ b/src/soc/mediatek/mt8173/mt6391.c<br>@@ -21,7 +21,7 @@<br> #include <soc/pmic_wrap.h><br> #include <types.h><br> <br>-#if CONFIG_DEBUG_PMIC<br>+#if IS_ENABLED(CONFIG_DEBUG_PMIC)<br> #define DEBUG_PMIC(level, x...) printk(level, x)<br> #else<br> #define DEBUG_PMIC(level, x...)<br>diff --git a/src/soc/nvidia/tegra210/include/soc/mtc.h b/src/soc/nvidia/tegra210/include/soc/mtc.h<br>index fa07f33..ca369ad 100644<br>--- a/src/soc/nvidia/tegra210/include/soc/mtc.h<br>+++ b/src/soc/nvidia/tegra210/include/soc/mtc.h<br>@@ -18,7 +18,7 @@<br> <br> #include <boot/coreboot_tables.h><br> <br>-#if CONFIG_HAVE_MTC<br>+#if IS_ENABLED(CONFIG_HAVE_MTC)<br> <br> int tegra210_run_mtc(void);<br> void soc_add_mtc(struct lb_header *header);<br>diff --git a/src/soc/nvidia/tegra210/romstage.c b/src/soc/nvidia/tegra210/romstage.c<br>index 9491570..7b6444d 100644<br>--- a/src/soc/nvidia/tegra210/romstage.c<br>+++ b/src/soc/nvidia/tegra210/romstage.c<br>@@ -45,7 +45,7 @@<br> <br> printk(BIOS_INFO, "T210: romstage here\n");<br> <br>-#if CONFIG_BOOTROM_SDRAM_INIT<br>+#if IS_ENABLED(CONFIG_BOOTROM_SDRAM_INIT)<br> printk(BIOS_INFO, "T210 romstage: SDRAM init done by BootROM, RAMCODE = %d\n",<br> sdram_get_ram_code());<br> #else<br></pre><p>To view, visit <a href="https://review.coreboot.org/20355">change 20355</a>. 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<div style="display:none"> Gerrit-Project: coreboot </div>
<div style="display:none"> Gerrit-Branch: master </div>
<div style="display:none"> Gerrit-MessageType: newchange </div>
<div style="display:none"> Gerrit-Change-Id: I2e7b756296e861e08cea846297f687a880daaf45 </div>
<div style="display:none"> Gerrit-Change-Number: 20355 </div>
<div style="display:none"> Gerrit-PatchSet: 1 </div>
<div style="display:none"> Gerrit-Owner: Martin Roth <martinroth@google.com> </div>