<p>Martin Roth has uploaded this change for <strong>review</strong>.</p><p><a href="https://review.coreboot.org/20336">View Change</a></p><pre style="font-family: monospace,monospace; white-space: pre-wrap;">cpu/intel: add IS_ENABLED() around Kconfig symbol references<br><br>Some of these can be changed from #if to if(), but that will happen<br>in a follow-on commmit.<br><br>Change-Id: Ie685bbbb1cbf06d32631ea40ad120b6f45374b2e<br>Signed-off-by: Martin Roth <martinroth@google.com><br>---<br>M src/cpu/intel/fsp_model_206ax/model_206ax_init.c<br>M src/cpu/intel/haswell/bootblock.c<br>M src/cpu/intel/haswell/romstage.c<br>M src/cpu/intel/hyperthreading/intel_sibling.c<br>M src/cpu/intel/model_2065x/bootblock.c<br>M src/cpu/intel/model_2065x/model_2065x_init.c<br>M src/cpu/intel/model_206ax/bootblock.c<br>M src/cpu/intel/model_206ax/model_206ax_init.c<br>M src/cpu/intel/turbo/turbo.c<br>9 files changed, 13 insertions(+), 12 deletions(-)<br><br></pre><pre style="font-family: monospace,monospace; white-space: pre-wrap;">git pull ssh://review.coreboot.org:29418/coreboot refs/changes/36/20336/1</pre><pre style="font-family: monospace,monospace; white-space: pre-wrap;">diff --git a/src/cpu/intel/fsp_model_206ax/model_206ax_init.c b/src/cpu/intel/fsp_model_206ax/model_206ax_init.c<br>index aedd467..be1f28b 100644<br>--- a/src/cpu/intel/fsp_model_206ax/model_206ax_init.c<br>+++ b/src/cpu/intel/fsp_model_206ax/model_206ax_init.c<br>@@ -316,7 +316,7 @@<br> cpu->path.apic.apic_id,<br> new->path.apic.apic_id);<br> <br>-#if CONFIG_SMP && CONFIG_MAX_CPUS > 1<br>+#if IS_ENABLED(CONFIG_SMP) && CONFIG_MAX_CPUS > 1<br> /* Start the new CPU */<br> if (!start_cpu(new)) {<br> /* Record the error in cpu? */<br>diff --git a/src/cpu/intel/haswell/bootblock.c b/src/cpu/intel/haswell/bootblock.c<br>index 0522f94..57e1bbb 100644<br>--- a/src/cpu/intel/haswell/bootblock.c<br>+++ b/src/cpu/intel/haswell/bootblock.c<br>@@ -24,7 +24,7 @@<br> #include <cpu/intel/microcode/microcode.c><br> #include "haswell.h"<br> <br>-#if CONFIG_SOUTHBRIDGE_INTEL_LYNXPOINT<br>+#if IS_ENABLED(CONFIG_SOUTHBRIDGE_INTEL_LYNXPOINT)<br> /* Needed for RCBA access to set Soft Reset Data register */<br> #include <southbridge/intel/lynxpoint/pch.h><br> #else<br>diff --git a/src/cpu/intel/haswell/romstage.c b/src/cpu/intel/haswell/romstage.c<br>index ac45ee6..c6162dc 100644<br>--- a/src/cpu/intel/haswell/romstage.c<br>+++ b/src/cpu/intel/haswell/romstage.c<br>@@ -34,7 +34,7 @@<br> #include <romstage_handoff.h><br> #include <reset.h><br> #include <vendorcode/google/chromeos/chromeos.h><br>-#if CONFIG_EC_GOOGLE_CHROMEEC<br>+#if IS_ENABLED(CONFIG_EC_GOOGLE_CHROMEEC)<br> #include <ec/google/chromeec/ec.h><br> #endif<br> #include "haswell.h"<br>@@ -182,7 +182,7 @@<br> <br> wake_from_s3 = early_pch_init(params->gpio_map, params->rcba_config);<br> <br>-#if CONFIG_EC_GOOGLE_CHROMEEC<br>+#if IS_ENABLED(CONFIG_EC_GOOGLE_CHROMEEC)<br> /* Ensure the EC is in the right mode for recovery */<br> google_chromeec_early_init();<br> #endif<br>@@ -197,7 +197,7 @@<br> printk(BIOS_DEBUG, "Back from haswell_early_initialization()\n");<br> <br> if (wake_from_s3) {<br>-#if CONFIG_HAVE_ACPI_RESUME<br>+#if IS_ENABLED(CONFIG_HAVE_ACPI_RESUME)<br> printk(BIOS_DEBUG, "Resume from S3 detected.\n");<br> #else<br> printk(BIOS_DEBUG, "Resume from S3 detected, but disabled.\n");<br>@@ -239,7 +239,7 @@<br> /* Save data returned from MRC on non-S3 resumes. */<br> save_mrc_data(params->pei_data);<br> } else if (cbmem_initialize()) {<br>- #if CONFIG_HAVE_ACPI_RESUME<br>+ #if IS_ENABLED(CONFIG_HAVE_ACPI_RESUME)<br> /* Failed S3 resume, reset to come up cleanly */<br> reset_system();<br> #endif<br>diff --git a/src/cpu/intel/hyperthreading/intel_sibling.c b/src/cpu/intel/hyperthreading/intel_sibling.c<br>index 57aa00c..d965470 100644<br>--- a/src/cpu/intel/hyperthreading/intel_sibling.c<br>+++ b/src/cpu/intel/hyperthreading/intel_sibling.c<br>@@ -20,7 +20,7 @@<br> #include <smp/spinlock.h><br> #include <assert.h><br> <br>-#if CONFIG_PARALLEL_CPU_INIT<br>+#if IS_ENABLED(CONFIG_PARALLEL_CPU_INIT)<br> #error Intel hyper-threading requires serialized CPU init<br> #endif<br> <br>diff --git a/src/cpu/intel/model_2065x/bootblock.c b/src/cpu/intel/model_2065x/bootblock.c<br>index a57f166..ed528d1 100644<br>--- a/src/cpu/intel/model_2065x/bootblock.c<br>+++ b/src/cpu/intel/model_2065x/bootblock.c<br>@@ -23,7 +23,7 @@<br> <br> #include <cpu/intel/microcode/microcode.c><br> <br>-#if CONFIG_SOUTHBRIDGE_INTEL_IBEXPEAK<br>+#if IS_ENABLED(CONFIG_SOUTHBRIDGE_INTEL_IBEXPEAK)<br> #include <southbridge/intel/ibexpeak/pch.h><br> #include "model_2065x.h"<br> #else<br>diff --git a/src/cpu/intel/model_2065x/model_2065x_init.c b/src/cpu/intel/model_2065x/model_2065x_init.c<br>index fe095c4..f7e6c1d 100644<br>--- a/src/cpu/intel/model_2065x/model_2065x_init.c<br>+++ b/src/cpu/intel/model_2065x/model_2065x_init.c<br>@@ -295,7 +295,7 @@<br> cpu->path.apic.apic_id,<br> new->path.apic.apic_id);<br> <br>-#if CONFIG_SMP && CONFIG_MAX_CPUS > 1<br>+#if IS_ENABLED(CONFIG_SMP) && CONFIG_MAX_CPUS > 1<br> /* Start the new CPU */<br> if (!start_cpu(new)) {<br> /* Record the error in cpu? */<br>diff --git a/src/cpu/intel/model_206ax/bootblock.c b/src/cpu/intel/model_206ax/bootblock.c<br>index 493d089..670b097 100644<br>--- a/src/cpu/intel/model_206ax/bootblock.c<br>+++ b/src/cpu/intel/model_206ax/bootblock.c<br>@@ -24,7 +24,8 @@<br> #include <cpu/intel/microcode/microcode.c><br> #include "model_206ax.h"<br> <br>-#if CONFIG_SOUTHBRIDGE_INTEL_BD82X6X || CONFIG_SOUTHBRIDGE_INTEL_C216<br>+#if IS_ENABLED(CONFIG_SOUTHBRIDGE_INTEL_BD82X6X) || \<br>+ IS_ENABLED(CONFIG_SOUTHBRIDGE_INTEL_C216)<br> /* Needed for RCBA access to set Soft Reset Data register */<br> #include <southbridge/intel/bd82x6x/pch.h><br> #else<br>diff --git a/src/cpu/intel/model_206ax/model_206ax_init.c b/src/cpu/intel/model_206ax/model_206ax_init.c<br>index 2722454..589f3b6 100644<br>--- a/src/cpu/intel/model_206ax/model_206ax_init.c<br>+++ b/src/cpu/intel/model_206ax/model_206ax_init.c<br>@@ -489,7 +489,7 @@<br> cpu->path.apic.apic_id,<br> new->path.apic.apic_id);<br> <br>-#if CONFIG_SMP && CONFIG_MAX_CPUS > 1<br>+#if IS_ENABLED(CONFIG_SMP) && CONFIG_MAX_CPUS > 1<br> /* Start the new CPU */<br> if (!start_cpu(new)) {<br> /* Record the error in cpu? */<br>diff --git a/src/cpu/intel/turbo/turbo.c b/src/cpu/intel/turbo/turbo.c<br>index 3fae3f0..9b93870 100644<br>--- a/src/cpu/intel/turbo/turbo.c<br>+++ b/src/cpu/intel/turbo/turbo.c<br>@@ -19,7 +19,7 @@<br> #include <cpu/x86/msr.h><br> #include <arch/cpu.h><br> <br>-#if CONFIG_CPU_INTEL_TURBO_NOT_PACKAGE_SCOPED<br>+#if IS_ENABLED(CONFIG_CPU_INTEL_TURBO_NOT_PACKAGE_SCOPED)<br> static inline int get_global_turbo_state(void)<br> {<br> return TURBO_UNKNOWN;<br></pre><p>To view, visit <a href="https://review.coreboot.org/20336">change 20336</a>. To unsubscribe, visit <a href="https://review.coreboot.org/settings">settings</a>.</p><div itemscope itemtype="http://schema.org/EmailMessage"><div itemscope itemprop="action" itemtype="http://schema.org/ViewAction"><link itemprop="url" href="https://review.coreboot.org/20336"/><meta itemprop="name" content="View Change"/></div></div>
<div style="display:none"> Gerrit-Project: coreboot </div>
<div style="display:none"> Gerrit-Branch: master </div>
<div style="display:none"> Gerrit-MessageType: newchange </div>
<div style="display:none"> Gerrit-Change-Id: Ie685bbbb1cbf06d32631ea40ad120b6f45374b2e </div>
<div style="display:none"> Gerrit-Change-Number: 20336 </div>
<div style="display:none"> Gerrit-PatchSet: 1 </div>
<div style="display:none"> Gerrit-Owner: Martin Roth <martinroth@google.com> </div>