<p>Martin Roth has uploaded this change for <strong>review</strong>.</p><p><a href="https://review.coreboot.org/20342">View Change</a></p><pre style="font-family: monospace,monospace; white-space: pre-wrap;">mainboard/[a-e]: add IS_ENABLED() around Kconfig symbol references<br><br>Change-Id: Icca8bac5e67f83dfc5a8f5ef1cb87c6432e0a236<br>Signed-off-by: Martin Roth <martinroth@google.com><br>---<br>M src/mainboard/advansus/a785e-i/get_bus_conf.c<br>M src/mainboard/advansus/a785e-i/romstage.c<br>M src/mainboard/amd/bettong/BiosCallOuts.c<br>M src/mainboard/amd/bimini_fam10/romstage.c<br>M src/mainboard/amd/dbm690t/romstage.c<br>M src/mainboard/amd/dinar/rd890_cfg.h<br>M src/mainboard/amd/dinar/sb700_cfg.h<br>M src/mainboard/amd/gardenia/BiosCallOuts.c<br>M src/mainboard/amd/inagua/broadcom.c<br>M src/mainboard/amd/mahogany/romstage.c<br>M src/mainboard/amd/mahogany_fam10/romstage.c<br>M src/mainboard/amd/parmer/buildOpts.c<br>M src/mainboard/amd/pistachio/romstage.c<br>M src/mainboard/amd/serengeti_cheetah/mptable.c<br>M src/mainboard/amd/serengeti_cheetah/romstage.c<br>M src/mainboard/amd/serengeti_cheetah_fam10/mptable.c<br>M src/mainboard/amd/serengeti_cheetah_fam10/romstage.c<br>M src/mainboard/amd/thatcher/buildOpts.c<br>M src/mainboard/amd/tilapia_fam10/romstage.c<br>M src/mainboard/amd/torpedo/Oem.h<br>M src/mainboard/amd/torpedo/platform_cfg.h<br>M src/mainboard/aopen/dxplplusu/romstage.c<br>M src/mainboard/apple/macbook21/gpio.c<br>M src/mainboard/apple/macbook21/hda_verb.c<br>M src/mainboard/asrock/939a785gmh/romstage.c<br>M src/mainboard/asus/a8n_e/romstage.c<br>M src/mainboard/asus/a8v-e_deluxe/romstage.c<br>M src/mainboard/asus/a8v-e_se/romstage.c<br>M src/mainboard/asus/f2a85-m/acpi/routing.asl<br>M src/mainboard/asus/f2a85-m/buildOpts.c<br>M src/mainboard/asus/k8v-x/romstage.c<br>M src/mainboard/asus/kcma-d8/bootblock.c<br>M src/mainboard/asus/kfsn4-dre/bootblock.c<br>M src/mainboard/asus/kfsn4-dre_k8/bootblock.c<br>M src/mainboard/asus/kfsn4-dre_k8/get_bus_conf.c<br>M src/mainboard/asus/kgpe-d16/bootblock.c<br>M src/mainboard/asus/m2n-e/romstage.c<br>M src/mainboard/asus/m2v-mx_se/romstage.c<br>M src/mainboard/asus/m2v/romstage.c<br>M src/mainboard/asus/m4a78-em/romstage.c<br>M src/mainboard/asus/m4a785-m/romstage.c<br>M src/mainboard/asus/m5a88-v/get_bus_conf.c<br>M src/mainboard/asus/m5a88-v/romstage.c<br>M src/mainboard/avalue/eax-785e/get_bus_conf.c<br>M src/mainboard/avalue/eax-785e/romstage.c<br>M src/mainboard/broadcom/blast/mptable.c<br>M src/mainboard/broadcom/blast/romstage.c<br>M src/mainboard/dmp/vortex86ex/romstage.c<br>M src/mainboard/emulation/qemu-i440fx/northbridge.c<br>49 files changed, 98 insertions(+), 95 deletions(-)<br><br></pre><pre style="font-family: monospace,monospace; white-space: pre-wrap;">git pull ssh://review.coreboot.org:29418/coreboot refs/changes/42/20342/1</pre><pre style="font-family: monospace,monospace; white-space: pre-wrap;">diff --git a/src/mainboard/advansus/a785e-i/get_bus_conf.c b/src/mainboard/advansus/a785e-i/get_bus_conf.c<br>index 9bd7c25..ed46359 100644<br>--- a/src/mainboard/advansus/a785e-i/get_bus_conf.c<br>+++ b/src/mainboard/advansus/a785e-i/get_bus_conf.c<br>@@ -21,7 +21,7 @@<br> #include <stdlib.h><br> #include <cpu/amd/multicore.h><br> #include <cpu/amd/amdfam10_sysconf.h><br>-#if CONFIG_AMD_SB_CIMX<br>+#if IS_ENABLED(CONFIG_AMD_SB_CIMX)<br> #include <sb_cimx.h><br> #endif<br> <br>@@ -128,7 +128,7 @@<br> apicid_base = CONFIG_MAX_PHYSICAL_CPUS;<br> apicid_sb800 = apicid_base + 0;<br> <br>-#if CONFIG_AMD_SB_CIMX<br>+#if IS_ENABLED(CONFIG_AMD_SB_CIMX)<br> sb_Late_Post();<br> #endif<br> }<br>diff --git a/src/mainboard/advansus/a785e-i/romstage.c b/src/mainboard/advansus/a785e-i/romstage.c<br>index f145c25..7161903 100644<br>--- a/src/mainboard/advansus/a785e-i/romstage.c<br>+++ b/src/mainboard/advansus/a785e-i/romstage.c<br>@@ -144,7 +144,7 @@<br> */<br> wait_all_core0_started();<br> <br>-#if CONFIG_LOGICAL_CPUS<br>+#if IS_ENABLED(CONFIG_LOGICAL_CPUS)<br> /* Core0 on each node is configured. Now setup any additional cores. */<br> printk(BIOS_DEBUG, "start_other_cores()\n");<br> start_other_cores(bsp_apicid);<br>@@ -158,7 +158,7 @@<br> rs780_early_setup();<br> sb800_early_setup();<br> <br>-#if CONFIG_SET_FIDVID<br>+#if IS_ENABLED(CONFIG_SET_FIDVID)<br> msr = rdmsr(0xc0010071);<br> printk(BIOS_DEBUG, "\nBegin FIDVID MSR 0xc0010071 0x%08x 0x%08x\n", msr.hi, msr.lo);<br> post_code(0x39);<br>diff --git a/src/mainboard/amd/bettong/BiosCallOuts.c b/src/mainboard/amd/bettong/BiosCallOuts.c<br>index e5eed05..7073ec7 100644<br>--- a/src/mainboard/amd/bettong/BiosCallOuts.c<br>+++ b/src/mainboard/amd/bettong/BiosCallOuts.c<br>@@ -83,7 +83,7 @@<br> #endif<br> <br> /* XHCI configuration */<br>-#if CONFIG_HUDSON_XHCI_ENABLE<br>+#if IS_ENABLED(CONFIG_HUDSON_XHCI_ENABLE)<br> FchParams_env->Usb.Xhci0Enable = TRUE;<br> #else<br> FchParams_env->Usb.Xhci0Enable = FALSE;<br>diff --git a/src/mainboard/amd/bimini_fam10/romstage.c b/src/mainboard/amd/bimini_fam10/romstage.c<br>index cdb12e3..53cc648 100644<br>--- a/src/mainboard/amd/bimini_fam10/romstage.c<br>+++ b/src/mainboard/amd/bimini_fam10/romstage.c<br>@@ -136,7 +136,7 @@<br> */<br> wait_all_core0_started();<br> <br>-#if CONFIG_LOGICAL_CPUS<br>+#if IS_ENABLED(CONFIG_LOGICAL_CPUS)<br> /* Core0 on each node is configured. Now setup any additional cores. */<br> printk(BIOS_DEBUG, "start_other_cores()\n");<br> start_other_cores(bsp_apicid);<br>@@ -150,7 +150,7 @@<br> rs780_early_setup();<br> sb800_early_setup();<br> <br>-#if CONFIG_SET_FIDVID<br>+#if IS_ENABLED(CONFIG_SET_FIDVID)<br> msr = rdmsr(0xc0010071);<br> printk(BIOS_DEBUG, "\nBegin FIDVID MSR 0xc0010071 0x%08x 0x%08x\n", msr.hi, msr.lo);<br> <br>diff --git a/src/mainboard/amd/dbm690t/romstage.c b/src/mainboard/amd/dbm690t/romstage.c<br>index b4a3d12..5c841cb 100644<br>--- a/src/mainboard/amd/dbm690t/romstage.c<br>+++ b/src/mainboard/amd/dbm690t/romstage.c<br>@@ -88,7 +88,7 @@<br> <br> setup_coherent_ht_domain();<br> <br>-#if CONFIG_LOGICAL_CPUS<br>+#if IS_ENABLED(CONFIG_LOGICAL_CPUS)<br> /* It is said that we should start core1 after all core0 launched */<br> wait_all_core0_started();<br> start_other_cores();<br>diff --git a/src/mainboard/amd/dinar/rd890_cfg.h b/src/mainboard/amd/dinar/rd890_cfg.h<br>index 8645553..ac3c818 100644<br>--- a/src/mainboard/amd/dinar/rd890_cfg.h<br>+++ b/src/mainboard/amd/dinar/rd890_cfg.h<br>@@ -28,10 +28,10 @@<br> * [12..15] - Sublink (1..2), If NB connected to full link than Sublink should be set to 0.<br> */<br> #ifndef DEFAULT_HT_PATH<br>-#if CONFIG_CPU_AMD_AGESA_FAMILY10<br>+#if IS_ENABLED(CONFIG_CPU_AMD_AGESA_FAMILY10)<br> #define DEFAULT_HT_PATH {0x0, 0x3}<br> #endif<br>-#if CONFIG_CPU_AMD_AGESA_FAMILY15<br>+#if IS_ENABLED(CONFIG_CPU_AMD_AGESA_FAMILY15)<br> #define DEFAULT_HT_PATH {0x0, 0x1}<br> #endif<br> #endif<br>diff --git a/src/mainboard/amd/dinar/sb700_cfg.h b/src/mainboard/amd/dinar/sb700_cfg.h<br>index 02c3934..1896d11 100644<br>--- a/src/mainboard/amd/dinar/sb700_cfg.h<br>+++ b/src/mainboard/amd/dinar/sb700_cfg.h<br>@@ -36,13 +36,13 @@<br> * before AGESA module get call.<br> */<br> #ifndef BIOS_SIZE<br>-#if CONFIG_COREBOOT_ROMSIZE_KB_1024<br>+#if IS_ENABLED(CONFIG_COREBOOT_ROMSIZE_KB_1024)<br> #define BIOS_SIZE BIOS_SIZE_1M<br>-#elif CONFIG_COREBOOT_ROMSIZE_KB_2048 == 1<br>+#elif IS_ENABLED(CONFIG_COREBOOT_ROMSIZE_KB_2048)<br> #define BIOS_SIZE BIOS_SIZE_2M<br>-#elif CONFIG_COREBOOT_ROMSIZE_KB_4096 == 1<br>+#elif IS_ENABLED(CONFIG_COREBOOT_ROMSIZE_KB_4096)<br> #define BIOS_SIZE BIOS_SIZE_4M<br>-#elif CONFIG_COREBOOT_ROMSIZE_KB_8192 == 1<br>+#elif IS_ENABLED(CONFIG_COREBOOT_ROMSIZE_KB_8192)<br> #define BIOS_SIZE BIOS_SIZE_8M<br> #endif<br> #endif<br>diff --git a/src/mainboard/amd/gardenia/BiosCallOuts.c b/src/mainboard/amd/gardenia/BiosCallOuts.c<br>index 23ce0c6..09cac71 100644<br>--- a/src/mainboard/amd/gardenia/BiosCallOuts.c<br>+++ b/src/mainboard/amd/gardenia/BiosCallOuts.c<br>@@ -100,7 +100,7 @@<br> #endif<br> <br> /* XHCI configuration */<br>-#if CONFIG_HUDSON_XHCI_ENABLE<br>+#if IS_ENABLED(CONFIG_HUDSON_XHCI_ENABLE)<br> FchParams_env->Usb.Xhci0Enable = TRUE;<br> #else<br> FchParams_env->Usb.Xhci0Enable = FALSE;<br>diff --git a/src/mainboard/amd/inagua/broadcom.c b/src/mainboard/amd/inagua/broadcom.c<br>index 9f140a2..f1c49d2 100644<br>--- a/src/mainboard/amd/inagua/broadcom.c<br>+++ b/src/mainboard/amd/inagua/broadcom.c<br>@@ -37,7 +37,7 @@<br> #define be(x) cpu_to_be32(x) //this is used a lot!<br> <br> /* C forces us to specify these before defining struct selfboot_patch :-( */<br>-#if !CONFIG_BOARD_LIPPERT_FRONTRUNNER_AF<br>+#if !IS_ENABLED(CONFIG_BOARD_LIPPERT_FRONTRUNNER_AF)<br> #define INIT1_LENGTH 9<br> #define INIT2_LENGTH 10<br> #define INIT3_LENGTH 3<br>@@ -179,7 +179,7 @@<br> .powerdown.padding = be16(0x0000),<br> <br> /* Only the lines below may be adapted to your needs ... */<br>-#if !CONFIG_BOARD_LIPPERT_FRONTRUNNER_AF<br>+#if !IS_ENABLED(CONFIG_BOARD_LIPPERT_FRONTRUNNER_AF)<br> .header.mac_addr = { 0x00, 0x10, 0x18, 0x00, 0x00, 0x00 }, //Broadcom<br> .header.subsys_device = be16(0x1699), //same as pci_device<br> .header.subsys_vendor = be16(0x14E4), //Broadcom<br>@@ -189,7 +189,7 @@<br> .header.subsys_vendor = be16(0x121D), //LiPPERT<br> #endif<br> .header.pci_device = be16(0x1699), //Broadcom 5785 with GbE PHY<br>-#if !CONFIG_BOARD_LIPPERT_FRONTRUNNER_AF<br>+#if !IS_ENABLED(CONFIG_BOARD_LIPPERT_FRONTRUNNER_AF)<br> .header.patch_version = be16(0x010B), //1.11 (Broadcom's sb5785m1.11)<br> #else<br> .header.patch_version = be16(0x110B), //1.11b, i.e. hacked :-)<br>@@ -208,7 +208,7 @@<br> * 1 X 0 | 0x330C5180 - - -<br> * 1 X 1 | 0x391C6140 - - -<br> */<br>-#if !CONFIG_BOARD_LIPPERT_FRONTRUNNER_AF<br>+#if !IS_ENABLED(CONFIG_BOARD_LIPPERT_FRONTRUNNER_AF)<br> .header.basic_config = be16(0x0404), //original for B50610<br> #else<br> .header.basic_config = be16(0x0604), //bit 9 set so not to mess up PHY regs, kept other bits unchanged<br>@@ -244,7 +244,7 @@<br> * was added, for reference see Broadcom's changelog.<br> */<br> .init.hunk1_code = {<br>-#if CONFIG_BOARD_LIPPERT_FRONTRUNNER_AF<br>+#if IS_ENABLED(CONFIG_BOARD_LIPPERT_FRONTRUNNER_AF)<br> be(0x082B8104), //CFR-AF: PHY0B: KSZ9021 select PHY104<br> be(0x082CF0F0), //CFR-AF: PHY0C: KSZ9021 clk/ctl skew (advised by Micrel)<br> be(0x082B8105), //CFR-AF: PHY0B: KSZ9021 select PHY105<br>@@ -258,7 +258,7 @@<br> <br> .init.hunk2_when = 0x30, //after global reset, PHY reset<br> .init.hunk2_code = {<br>-#if !CONFIG_BOARD_LIPPERT_FRONTRUNNER_AF<br>+#if !IS_ENABLED(CONFIG_BOARD_LIPPERT_FRONTRUNNER_AF)<br> be(0x08370F08), //v1.06 : PHY17: B50610 select reg. 08<br> be(0x08350001), //v1.06 : PHY15: B50610 slow link fix<br> be(0x08370F00), //v1.06 : PHY17: B50610 disable reg. 08<br>@@ -275,20 +275,20 @@<br> be(0xC1F03604), be(0xFFE0FFFF), be(0x00110000), //v1.08 : 3604.20-16: 10Mb clock = 12.5MHz<br> }, //-->INIT3_LENGTH!<br> <br>-#if !CONFIG_BOARD_LIPPERT_FRONTRUNNER_AF<br>+#if !IS_ENABLED(CONFIG_BOARD_LIPPERT_FRONTRUNNER_AF)<br> .init.hunk4_when = 0xD8, //original for B50610<br> #else<br> .init.hunk4_when = 0x80, //run last, after Linux' "ifconfig up"<br> #endif<br> .init.hunk4_code = {<br>-#if CONFIG_BOARD_LIPPERT_FRONTRUNNER_AF<br>+#if IS_ENABLED(CONFIG_BOARD_LIPPERT_FRONTRUNNER_AF)<br> be(0x083F4300), //CFR-AF: PHY1F: IRQ active high<br> be(0x083C0000), //CFR-AF: PHY1C: revert driver writes<br> be(0x08380000), //CFR-AF: PHY18|<br> be(0x083C0000), //CFR-AF: PHY1C|<br> #endif<br> be(0xCB0005A4), be(0xF7F0000C), //v1.01 : if 5A4.0 == 1 -->skip next 12 bytes<br>-#if !CONFIG_BOARD_LIPPERT_FRONTRUNNER_AF<br>+#if !IS_ENABLED(CONFIG_BOARD_LIPPERT_FRONTRUNNER_AF)<br> be(0xC61005A4), be(0x3210C500), //v1.01 : 5A4: PHY LED mode<br> #else<br> be(0xC61005A4), be(0x331C71CE), //CFR-AF: 5A4: fake LED mode<br>@@ -300,7 +300,7 @@<br> <br> .powerdown.hunk1_when = 0x50, //prior to IDDQ MAC<br> .powerdown.hunk1_code = {<br>-#if !CONFIG_BOARD_LIPPERT_FRONTRUNNER_AF<br>+#if !IS_ENABLED(CONFIG_BOARD_LIPPERT_FRONTRUNNER_AF)<br> be(0x083CB001), //v1.10 : PHY1C: IDDQ B50610 PHY<br> #endif<br> be(0xF7F30116), // IDDQ PHY<br>diff --git a/src/mainboard/amd/mahogany/romstage.c b/src/mainboard/amd/mahogany/romstage.c<br>index a8e54d5..86cb9ab 100644<br>--- a/src/mainboard/amd/mahogany/romstage.c<br>+++ b/src/mainboard/amd/mahogany/romstage.c<br>@@ -91,7 +91,7 @@<br> <br> setup_coherent_ht_domain();<br> <br>-#if CONFIG_LOGICAL_CPUS<br>+#if IS_ENABLED(CONFIG_LOGICAL_CPUS)<br> /* It is said that we should start core1 after all core0 launched */<br> wait_all_core0_started();<br> start_other_cores();<br>diff --git a/src/mainboard/amd/mahogany_fam10/romstage.c b/src/mainboard/amd/mahogany_fam10/romstage.c<br>index efb2885..0393822 100644<br>--- a/src/mainboard/amd/mahogany_fam10/romstage.c<br>+++ b/src/mainboard/amd/mahogany_fam10/romstage.c<br>@@ -141,7 +141,7 @@<br> */<br> wait_all_core0_started();<br> <br>- #if CONFIG_LOGICAL_CPUS<br>+ #if IS_ENABLED(CONFIG_LOGICAL_CPUS)<br> /* Core0 on each node is configured. Now setup any additional cores. */<br> printk(BIOS_DEBUG, "start_other_cores()\n");<br> start_other_cores(bsp_apicid);<br>@@ -155,7 +155,7 @@<br> rs780_early_setup();<br> sb7xx_51xx_early_setup();<br> <br>- #if CONFIG_SET_FIDVID<br>+ #if IS_ENABLED(CONFIG_SET_FIDVID)<br> msr = rdmsr(0xc0010071);<br> printk(BIOS_DEBUG, "\nBegin FIDVID MSR 0xc0010071 0x%08x 0x%08x\n", msr.hi, msr.lo);<br> <br>diff --git a/src/mainboard/amd/parmer/buildOpts.c b/src/mainboard/amd/parmer/buildOpts.c<br>index 8ba3c53..49a9feb 100644<br>--- a/src/mainboard/amd/parmer/buildOpts.c<br>+++ b/src/mainboard/amd/parmer/buildOpts.c<br>@@ -154,7 +154,7 @@<br> #define BLDCFG_LVDS_POWER_ON_SEQ_VARY_BL_TO_BLON 3<br> #define BLDCFG_LVDS_POWER_ON_SEQ_BLON_TO_VARY_BL 3<br> <br>-#if CONFIG_GFXUMA<br>+#if IS_ENABLED(CONFIG_GFXUMA)<br> #define BLDCFG_UMA_ALIGNMENT UMA_4MB_ALIGNED<br> #define BLDCFG_UMA_ALLOCATION_MODE UMA_SPECIFIED<br> //#define BLDCFG_UMA_ALLOCATION_SIZE 0x1000//0x1800//0x1000 /* (1000 << 16) = 256M*/<br>diff --git a/src/mainboard/amd/pistachio/romstage.c b/src/mainboard/amd/pistachio/romstage.c<br>index 2008619..7f04e7f 100644<br>--- a/src/mainboard/amd/pistachio/romstage.c<br>+++ b/src/mainboard/amd/pistachio/romstage.c<br>@@ -87,7 +87,7 @@<br> <br> setup_coherent_ht_domain();<br> <br>-#if CONFIG_LOGICAL_CPUS<br>+#if IS_ENABLED(CONFIG_LOGICAL_CPUS)<br> /* It is said that we should start core1 after all core0 launched */<br> wait_all_core0_started();<br> start_other_cores();<br>diff --git a/src/mainboard/amd/serengeti_cheetah/mptable.c b/src/mainboard/amd/serengeti_cheetah/mptable.c<br>index fc421a9..0210368 100644<br>--- a/src/mainboard/amd/serengeti_cheetah/mptable.c<br>+++ b/src/mainboard/amd/serengeti_cheetah/mptable.c<br>@@ -17,7 +17,7 @@<br> #include <device/pci.h><br> #include <string.h><br> #include <stdint.h><br>-#if CONFIG_LOGICAL_CPUS<br>+#if IS_ENABLED(CONFIG_LOGICAL_CPUS)<br> #include <cpu/amd/multicore.h><br> #endif<br> #include <cpu/amd/amdk8_sysconf.h><br>diff --git a/src/mainboard/amd/serengeti_cheetah/romstage.c b/src/mainboard/amd/serengeti_cheetah/romstage.c<br>index 73a1e9f..17ac940 100644<br>--- a/src/mainboard/amd/serengeti_cheetah/romstage.c<br>+++ b/src/mainboard/amd/serengeti_cheetah/romstage.c<br>@@ -104,7 +104,7 @@<br> struct sys_info *sysinfo = &sysinfo_car;<br> int needs_reset;<br> unsigned bsp_apicid = 0;<br>-#if CONFIG_SET_FIDVID<br>+#if IS_ENABLED(CONFIG_SET_FIDVID)<br> struct cpuid_result cpuid1;<br> #endif<br> <br>@@ -127,7 +127,7 @@<br> setup_coherent_ht_domain(); /* routing table and start other core0 */<br> <br> wait_all_core0_started();<br>-#if CONFIG_LOGICAL_CPUS<br>+#if IS_ENABLED(CONFIG_LOGICAL_CPUS)<br> /* It is said that we should start core1 after all core0 launched */<br> /* becase optimize_link_coherent_ht is moved out from setup_coherent_ht_domain,<br> * So here need to make sure last core0 is started, esp for two way system,<br>@@ -140,7 +140,7 @@<br> /* it will set up chains and store link pair for optimization later */<br> ht_setup_chains_x(sysinfo); /* it will init sblnk and sbbusn, nodes, sbdn */<br> <br>-#if CONFIG_SET_FIDVID<br>+#if IS_ENABLED(CONFIG_SET_FIDVID)<br> /* Check to see if processor is capable of changing FIDVID */<br> /* otherwise it will throw a GP# when reading FIDVID_STATUS */<br> cpuid1 = cpuid(0x80000007);<br>diff --git a/src/mainboard/amd/serengeti_cheetah_fam10/mptable.c b/src/mainboard/amd/serengeti_cheetah_fam10/mptable.c<br>index d800051..048e800 100644<br>--- a/src/mainboard/amd/serengeti_cheetah_fam10/mptable.c<br>+++ b/src/mainboard/amd/serengeti_cheetah_fam10/mptable.c<br>@@ -19,7 +19,7 @@<br> #include <device/pci.h><br> #include <string.h><br> #include <stdint.h><br>-#if CONFIG_LOGICAL_CPUS<br>+#if IS_ENABLED(CONFIG_LOGICAL_CPUS)<br> #include <cpu/amd/multicore.h><br> #endif<br> #include <cpu/amd/amdfam10_sysconf.h><br>diff --git a/src/mainboard/amd/serengeti_cheetah_fam10/romstage.c b/src/mainboard/amd/serengeti_cheetah_fam10/romstage.c<br>index 831e050..e130ebd 100644<br>--- a/src/mainboard/amd/serengeti_cheetah_fam10/romstage.c<br>+++ b/src/mainboard/amd/serengeti_cheetah_fam10/romstage.c<br>@@ -242,7 +242,7 @@<br> */<br> wait_all_core0_started();<br> <br>- #if CONFIG_LOGICAL_CPUS<br>+ #if IS_ENABLED(CONFIG_LOGICAL_CPUS)<br> /* Core0 on each node is configured. Now setup any additional cores. */<br> printk(BIOS_DEBUG, "start_other_cores()\n");<br> start_other_cores(bsp_apicid);<br>@@ -252,7 +252,7 @@<br> <br> post_code(0x38);<br> <br>- #if CONFIG_SET_FIDVID<br>+ #if IS_ENABLED(CONFIG_SET_FIDVID)<br> msr = rdmsr(0xc0010071);<br> printk(BIOS_DEBUG, "\nBegin FIDVID MSR 0xc0010071 0x%08x 0x%08x\n", msr.hi, msr.lo);<br> <br>diff --git a/src/mainboard/amd/thatcher/buildOpts.c b/src/mainboard/amd/thatcher/buildOpts.c<br>index 8ed3bf2..7bc5a77 100644<br>--- a/src/mainboard/amd/thatcher/buildOpts.c<br>+++ b/src/mainboard/amd/thatcher/buildOpts.c<br>@@ -154,7 +154,7 @@<br> #define BLDCFG_LVDS_POWER_ON_SEQ_VARY_BL_TO_BLON 3<br> #define BLDCFG_LVDS_POWER_ON_SEQ_BLON_TO_VARY_BL 3<br> <br>-#if CONFIG_GFXUMA<br>+#if IS_ENABLED(CONFIG_GFXUMA)<br> #define BLDCFG_UMA_ALIGNMENT UMA_4MB_ALIGNED<br> #define BLDCFG_UMA_ALLOCATION_MODE UMA_SPECIFIED<br> //#define BLDCFG_UMA_ALLOCATION_SIZE 0x1000//0x1800//0x1000 /* (1000 << 16) = 256M*/<br>diff --git a/src/mainboard/amd/tilapia_fam10/romstage.c b/src/mainboard/amd/tilapia_fam10/romstage.c<br>index 022e91d..92fee45 100644<br>--- a/src/mainboard/amd/tilapia_fam10/romstage.c<br>+++ b/src/mainboard/amd/tilapia_fam10/romstage.c<br>@@ -137,7 +137,7 @@<br> */<br> wait_all_core0_started();<br> <br>-#if CONFIG_LOGICAL_CPUS<br>+#if IS_ENABLED(CONFIG_LOGICAL_CPUS)<br> /* Core0 on each node is configured. Now setup any additional cores. */<br> printk(BIOS_DEBUG, "start_other_cores()\n");<br> start_other_cores(bsp_apicid);<br>@@ -151,7 +151,7 @@<br> rs780_early_setup();<br> sb7xx_51xx_early_setup();<br> <br>-#if CONFIG_SET_FIDVID<br>+#if IS_ENABLED(CONFIG_SET_FIDVID)<br> msr = rdmsr(0xc0010071);<br> printk(BIOS_DEBUG, "\nBegin FIDVID MSR 0xc0010071 0x%08x 0x%08x\n", msr.hi, msr.lo);<br> <br>diff --git a/src/mainboard/amd/torpedo/Oem.h b/src/mainboard/amd/torpedo/Oem.h<br>index 0910ddc..f8f9d80 100644<br>--- a/src/mainboard/amd/torpedo/Oem.h<br>+++ b/src/mainboard/amd/torpedo/Oem.h<br>@@ -16,7 +16,7 @@<br> #define BIOS_SIZE 0x04 //04 - 1MB<br> #endif<br> #define LEGACY_FREE 0x00<br>-#if !CONFIG_ONBOARD_USB30<br>+#if !IS_ENABLED(CONFIG_ONBOARD_USB30)<br> #define XHCI_SUPPORT 0x01<br> #endif<br> <br>diff --git a/src/mainboard/amd/torpedo/platform_cfg.h b/src/mainboard/amd/torpedo/platform_cfg.h<br>index 0713e41..72a97d1 100644<br>--- a/src/mainboard/amd/torpedo/platform_cfg.h<br>+++ b/src/mainboard/amd/torpedo/platform_cfg.h<br>@@ -294,7 +294,7 @@<br> #define INCHIP_USB_CINFIG 0x7F<br> #define INCHIP_USB_OHCI1_CINFIG 0x01<br> #define INCHIP_USB_OHCI2_CINFIG 0x01<br>-#if CONFIG_ONBOARD_USB30<br>+#if IS_ENABLED(CONFIG_ONBOARD_USB30)<br> #define INCHIP_USB_OHCI3_CINFIG 0x00<br> #else<br> #define INCHIP_USB_OHCI3_CINFIG 0x01<br>@@ -962,7 +962,7 @@<br> * @li <b>0</b> - Disable<br> * @li <b>1</b> - Enable<br> */<br>-#if CONFIG_ONBOARD_USB30<br>+#if IS_ENABLED(CONFIG_ONBOARD_USB30)<br> #define SB_XHCI_SWITCH 0<br> #else<br> #define SB_XHCI_SWITCH 1<br>diff --git a/src/mainboard/aopen/dxplplusu/romstage.c b/src/mainboard/aopen/dxplplusu/romstage.c<br>index 3fba1ad..f79d3d3 100644<br>--- a/src/mainboard/aopen/dxplplusu/romstage.c<br>+++ b/src/mainboard/aopen/dxplplusu/romstage.c<br>@@ -65,8 +65,8 @@<br> * is lost. Only return addresses from main() and<br> * scrub_ecc() are recovered to stack via xmm0-xmm3.<br> */<br>-#if CONFIG_HW_SCRUBBER<br>-#if !CONFIG_USBDEBUG_IN_ROMSTAGE<br>+#if IS_ENABLED(CONFIG_HW_SCRUBBER)<br>+#if !IS_ENABLED(CONFIG_USBDEBUG_IN_ROMSTAGE)<br> unsigned long ret_addr = (unsigned long)((unsigned long*)&bist - 1);<br> e7505_mch_scrub_ecc(ret_addr);<br> #endif<br>diff --git a/src/mainboard/apple/macbook21/gpio.c b/src/mainboard/apple/macbook21/gpio.c<br>index 53c5c96..19296a7 100644<br>--- a/src/mainboard/apple/macbook21/gpio.c<br>+++ b/src/mainboard/apple/macbook21/gpio.c<br>@@ -56,7 +56,8 @@<br> };<br> <br> static const struct pch_gpio_set1 pch_gpio_set1_level = {<br>-#if (CONFIG_BOARD_APPLE_MACBOOK11 || CONFIG_BOARD_APPLE_MACBOOK21)<br>+#if IS_ENABLED(CONFIG_BOARD_APPLE_MACBOOK11) || \<br>+ IS_ENABLED(CONFIG_BOARD_APPLE_MACBOOK21)<br> .gpio5 = GPIO_LEVEL_LOW,<br> #else /* CONFIG_BOARD_APPLE_IMAC52 */<br> .gpio5 = GPIO_LEVEL_HIGH,<br>@@ -71,7 +72,8 @@<br> static const struct pch_gpio_set1 pch_gpio_set1_invert = {<br> .gpio1 = GPIO_INVERT,<br> .gpio7 = GPIO_INVERT,<br>-#if (CONFIG_BOARD_APPLE_MACBOOK11 || CONFIG_BOARD_APPLE_MACBOOK21)<br>+#if IS_ENABLED(CONFIG_BOARD_APPLE_MACBOOK11) || \<br>+ IS_ENABLED(CONFIG_BOARD_APPLE_MACBOOK21)<br> .gpio13 = GPIO_INVERT,<br> #endif<br> };<br>@@ -80,7 +82,7 @@<br> };<br> <br> static const struct pch_gpio_set2 pch_gpio_set2_mode = {<br>-#if CONFIG_BOARD_APPLE_IMAC52<br>+#if IS_ENABLED(CONFIG_BOARD_APPLE_IMAC52)<br> .gpio35 = GPIO_MODE_GPIO,<br> #endif<br> .gpio38 = GPIO_MODE_GPIO,<br>@@ -89,7 +91,7 @@<br> };<br> <br> static const struct pch_gpio_set2 pch_gpio_set2_direction = {<br>-#if CONFIG_BOARD_APPLE_IMAC52<br>+#if IS_ENABLED(CONFIG_BOARD_APPLE_IMAC52)<br> .gpio35 = GPIO_DIR_OUTPUT,<br> #endif<br> .gpio38 = GPIO_DIR_OUTPUT,<br>@@ -98,7 +100,7 @@<br> };<br> <br> static const struct pch_gpio_set2 pch_gpio_set2_level = {<br>-#if CONFIG_BOARD_APPLE_IMAC52<br>+#if IS_ENABLED(CONFIG_BOARD_APPLE_IMAC52)<br> .gpio35 = GPIO_LEVEL_LOW,<br> #endif<br> .gpio38 = GPIO_LEVEL_HIGH,<br>diff --git a/src/mainboard/apple/macbook21/hda_verb.c b/src/mainboard/apple/macbook21/hda_verb.c<br>index e0fc92e..9ae5cf8 100644<br>--- a/src/mainboard/apple/macbook21/hda_verb.c<br>+++ b/src/mainboard/apple/macbook21/hda_verb.c<br>@@ -19,7 +19,8 @@<br> const u32 cim_verb_data[] = {<br> /* coreboot specific header */<br> 0x83847680, /* Codec Vendor / Device ID: SigmaTel STAC9221 A1 */<br>-#if CONFIG_BOARD_APPLE_MACBOOK11 || CONFIG_BOARD_APPLE_MACBOOK21<br>+#if IS_ENABLED(CONFIG_BOARD_APPLE_MACBOOK11) || \<br>+ IS_ENABLED(CONFIG_BOARD_APPLE_MACBOOK21)<br> 0x106b2200, /* Subsystem ID */<br> 0x0000000B, /* Number of 4 dword sets */<br> <br>diff --git a/src/mainboard/asrock/939a785gmh/romstage.c b/src/mainboard/asrock/939a785gmh/romstage.c<br>index bd74fde..c88f027 100644<br>--- a/src/mainboard/asrock/939a785gmh/romstage.c<br>+++ b/src/mainboard/asrock/939a785gmh/romstage.c<br>@@ -157,7 +157,7 @@<br> <br> setup_coherent_ht_domain();<br> <br>-#if CONFIG_LOGICAL_CPUS<br>+#if IS_ENABLED(CONFIG_LOGICAL_CPUS)<br> /* It is said that we should start core1 after all core0 launched */<br> wait_all_core0_started();<br> start_other_cores();<br>diff --git a/src/mainboard/asus/a8n_e/romstage.c b/src/mainboard/asus/a8n_e/romstage.c<br>index 5a3b1f6..dd76d8e 100644<br>--- a/src/mainboard/asus/a8n_e/romstage.c<br>+++ b/src/mainboard/asus/a8n_e/romstage.c<br>@@ -114,7 +114,7 @@<br> needs_reset = setup_coherent_ht_domain();<br> <br> wait_all_core0_started();<br>-#if CONFIG_LOGICAL_CPUS<br>+#if IS_ENABLED(CONFIG_LOGICAL_CPUS)<br> /* It is said that we should start core1 after all core0 launched. */<br> start_other_cores();<br> wait_all_other_cores_started(bsp_apicid);<br>diff --git a/src/mainboard/asus/a8v-e_deluxe/romstage.c b/src/mainboard/asus/a8v-e_deluxe/romstage.c<br>index a19b46a..7b27ed9 100644<br>--- a/src/mainboard/asus/a8v-e_deluxe/romstage.c<br>+++ b/src/mainboard/asus/a8v-e_deluxe/romstage.c<br>@@ -173,7 +173,7 @@<br> <br> printk(BIOS_INFO, "now booting... Core0 started\n");<br> <br>-#if CONFIG_LOGICAL_CPUS<br>+#if IS_ENABLED(CONFIG_LOGICAL_CPUS)<br> /* It is said that we should start core1 after all core0 launched. */<br> start_other_cores();<br> wait_all_other_cores_started(bsp_apicid);<br>diff --git a/src/mainboard/asus/a8v-e_se/romstage.c b/src/mainboard/asus/a8v-e_se/romstage.c<br>index 706b859..dbce83e 100644<br>--- a/src/mainboard/asus/a8v-e_se/romstage.c<br>+++ b/src/mainboard/asus/a8v-e_se/romstage.c<br>@@ -173,7 +173,7 @@<br> <br> printk(BIOS_INFO, "now booting... Core0 started\n");<br> <br>-#if CONFIG_LOGICAL_CPUS<br>+#if IS_ENABLED(CONFIG_LOGICAL_CPUS)<br> /* It is said that we should start core1 after all core0 launched. */<br> start_other_cores();<br> wait_all_other_cores_started(bsp_apicid);<br>diff --git a/src/mainboard/asus/f2a85-m/acpi/routing.asl b/src/mainboard/asus/f2a85-m/acpi/routing.asl<br>index cc36dcd..af8532f 100644<br>--- a/src/mainboard/asus/f2a85-m/acpi/routing.asl<br>+++ b/src/mainboard/asus/f2a85-m/acpi/routing.asl<br>@@ -46,7 +46,7 @@<br> /* Bus 0, Dev 7 - PCIe Bridge for x1 PCIe Slot */<br> /* Bus 0, Dev 8 - Southbridge port (normally hidden) */<br> <br>-#if CONFIG_BOARD_ASUS_F2A85_M_PRO<br>+#if IS_ENABLED(CONFIG_BOARD_ASUS_F2A85_M_PRO)<br> Package(){0x000FFFFF, 0, INTA, 0 },<br> Package(){0x000FFFFF, 1, INTB, 0 },<br> Package(){0x000FFFFF, 2, INTC, 0 },<br>diff --git a/src/mainboard/asus/f2a85-m/buildOpts.c b/src/mainboard/asus/f2a85-m/buildOpts.c<br>index e0a1ea4..ab9e151 100644<br>--- a/src/mainboard/asus/f2a85-m/buildOpts.c<br>+++ b/src/mainboard/asus/f2a85-m/buildOpts.c<br>@@ -168,7 +168,7 @@<br> #define BLDCFG_LVDS_POWER_ON_SEQ_VARY_BL_TO_BLON 3<br> #define BLDCFG_LVDS_POWER_ON_SEQ_BLON_TO_VARY_BL 3<br> <br>-#if CONFIG_GFXUMA<br>+#if IS_ENABLED(CONFIG_GFXUMA)<br> #define BLDCFG_UMA_ALIGNMENT UMA_4MB_ALIGNED<br> #define BLDCFG_UMA_ALLOCATION_MODE UMA_SPECIFIED<br> //#define BLDCFG_UMA_ALLOCATION_SIZE 0x1000//0x1800//0x1000 /* (1000 << 16) = 256M*/<br>diff --git a/src/mainboard/asus/k8v-x/romstage.c b/src/mainboard/asus/k8v-x/romstage.c<br>index 1df033a..8fad0b4 100644<br>--- a/src/mainboard/asus/k8v-x/romstage.c<br>+++ b/src/mainboard/asus/k8v-x/romstage.c<br>@@ -128,7 +128,7 @@<br> <br> printk(BIOS_INFO, "now booting... Core0 started\n");<br> <br>-#if CONFIG_LOGICAL_CPUS<br>+#if IS_ENABLED(CONFIG_LOGICAL_CPUS)<br> /* It is said that we should start core1 after all core0 launched. */<br> start_other_cores();<br> wait_all_other_cores_started(bsp_apicid);<br>diff --git a/src/mainboard/asus/kcma-d8/bootblock.c b/src/mainboard/asus/kcma-d8/bootblock.c<br>index 6f2c0a1..4e8a790 100644<br>--- a/src/mainboard/asus/kcma-d8/bootblock.c<br>+++ b/src/mainboard/asus/kcma-d8/bootblock.c<br>@@ -33,7 +33,7 @@<br> pci_io_write_config8(PCI_DEV(0, 0x14, 0), 0x56, byte);<br> recovery_enabled = (!(pci_io_read_config8(PCI_DEV(0, 0x14, 0), 0x57) & 0x1));<br> if (recovery_enabled) {<br>-#if CONFIG_USE_OPTION_TABLE<br>+#if IS_ENABLED(CONFIG_USE_OPTION_TABLE)<br> /* Clear NVRAM checksum */<br> for (addr = LB_CKS_RANGE_START; addr <= LB_CKS_RANGE_END; addr++) {<br> cmos_write(0x0, addr);<br>diff --git a/src/mainboard/asus/kfsn4-dre/bootblock.c b/src/mainboard/asus/kfsn4-dre/bootblock.c<br>index b25b34f..454443f 100644<br>--- a/src/mainboard/asus/kfsn4-dre/bootblock.c<br>+++ b/src/mainboard/asus/kfsn4-dre/bootblock.c<br>@@ -62,7 +62,7 @@<br> <br> recovery_enabled = bootblock_read_recovery_jumper(GPIO_DEV);<br> if (recovery_enabled) {<br>-#if CONFIG_USE_OPTION_TABLE<br>+#if IS_ENABLED(CONFIG_USE_OPTION_TABLE)<br> /* Clear NVRAM checksum */<br> for (addr = LB_CKS_RANGE_START; addr <= LB_CKS_RANGE_END; addr++) {<br> cmos_write(0x0, addr);<br>diff --git a/src/mainboard/asus/kfsn4-dre_k8/bootblock.c b/src/mainboard/asus/kfsn4-dre_k8/bootblock.c<br>index b25b34f..454443f 100644<br>--- a/src/mainboard/asus/kfsn4-dre_k8/bootblock.c<br>+++ b/src/mainboard/asus/kfsn4-dre_k8/bootblock.c<br>@@ -62,7 +62,7 @@<br> <br> recovery_enabled = bootblock_read_recovery_jumper(GPIO_DEV);<br> if (recovery_enabled) {<br>-#if CONFIG_USE_OPTION_TABLE<br>+#if IS_ENABLED(CONFIG_USE_OPTION_TABLE)<br> /* Clear NVRAM checksum */<br> for (addr = LB_CKS_RANGE_START; addr <= LB_CKS_RANGE_END; addr++) {<br> cmos_write(0x0, addr);<br>diff --git a/src/mainboard/asus/kfsn4-dre_k8/get_bus_conf.c b/src/mainboard/asus/kfsn4-dre_k8/get_bus_conf.c<br>index 101997a..6548d47 100644<br>--- a/src/mainboard/asus/kfsn4-dre_k8/get_bus_conf.c<br>+++ b/src/mainboard/asus/kfsn4-dre_k8/get_bus_conf.c<br>@@ -24,7 +24,7 @@<br> #include <string.h><br> #include <stdint.h><br> #include <stdlib.h><br>-#if CONFIG_LOGICAL_CPUS<br>+#if IS_ENABLED(CONFIG_LOGICAL_CPUS)<br> #include <cpu/amd/multicore.h><br> #endif<br> #include <stdlib.h><br>diff --git a/src/mainboard/asus/kgpe-d16/bootblock.c b/src/mainboard/asus/kgpe-d16/bootblock.c<br>index 6f2c0a1..4e8a790 100644<br>--- a/src/mainboard/asus/kgpe-d16/bootblock.c<br>+++ b/src/mainboard/asus/kgpe-d16/bootblock.c<br>@@ -33,7 +33,7 @@<br> pci_io_write_config8(PCI_DEV(0, 0x14, 0), 0x56, byte);<br> recovery_enabled = (!(pci_io_read_config8(PCI_DEV(0, 0x14, 0), 0x57) & 0x1));<br> if (recovery_enabled) {<br>-#if CONFIG_USE_OPTION_TABLE<br>+#if IS_ENABLED(CONFIG_USE_OPTION_TABLE)<br> /* Clear NVRAM checksum */<br> for (addr = LB_CKS_RANGE_START; addr <= LB_CKS_RANGE_END; addr++) {<br> cmos_write(0x0, addr);<br>diff --git a/src/mainboard/asus/m2n-e/romstage.c b/src/mainboard/asus/m2n-e/romstage.c<br>index 915ca84..7cfdcfb 100644<br>--- a/src/mainboard/asus/m2n-e/romstage.c<br>+++ b/src/mainboard/asus/m2n-e/romstage.c<br>@@ -134,7 +134,7 @@<br> setup_coherent_ht_domain(); /* Routing table and start other core0. */<br> wait_all_core0_started();<br> <br>-#if CONFIG_LOGICAL_CPUS<br>+#if IS_ENABLED(CONFIG_LOGICAL_CPUS)<br> /*<br> * It is said that we should start core1 after all core0 launched<br> * becase optimize_link_coherent_ht is moved out from<br>diff --git a/src/mainboard/asus/m2v-mx_se/romstage.c b/src/mainboard/asus/m2v-mx_se/romstage.c<br>index 13113b4..eebf96c 100644<br>--- a/src/mainboard/asus/m2v-mx_se/romstage.c<br>+++ b/src/mainboard/asus/m2v-mx_se/romstage.c<br>@@ -139,7 +139,7 @@<br> <br> printk(BIOS_INFO, "now booting... All core 0 started\n");<br> <br>-#if CONFIG_LOGICAL_CPUS<br>+#if IS_ENABLED(CONFIG_LOGICAL_CPUS)<br> /* It is said that we should start core1 after all core0 launched. */<br> start_other_cores();<br> wait_all_other_cores_started(bsp_apicid);<br>diff --git a/src/mainboard/asus/m2v/romstage.c b/src/mainboard/asus/m2v/romstage.c<br>index 61d7488..55d5aca 100644<br>--- a/src/mainboard/asus/m2v/romstage.c<br>+++ b/src/mainboard/asus/m2v/romstage.c<br>@@ -238,7 +238,7 @@<br> <br> printk(BIOS_INFO, "now booting... All core 0 started\n");<br> <br>-#if CONFIG_LOGICAL_CPUS<br>+#if IS_ENABLED(CONFIG_LOGICAL_CPUS)<br> /* It is said that we should start core1 after all core0 launched. */<br> start_other_cores();<br> wait_all_other_cores_started(bsp_apicid);<br>diff --git a/src/mainboard/asus/m4a78-em/romstage.c b/src/mainboard/asus/m4a78-em/romstage.c<br>index 1076bf6..3261fc7 100644<br>--- a/src/mainboard/asus/m4a78-em/romstage.c<br>+++ b/src/mainboard/asus/m4a78-em/romstage.c<br>@@ -141,7 +141,7 @@<br> */<br> wait_all_core0_started();<br> <br>- #if CONFIG_LOGICAL_CPUS<br>+ #if IS_ENABLED(CONFIG_LOGICAL_CPUS)<br> /* Core0 on each node is configured. Now setup any additional cores. */<br> printk(BIOS_DEBUG, "start_other_cores()\n");<br> start_other_cores(bsp_apicid);<br>@@ -155,7 +155,7 @@<br> rs780_early_setup();<br> sb7xx_51xx_early_setup();<br> <br>- #if CONFIG_SET_FIDVID<br>+ #if IS_ENABLED(CONFIG_SET_FIDVID)<br> msr = rdmsr(0xc0010071);<br> printk(BIOS_DEBUG, "\nBegin FIDVID MSR 0xc0010071 0x%08x 0x%08x\n", msr.hi, msr.lo);<br> <br>diff --git a/src/mainboard/asus/m4a785-m/romstage.c b/src/mainboard/asus/m4a785-m/romstage.c<br>index 40334d6..a97488e 100644<br>--- a/src/mainboard/asus/m4a785-m/romstage.c<br>+++ b/src/mainboard/asus/m4a785-m/romstage.c<br>@@ -142,7 +142,7 @@<br> */<br> wait_all_core0_started();<br> <br>- #if CONFIG_LOGICAL_CPUS<br>+ #if IS_ENABLED(CONFIG_LOGICAL_CPUS)<br> /* Core0 on each node is configured. Now setup any additional cores. */<br> printk(BIOS_DEBUG, "start_other_cores()\n");<br> start_other_cores(bsp_apicid);<br>@@ -156,7 +156,7 @@<br> rs780_early_setup();<br> sb7xx_51xx_early_setup();<br> <br>- #if CONFIG_SET_FIDVID<br>+ #if IS_ENABLED(CONFIG_SET_FIDVID)<br> msr = rdmsr(0xc0010071);<br> printk(BIOS_DEBUG, "\nBegin FIDVID MSR 0xc0010071 0x%08x 0x%08x\n", msr.hi, msr.lo);<br> <br>@@ -244,7 +244,7 @@<br> */<br> BOOL AMD_CB_ManualBUIDSwapList (u8 node, u8 link, const u8 **List)<br> {<br>-#if !CONFIG_BOARD_ASUS_M4A785TM<br>+#if !IS_ENABLED(CONFIG_BOARD_ASUS_M4A785TM)<br> static const u8 swaplist[] = { 0xFF, CONFIG_HT_CHAIN_UNITID_BASE, CONFIG_HT_CHAIN_END_UNITID_BASE, 0xFF };<br> /* If the BUID was adjusted in early_ht we need to do the manual override */<br> if ((CONFIG_HT_CHAIN_UNITID_BASE != 0) && (CONFIG_HT_CHAIN_END_UNITID_BASE != 0)) {<br>diff --git a/src/mainboard/asus/m5a88-v/get_bus_conf.c b/src/mainboard/asus/m5a88-v/get_bus_conf.c<br>index 5d32c3a..85daf69 100644<br>--- a/src/mainboard/asus/m5a88-v/get_bus_conf.c<br>+++ b/src/mainboard/asus/m5a88-v/get_bus_conf.c<br>@@ -21,7 +21,7 @@<br> #include <stdlib.h><br> #include <cpu/amd/multicore.h><br> #include <cpu/amd/amdfam10_sysconf.h><br>-#if CONFIG_AMD_SB_CIMX<br>+#if IS_ENABLED(CONFIG_AMD_SB_CIMX)<br> #include <sb_cimx.h><br> #endif<br> <br>@@ -128,7 +128,7 @@<br> apicid_base = CONFIG_MAX_PHYSICAL_CPUS;<br> apicid_sb800 = apicid_base + 0;<br> <br>-#if CONFIG_AMD_SB_CIMX<br>+#if IS_ENABLED(CONFIG_AMD_SB_CIMX)<br> sb_Late_Post();<br> #endif<br> }<br>diff --git a/src/mainboard/asus/m5a88-v/romstage.c b/src/mainboard/asus/m5a88-v/romstage.c<br>index d11f98a..4137e15 100644<br>--- a/src/mainboard/asus/m5a88-v/romstage.c<br>+++ b/src/mainboard/asus/m5a88-v/romstage.c<br>@@ -146,7 +146,7 @@<br> */<br> wait_all_core0_started();<br> <br>-#if CONFIG_LOGICAL_CPUS<br>+#if IS_ENABLED(CONFIG_LOGICAL_CPUS)<br> /* Core0 on each node is configured. Now setup any additional cores. */<br> printk(BIOS_DEBUG, "start_other_cores()\n");<br> start_other_cores(bsp_apicid);<br>@@ -160,7 +160,7 @@<br> rs780_early_setup();<br> sb800_early_setup();<br> <br>-#if CONFIG_SET_FIDVID<br>+#if IS_ENABLED(CONFIG_SET_FIDVID)<br> msr = rdmsr(0xc0010071);<br> printk(BIOS_DEBUG, "\nBegin FIDVID MSR 0xc0010071 0x%08x 0x%08x\n", msr.hi, msr.lo);<br> post_code(0x39);<br>diff --git a/src/mainboard/avalue/eax-785e/get_bus_conf.c b/src/mainboard/avalue/eax-785e/get_bus_conf.c<br>index 5d32c3a..85daf69 100644<br>--- a/src/mainboard/avalue/eax-785e/get_bus_conf.c<br>+++ b/src/mainboard/avalue/eax-785e/get_bus_conf.c<br>@@ -21,7 +21,7 @@<br> #include <stdlib.h><br> #include <cpu/amd/multicore.h><br> #include <cpu/amd/amdfam10_sysconf.h><br>-#if CONFIG_AMD_SB_CIMX<br>+#if IS_ENABLED(CONFIG_AMD_SB_CIMX)<br> #include <sb_cimx.h><br> #endif<br> <br>@@ -128,7 +128,7 @@<br> apicid_base = CONFIG_MAX_PHYSICAL_CPUS;<br> apicid_sb800 = apicid_base + 0;<br> <br>-#if CONFIG_AMD_SB_CIMX<br>+#if IS_ENABLED(CONFIG_AMD_SB_CIMX)<br> sb_Late_Post();<br> #endif<br> }<br>diff --git a/src/mainboard/avalue/eax-785e/romstage.c b/src/mainboard/avalue/eax-785e/romstage.c<br>index 4648310..70dcc40 100644<br>--- a/src/mainboard/avalue/eax-785e/romstage.c<br>+++ b/src/mainboard/avalue/eax-785e/romstage.c<br>@@ -144,7 +144,7 @@<br> */<br> wait_all_core0_started();<br> <br>-#if CONFIG_LOGICAL_CPUS<br>+#if IS_ENABLED(CONFIG_LOGICAL_CPUS)<br> /* Core0 on each node is configured. Now setup any additional cores. */<br> printk(BIOS_DEBUG, "start_other_cores()\n");<br> start_other_cores(bsp_apicid);<br>@@ -158,7 +158,7 @@<br> rs780_early_setup();<br> sb800_early_setup();<br> <br>-#if CONFIG_SET_FIDVID<br>+#if IS_ENABLED(CONFIG_SET_FIDVID)<br> msr = rdmsr(0xc0010071);<br> printk(BIOS_DEBUG, "\nBegin FIDVID MSR 0xc0010071 0x%08x 0x%08x\n", msr.hi, msr.lo);<br> post_code(0x39);<br>diff --git a/src/mainboard/broadcom/blast/mptable.c b/src/mainboard/broadcom/blast/mptable.c<br>index 81c3049..2417c96 100644<br>--- a/src/mainboard/broadcom/blast/mptable.c<br>+++ b/src/mainboard/broadcom/blast/mptable.c<br>@@ -4,7 +4,7 @@<br> #include <device/pci.h><br> #include <string.h><br> #include <stdint.h><br>-#if CONFIG_LOGICAL_CPUS<br>+#if IS_ENABLED(CONFIG_LOGICAL_CPUS)<br> #include <cpu/amd/multicore.h><br> #endif<br> #include <cpu/amd/amdk8_sysconf.h><br>diff --git a/src/mainboard/broadcom/blast/romstage.c b/src/mainboard/broadcom/blast/romstage.c<br>index f49f8d3..bb472fb 100644<br>--- a/src/mainboard/broadcom/blast/romstage.c<br>+++ b/src/mainboard/broadcom/blast/romstage.c<br>@@ -90,7 +90,7 @@<br> <br> needs_reset = setup_coherent_ht_domain();<br> <br>-#if CONFIG_LOGICAL_CPUS<br>+#if IS_ENABLED(CONFIG_LOGICAL_CPUS)<br> // It is said that we should start core1 after all core0 launched<br> wait_all_core0_started();<br> start_other_cores();<br>diff --git a/src/mainboard/dmp/vortex86ex/romstage.c b/src/mainboard/dmp/vortex86ex/romstage.c<br>index d2cc146..108cc1d 100644<br>--- a/src/mainboard/dmp/vortex86ex/romstage.c<br>+++ b/src/mainboard/dmp/vortex86ex/romstage.c<br>@@ -72,25 +72,25 @@<br> {<br> u32 powerdown_ctrl;<br> powerdown_ctrl = pci_read_config32(SB, 0xbc);<br>-#if CONFIG_TEMP_POWERDOWN<br>+#if IS_ENABLED(CONFIG_TEMP_POWERDOWN)<br> powerdown_ctrl |= (1 << 31);<br> #endif<br>-#if CONFIG_SATA_POWERDOWN<br>+#if IS_ENABLED(CONFIG_SATA_POWERDOWN)<br> powerdown_ctrl |= (1 << 30);<br> #endif<br>-#if CONFIG_ADC_POWERDOWN<br>+#if IS_ENABLED(CONFIG_ADC_POWERDOWN)<br> powerdown_ctrl |= (1 << 28);<br> #endif<br>-#if CONFIG_PCIE0_POWERDOWN<br>+#if IS_ENABLED(CONFIG_PCIE0_POWERDOWN)<br> powerdown_ctrl |= (1 << 13);<br> #endif<br>-#if CONFIG_MAC_POWERDOWN<br>+#if IS_ENABLED(CONFIG_MAC_POWERDOWN)<br> powerdown_ctrl |= (1 << 3);<br> #endif<br>-#if CONFIG_USB1_POWERDOWN<br>+#if IS_ENABLED(CONFIG_USB1_POWERDOWN)<br> powerdown_ctrl |= (1 << 1);<br> #endif<br>-#if CONFIG_IDE_POWERDOWN<br>+#if IS_ENABLED(CONFIG_IDE_POWERDOWN)<br> powerdown_ctrl |= (1 << 0);<br> #endif<br> pci_write_config32(SB, 0xbc, powerdown_ctrl);<br>@@ -169,16 +169,16 @@<br> <br> static void init_wdt1(void)<br> {<br>-#if CONFIG_WDT1_INITIALIZE<br>-#if CONFIG_WDT1_ENABLE<br>+#if IS_ENABLED(CONFIG_WDT1_INITIALIZE)<br>+#if IS_ENABLED(CONFIG_WDT1_ENABLE)<br> outb(0x1 << 6, 0xa8);<br> #endif<br> u8 wdt1_signal_reg = 0;<br>-#if CONFIG_WDT1_SINGAL_NMI<br>+#if IS_ENABLED(CONFIG_WDT1_SINGAL_NMI)<br> wdt1_signal_reg = 0x0c << 4;<br>-#elif CONFIG_WDT1_SIGNAL_RESET<br>+#elif IS_ENABLED(CONFIG_WDT1_SIGNAL_RESET)<br> wdt1_signal_reg = 0x0d << 4;<br>-#elif CONFIG_WDT1_SIGNAL_SMI<br>+#elif IS_ENABLED(CONFIG_WDT1_SIGNAL_SMI)<br> wdt1_signal_reg = 0x0e << 4;<br> #endif<br> outb(wdt1_signal_reg, 0xa9);<br>diff --git a/src/mainboard/emulation/qemu-i440fx/northbridge.c b/src/mainboard/emulation/qemu-i440fx/northbridge.c<br>index d465afe..18dcae3 100644<br>--- a/src/mainboard/emulation/qemu-i440fx/northbridge.c<br>+++ b/src/mainboard/emulation/qemu-i440fx/northbridge.c<br>@@ -167,7 +167,7 @@<br> IORESOURCE_ASSIGNED;<br> }<br> <br>-#if CONFIG_GENERATE_SMBIOS_TABLES<br>+#if IS_ENABLED(CONFIG_GENERATE_SMBIOS_TABLES)<br> static int qemu_get_smbios_data16(int handle, unsigned long *current)<br> {<br> struct smbios_type16 *t = (struct smbios_type16 *)*current;<br>@@ -231,7 +231,7 @@<br> .init = NULL,<br> .scan_bus = pci_domain_scan_bus,<br> .ops_pci_bus = pci_bus_default_ops,<br>-#if CONFIG_GENERATE_SMBIOS_TABLES<br>+#if IS_ENABLED(CONFIG_GENERATE_SMBIOS_TABLES)<br> .get_smbios_data = qemu_get_smbios_data,<br> #endif<br> };<br></pre><p>To view, visit <a href="https://review.coreboot.org/20342">change 20342</a>. To unsubscribe, visit <a href="https://review.coreboot.org/settings">settings</a>.</p><div itemscope itemtype="http://schema.org/EmailMessage"><div itemscope itemprop="action" itemtype="http://schema.org/ViewAction"><link itemprop="url" href="https://review.coreboot.org/20342"/><meta itemprop="name" content="View Change"/></div></div>
<div style="display:none"> Gerrit-Project: coreboot </div>
<div style="display:none"> Gerrit-Branch: master </div>
<div style="display:none"> Gerrit-MessageType: newchange </div>
<div style="display:none"> Gerrit-Change-Id: Icca8bac5e67f83dfc5a8f5ef1cb87c6432e0a236 </div>
<div style="display:none"> Gerrit-Change-Number: 20342 </div>
<div style="display:none"> Gerrit-PatchSet: 1 </div>
<div style="display:none"> Gerrit-Owner: Martin Roth <martinroth@google.com> </div>