<p>Shaunak Saha has uploaded this change for <strong>review</strong>.</p><p><a href="https://review.coreboot.org/20307">View Change</a></p><pre style="font-family: monospace,monospace; white-space: pre-wrap;">soc/intel/common: Use common PMC for SMM<br><br>Change-Id: I067b99415e882a24970140280d3b223eb1301e2d<br>Signed-off-by: Shaunak Saha <shaunak.saha@intel.com><br>---<br>M src/soc/intel/common/block/smm/smihandler.c<br>M src/soc/intel/common/block/smm/smm.c<br>2 files changed, 26 insertions(+), 24 deletions(-)<br><br></pre><pre style="font-family: monospace,monospace; white-space: pre-wrap;">git pull ssh://review.coreboot.org:29418/coreboot refs/changes/07/20307/1</pre><pre style="font-family: monospace,monospace; white-space: pre-wrap;">diff --git a/src/soc/intel/common/block/smm/smihandler.c b/src/soc/intel/common/block/smm/smihandler.c<br>index b620ff9..7a4be47 100644<br>--- a/src/soc/intel/common/block/smm/smihandler.c<br>+++ b/src/soc/intel/common/block/smm/smihandler.c<br>@@ -21,6 +21,7 @@<br> #include <cpu/x86/smm.h><br> #include <device/pci_def.h><br> #include <elog.h><br>+#include <intelblocks/pmclib.h><br> #include <intelblocks/smihandler.h><br> #include <soc/nvs.h><br> #include <soc/pm.h><br>@@ -73,7 +74,7 @@<br> /* Inherited from cpu/x86/smm.h resulting in a different signature */<br> void southbridge_smi_set_eos(void)<br> {<br>- enable_smi(EOS);<br>+ pmc_enable_smi(EOS);<br> }<br> <br> struct global_nvs_t *smm_get_gnvs(void)<br>@@ -135,7 +136,7 @@<br> uint8_t slp_typ;<br> <br> /* First, disable further SMIs */<br>- disable_smi(SLP_SMI_EN);<br>+ pmc_disable_smi(SLP_SMI_EN);<br> /* Figure out SLP_TYP */<br> reg32 = inl(ACPI_BASE_ADDRESS + PM1_CNT);<br> printk(BIOS_SPEW, "SMI#: SLP = 0x%08x\n", reg32);<br>@@ -149,7 +150,7 @@<br> elog_add_event_byte(ELOG_TYPE_ACPI_ENTER, slp_typ);<br> <br> /* Clear pending GPE events */<br>- clear_gpe_status();<br>+ pmc_clear_gpe_status();<br> <br> /* Next, do the deed. */<br> <br>@@ -170,7 +171,7 @@<br> printk(BIOS_DEBUG, "SMI#: Entering S5 (Soft Power off)\n");<br> <br> /* Disable all GPE */<br>- disable_all_gpe();<br>+ pmc_disable_all_gpe();<br> /* also iterates over all bridges on bus 0 */<br> busmaster_disable_on_bus(0);<br> break;<br>@@ -180,7 +181,7 @@<br> }<br> <br> /* Clear the gpio gpe0 status bits in ACPI registers */<br>- clear_gpi_gpe_sts();<br>+ pmc_clear_gpi_gpe_sts();<br> <br> /* Tri-state specific GPIOS to avoid leakage during S3/S5 */<br> <br>@@ -189,7 +190,7 @@<br> * event again. We need to set BIT13 (SLP_EN) though to make the<br> * sleep happen.<br> */<br>- enable_pm1_control(SLP_EN);<br>+ pmc_enable_pm1_control(SLP_EN);<br> <br> /* Make sure to stop executing code here for S3/S4/S5 */<br> if (slp_typ >= ACPI_S3)<br>@@ -203,7 +204,7 @@<br> reg32 = inl(ACPI_BASE_ADDRESS + PM1_CNT);<br> if (reg32 & SCI_EN) {<br> /* The OS is not an ACPI OS, so we set the state to S0 */<br>- disable_pm1_control(SLP_EN | SLP_TYP);<br>+ pmc_disable_pm1_control(SLP_EN | SLP_TYP);<br> }<br> }<br> <br>@@ -269,11 +270,11 @@<br> printk(BIOS_DEBUG, "P-state control\n");<br> break;<br> case APM_CNT_ACPI_DISABLE:<br>- disable_pm1_control(SCI_EN);<br>+ pmc_disable_pm1_control(SCI_EN);<br> printk(BIOS_DEBUG, "SMI#: ACPI disabled.\n");<br> break;<br> case APM_CNT_ACPI_ENABLE:<br>- enable_pm1_control(SCI_EN);<br>+ pmc_enable_pm1_control(SCI_EN);<br> printk(BIOS_DEBUG, "SMI#: ACPI enabled.\n");<br> break;<br> case APM_CNT_GNVS_UPDATE:<br>@@ -306,7 +307,7 @@<br> void smihandler_southbridge_pm1(<br> const struct smm_save_state_ops *save_state_ops)<br> {<br>- uint16_t pm1_sts = clear_pm1_status();<br>+ uint16_t pm1_sts = pmc_clear_pm1_status();<br> <br> /*<br> * While OSPM is not active, poweroff immediately<br>@@ -316,21 +317,21 @@<br> /* power button pressed */<br> if (IS_ENABLED(CONFIG_ELOG_GSMI))<br> elog_add_event(ELOG_TYPE_POWER_BUTTON);<br>- disable_pm1_control(-1UL);<br>- enable_pm1_control(SLP_EN | (SLP_TYP_S5 << SLP_TYP_SHIFT));<br>+ pmc_disable_pm1_control(-1UL);<br>+ pmc_enable_pm1_control(SLP_EN | (SLP_TYP_S5 << SLP_TYP_SHIFT));<br> }<br> }<br> <br> void smihandler_southbridge_gpe0(<br> const struct smm_save_state_ops *save_state_ops)<br> {<br>- clear_gpe_status();<br>+ pmc_clear_gpe_status();<br> }<br> <br> void smihandler_southbridge_tco(<br> const struct smm_save_state_ops *save_state_ops)<br> {<br>- uint32_t tco_sts = clear_tco_status();<br>+ uint32_t tco_sts = pmc_clear_tco_status();<br> <br> /* Any TCO event? */<br> if (!tco_sts)<br>@@ -347,7 +348,7 @@<br> {<br> uint32_t reg32;<br> <br>- reg32 = get_smi_en();<br>+ reg32 = pmc_get_smi_en();<br> <br> /* Are periodic SMIs enabled? */<br> if ((reg32 & PERIODIC_EN) == 0)<br>@@ -365,7 +366,7 @@<br> * We need to clear the SMI status registers, or we won't see what's<br> * happening in the following calls.<br> */<br>- smi_sts = clear_smi_status();<br>+ smi_sts = pmc_clear_smi_status();<br> <br> save_state_ops = get_smm_save_state_ops();<br> <br>diff --git a/src/soc/intel/common/block/smm/smm.c b/src/soc/intel/common/block/smm/smm.c<br>index ab60af6..41f3426 100644<br>--- a/src/soc/intel/common/block/smm/smm.c<br>+++ b/src/soc/intel/common/block/smm/smm.c<br>@@ -17,6 +17,7 @@<br> <br> #include <console/console.h><br> #include <cpu/x86/smm.h><br>+#include <intelblocks/pmclib.h><br> #include <intelblocks/smm.h><br> #include <soc/pm.h><br> <br>@@ -24,24 +25,24 @@<br> {<br> printk(BIOS_DEBUG, "Clearing SMI status registers\n");<br> <br>- if (get_smi_en() & APMC_EN) {<br>+ if (pmc_get_smi_en() & APMC_EN) {<br> printk(BIOS_INFO, "SMI# handler already enabled?\n");<br> return;<br> }<br> <br> /* Dump and clear status registers */<br>- clear_smi_status();<br>- clear_pm1_status();<br>- clear_tco_status();<br>- clear_gpe_status();<br>+ pmc_clear_smi_status();<br>+ pmc_clear_pm1_status();<br>+ pmc_clear_tco_status();<br>+ pmc_clear_gpe_status();<br> }<br> <br> void smm_southbridge_enable(void)<br> {<br> printk(BIOS_DEBUG, "Enabling SMIs.\n");<br> /* Configure events */<br>- enable_pm1(PWRBTN_EN | GBL_EN);<br>- disable_gpe(PME_B0_EN);<br>+ pmc_enable_pm1(PWRBTN_EN | GBL_EN);<br>+ pmc_disable_gpe(PME_B0_EN);<br> <br> /*<br> * Enable SMI generation:<br>@@ -55,7 +56,7 @@<br> */<br> <br> /* Enable SMI generation: */<br>- enable_smi(ENABLE_SMI_PARAMS);<br>+ pmc_enable_smi(ENABLE_SMI_PARAMS);<br> }<br> <br> void smm_setup_structures(void *gnvs, void *tcg, void *smi1)<br></pre><p>To view, visit <a href="https://review.coreboot.org/20307">change 20307</a>. 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<div style="display:none"> Gerrit-Project: coreboot </div>
<div style="display:none"> Gerrit-Branch: master </div>
<div style="display:none"> Gerrit-MessageType: newchange </div>
<div style="display:none"> Gerrit-Change-Id: I067b99415e882a24970140280d3b223eb1301e2d </div>
<div style="display:none"> Gerrit-Change-Number: 20307 </div>
<div style="display:none"> Gerrit-PatchSet: 1 </div>
<div style="display:none"> Gerrit-Owner: Shaunak Saha <shaunak.saha@intel.com> </div>